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madsilicon |
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-- RV01: simulation & synthesis VHDL files --
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-----------------------------------------------------
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This folder includes all VHDL source files required
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by RV01 core.
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VHDL packages (stored in RV01_*_pkg.vhd files) are
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used to define data types and constants that are not
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user-modifiable (like, for instance, word width).
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All parameters that are user-modifiable get passed
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through top-level module generics, in order to allow
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every core instance to be configured independently
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from the other ones.
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The files actually needed to perform a simulation or
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synthesis run depend by the core configuration
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specified through the top-level module generics.
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File RV01_jrpu.vhd, for instance, is needed only if
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generic JRPU_PRESENT is set to '1'.
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The modules RV01_ST_CHECKER, RV01_WB_CHECKER and
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RV01_STATS are referenced by module RV01_CPU_2W_P6
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but are not actually needed, as their instantiation
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is disabled by generic SIMULATION_ONLY being set to
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'0', as required by core documentation.
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If simulation/synthesis tool complains about these
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modules to be missing, please check generic
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SIMULATION_ONLY setting.
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The RV01 top-level module is RV01_TOP from file
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RV01_top.vhd.
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An alternative top-level module is RV01_TOP_NOHOST
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from file RV01_top_nohost.vhd.
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This module exists mainly as a debugging and
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simulation aid, it consists of an instance of the
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top-level module RV01_TOP with the MTOHOST_o output
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looping back to the MFROMHOST_i and EI_REQ_i inputs.
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This arrangement allows to simulate the host interface
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and, to some degree, PLIC module operations without
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additional logic.
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All module and signal names use uppercase letters only,
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except for the suffixes described below here.
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Signals input to a module have a "_i" suffix appended
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to their name, signals output from a module have a "_o"
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suffix, while signals internal to a module and driven
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by a register, have a "_q" suffix. Signals names without
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one of these suffixes are internal to a module and
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generated by combinatorial logic.
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