Subversion Repositories rv01_riscv_core

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-- Copyright (C) 2016 Stefano Tonello                          --

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-- RV01 Control/Debug Common Output mux

---------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

library work;

use work.RV01_CONSTS_PKG.all;

use work.RV01_TYPES_PKG.all;

use work.RV01_IDEC_PKG.all;

entity RV01_CDCOMUX is

  generic(

    DMP : std_logic := '0'

  );

  port(

    CLK_i : in std_logic;

    HCSR_i : in std_logic;

    HCSRQ_i : in SDWORD_T;

    CSRQ_i : in SDWORD_T;

    HILLG_i : in std_logic;

    ILLG_i : in std_logic;

    CP_ADR_MSB_i : in std_logic;

    HCP_i : in std_logic;

    HCPQ_i : in std_logic_vector(SDLEN-1 downto 0);

    CPQ_i : in std_logic_vector(SDLEN-1 downto 0);

    DCPQ_i : in std_logic_vector(SDLEN-1 downto 0);

    STRT_i : in std_logic;

    DRSM_i : in std_logic;

    DPC_i : in ADR_T;

    STRTPC_i : in ADR_T;

    ILLG_o : out std_logic;

    CSRU_RES_o : out SDWORD_T;

    CP_Q_o : out std_logic_vector(SDLEN-1 downto 0);

    STRT_o : out std_logic;

    STRTPC_o : out ADR_T

  );

end RV01_CDCOMUX;

architecture ARC of RV01_CDCOMUX is

  signal CSRQ_q : SDWORD_T;

  signal ILLG_q : std_logic;

  signal CP_ADR_MSB_q : std_logic;

  signal CPQ_q : std_logic_vector(SDLEN-1 downto 0);

begin

  -- Mux CSR output data and illegal CSR

  -- instruction flags from CSRU and HLTU.

  process(CLK_i)

  begin

    if(CLK_i = '1' and CLK_i'event) then

      if(HCSR_i = '1') then

        CSRQ_q <= HCSRQ_i;

      else

        CSRQ_q <= CSRQ_i;

      end if;

      ILLG_q <= HILLG_i and ILLG_i;

    end if;

  end process;

  ILLG_o <= ILLG_q;

  CSRU_RES_o <= CSRQ_q;

  -- Mux control port output data from

  -- CSRU, HLTU and DBGU.

  process(CLK_i)

  begin

    if(CLK_i = '1' and CLK_i'event) then

      CP_ADR_MSB_q <= CP_ADR_MSB_i;

    end if;

  end process;

  process(CLK_i)

  begin

    if(CLK_i = '1' and CLK_i'event) then

      if(CP_ADR_MSB_q = '1') then

        if(HCP_i = '1') then

          CPQ_q <= HCPQ_i;

        else

          CPQ_q <= CPQ_i;

        end if;

      else

        CPQ_q <= DCPQ_i;

      end if;

    end if;

  end process;

  CP_Q_o <= CPQ_q;

  STRT_o <= STRT_i or DRSM_i;

  STRTPC_o <= DPC_i when (DMP = '1') else STRTPC_i;

end ARC;