Subversion Repositories rv01_riscv_core

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-- Copyright (C) 2015 Stefano Tonello                          --

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-- RV01 3:2 compressor

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library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

entity RV01_COMP32 is

  port(

    A_i : in std_logic_vector(3-1 downto 0);

    S_o : out std_logic;

    C_o : out std_logic

  );

end RV01_COMP32;

architecture ARC of RV01_COMP32 is

  signal UA,UB,CS : unsigned(3-1 downto 0);

begin

  -- A complicated way of calculating A_i(0) + A_i(1) + A_i(2)

  -- (trying to force synthesis tools to infer a single full

  -- adder).

  UA(0) <= A_i(2);

  UA(1) <= A_i(0);

  UA(2) <= '0';

  UB(0) <= '1';

  UB(1) <= A_i(1);

  UB(2) <= '0';

  CS <= UA + UB;

  S_o <= CS(1);

  C_o <= CS(2);

end ARC;