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-----------------------------------------------------------------
--                                                             --
-----------------------------------------------------------------
--                                                             --
-- Copyright (C) 2017 Stefano Tonello                          --
--                                                             --
-- This source file may be used and distributed without        --
-- restriction provided that this copyright statement is not   --
-- removed from the file and that any derivative work contains --
-- the original copyright notice and the associated disclaimer.--
--                                                             --
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY         --
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   --
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   --
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      --
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         --
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    --
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   --
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        --
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  --
-- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  --
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  --
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
-- POSSIBILITY OF SUCH DAMAGE.                                 --
--                                                             --
-----------------------------------------------------------------
 
---------------------------------------------------------------
-- RV01 CPU module
---------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use STD.textio.all;
 
library work;
use work.RV01_CONSTS_PKG.all;
use work.RV01_TYPES_PKG.all;
use WORK.RV01_FUNCS_PKG.all;
use WORK.RV01_ARITH_PKG.all;
use work.RV01_IDEC_PKG.all;
use WORK.RV01_OP_PKG.all;
use WORK.RV01_CSR_PKG.all;
 
entity RV01_CPU_2W is
  generic(
    -- synthesis translate_off
    ST_FILENAME : string := "NONE";
    WB_FILENAME : string := "NONE";
    -- synthesis translate_on
    IMEM_SIZE : natural := 1024*32; -- 128Kb
    DMEM_SIZE : natural := 1024*16; -- 64Kb
    IMEM_LOWM : std_logic := '1';
    BHT_SIZE : natural := 256;
    CFG_FLAGS : std_logic_vector(16-1 downto 0) := "00000000"&"01100111";
    SIMULATION_ONLY : std_logic := '1'
  );
  port(
    CLK_i : in std_logic; -- clock
    RST_i : in std_logic; -- reset
    -- Instruction memory interface
    INSTR_i : in std_logic_vector(ILEN*2-1 downto 0); -- two instructions!
    -- Data memory interface
    DDAT0_i : in std_logic_vector(SDLEN-1 downto 0); -- data port #0 data-in
    DDAT1_i : in std_logic_vector(SDLEN-1 downto 0); -- data port #1 data-in
    IADR_ERR_i : in std_logic; -- instr. port address error
    DADR0_ERR_i : in std_logic; -- data port #0 address error 
    DADR1_ERR_i : in std_logic; -- data port #1 address error
    IDADR_CFLT_i : in std_logic; -- address conflict error
    -- Check enable (simulation only)
    CHK_ENB_i : in std_logic;
    -- External Interrupt (from PLIC)
    EXT_INT_i : in std_logic;
    -- Host interface
    MFROMHOST_WE_i : in std_logic; -- MFROMHOST write-enable
    MFROMHOST_i : in std_logic_vector(SDLEN-1 downto 0); -- MFROMHOST data-in
    -- Control Port
    CP_RE_i : in std_logic; -- CP read-enable
    CP_WE_i : in std_logic; -- CP write-enable
    CP_ADR_i : in std_logic_vector(17-1 downto 0); -- CP address
    CP_D_i : in std_logic_vector(SDLEN-1 downto 0); -- CP data-in
 
    HALT_o : out std_logic; -- halt flag
    -- Instruction memory interface
    IADR_o : out unsigned(ALEN-1 downto 0); -- instr. port address
    -- Data memory interface
    DRE_o : out std_logic_vector(2-1 downto 0); -- data port #0/1 read-enable
    DWE0_o : out std_logic; -- data port #0 write-enable
    DBE_o : out std_logic_vector(4-1 downto 0); -- data port #0 byte-enable
    DADR0_o : out unsigned(ALEN-1 downto 0); -- data port #0 address
    DADR1_o : out unsigned(ALEN-1 downto 0); -- data port #1 address
    DIADR0_o : out unsigned(ALEN-1 downto 0); -- data port #0 address
    DIADR1_o : out unsigned(ALEN-1 downto 0); -- data port #1 address
    DIMS_o : out std_logic_vector(2-1 downto 0); -- data port #0/1 mem. select
    DDAT0_o : out std_logic_vector(SDLEN-1 downto 0); -- data port #0 data-out
    -- Host interface
    MTOHOST_OE_o : out std_logic; -- MTOHOST output-enable
    MTOHOST_o : out std_logic_vector(SDLEN-1 downto 0); -- MTOHOST data-out
    -- Control port
    CP_Q_o : out std_logic_vector(SDLEN-1 downto 0) -- CP data-out
  );
end RV01_CPU_2W;
 
architecture ARC of RV01_CPU_2W is
 
  constant SZERO : SDWORD_T := (others => '0');
  constant LZERO : LDWORD_T := (others => '0');
 
  constant PARALLEL_EXECUTION_ENABLED : std_logic := CFG_FLAGS(0);
  constant DELAYED_EXECUTION_ENABLED : std_logic := CFG_FLAGS(1);
  constant BRANCH_PREDICTION_ENABLED : std_logic := CFG_FLAGS(2);
  constant JALR_PREDICTION_ENABLED : std_logic := CFG_FLAGS(3);
  constant FPU_PRESENT : std_logic := CFG_FLAGS(4);
  constant DM_PRESENT : std_logic := CFG_FLAGS(5);
 
  -- number of (superscalar) ways
  constant NW : natural := 2;
 
  component RV01_FTCHLOG_1W is
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      STRT_i : in std_logic;
      STRTPC_i : in ADR_T;
      HALT_i : in std_logic;
      BJX_i : in std_logic;
      BJTA_i : in ADR_T;
      PBX_i : in std_logic;
      PBTA_i : in ADR_T;
      KLL1_i : in std_logic;
      PJRX_i : std_logic;
      PJRTA_i : in ADR_T;
      EXCP_i : in std_logic;
      ERET_i : in std_logic;
      RFTCH_i : in std_logic;
      ETVA_i : in ADR_T;
      PSTALL_i : in std_logic;
      DHALT_i : in std_logic;
 
      IFV_o : out std_logic;
      IADR0_o : out ADR_T;
      IADR_MIS_o : out std_logic
    );
  end component;
 
  component RV01_FTCHLOG_2W is
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      STRT_i : in std_logic;
      STRTPC_i : in ADR_T;
      HALT_i : in std_logic;
      BJX_i : in std_logic;
      BJTA_i : in ADR_T;
      PBX_i : in std_logic;
      PBTA_i : in ADR_T;
      KLL1_i : in std_logic;
      PJRX_i : in std_logic;
      PJRTA_i : in ADR_T;
      EXCP_i : in std_logic;
      ERET_i : in std_logic;
      RFTCH_i : in std_logic;
      ETVA_i : in ADR_T;
      PSTALL_i : in std_logic;
      DHALT_i : in std_logic;
 
      IFV_o : out std_logic_vector(2-1 downto 0);
      IADR0_o : out ADR_T;
      IADR1_o : out ADR_T;
      IADR_MIS_o : out std_logic
    );
  end component;
 
  component RV01_IFQ is
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      ID_HALT_i : in std_logic;
      IX_BJX_i : in std_logic;
      ID_ISSUE_i : in std_logic_vector(2-1 downto 0);
      IF_V_i : in std_logic_vector(2-1 downto 0);
      IF_PC0_i : in unsigned(ALEN-1 downto 0);
      IF_PC1_i : in unsigned(ALEN-1 downto 0);
      IF_INSTR0_i : in std_logic_vector(ILEN-1 downto 0);
      IF_INSTR1_i : in std_logic_vector(ILEN-1 downto 0);
      IF_DEC_INSTR0_i : in DEC_INSTR_T;
      IF_DEC_INSTR1_i : in DEC_INSTR_T;
      IF_OPA_PC0_i : in std_logic;
      IF_OPA_PC1_i : in std_logic;
      IF_OPB_IMM0_i : in std_logic;
      IF_OPB_IMM1_i : in std_logic;
      IF_BPVD0_i : in std_logic_vector(3-1 downto 0);
      IF_BPVD1_i : in std_logic_vector(3-1 downto 0);
 
      PSTALL_o : out std_logic;
      ID_V_o : out std_logic_vector(2-1 downto 0);
      ID_PC0_o : out unsigned(ALEN-1 downto 0);
      ID_PC1_o : out unsigned(ALEN-1 downto 0);
      ID_INSTR0_o : out std_logic_vector(ILEN-1 downto 0);
      ID_INSTR1_o : out std_logic_vector(ILEN-1 downto 0);
      ID_DEC_INSTR0_o : out DEC_INSTR_T;
      ID_DEC_INSTR1_o : out DEC_INSTR_T;
      ID_OPA_PC0_o : out std_logic;
      ID_OPA_PC1_o : out std_logic;
      ID_OPB_IMM0_o : out std_logic;
      ID_OPB_IMM1_o : out std_logic;
      ID_BPVD0_o : out std_logic_vector(3-1 downto 0);
      ID_BPVD1_o : out std_logic_vector(3-1 downto 0)
    );
  end component;
 
  component RV01_IDEC is
    port(
      INSTR_i : in std_logic_vector(ILEN-1 downto 0);
      IADR_MIS_i : in std_logic;
      IADR_ERR_i : in std_logic;
 
      OPA_PC_o : out std_logic;
      OPB_IMM_o : out std_logic;
      DEC_INSTR_o : out DEC_INSTR_T
    );
  end component;
 
  component RV01_PXLOG is
    port(
      ID_INSTR0_i : in DEC_INSTR_T;
      ID_INSTR1_i : in DEC_INSTR_T;
      ID_V_i : in std_logic_vector(2-1 downto 0);
      ID_FWDE_i : in std_logic_vector(2-1 downto 0);
 
      PXE1_o : out std_logic
    );
  end component;
 
  component RV01_ISSLOG is
    generic(
      NW : natural := 2
    );
    port(
      V_i : in std_logic_vector(NW-1 downto 0);
      BJX_i : in std_logic;
      PC1_i : in ADR_T;
      PS_i : in std_logic_vector(NW-1 downto 0);
      SBF_i : in std_logic;
      DIV_STRT_i : in std_logic;
      DIV_BSY_i : in std_logic;
      SEQX_i : in std_logic;
      PXE_i : in std_logic;
      PXE1_i : in std_logic;
      STEP_i : in std_logic;
      PSLP_i : in std_logic;
 
      V_o : out std_logic_vector(NW-1 downto 0);
      JLRA_o : out ADR_VEC_T(NW-1 downto 0);
      ISSUE_o : out std_logic_vector(NW-1 downto 0)
    );
  end component;
 
  component RV01_PIPE_A_DEC is
    port(
      INSTR_i : in DEC_INSTR_T;
 
      FWDE_o : out std_logic;
      SEL_o :  out std_logic_vector(4-1 downto 0)
    );
  end component;
 
  component RV01_FWDLOG_2W_P6 is
    port(
      ID_RX_i : in RID_T;
      ID_RRX_i : in std_logic;
      IX1_INSTR0_i : in DEC_INSTR_T;
      IX2_INSTR0_i : in DEC_INSTR_T;
      IX3_INSTR0_i : in DEC_INSTR_T;
      IX1_INSTR1_i : in DEC_INSTR_T;
      IX2_INSTR1_i : in DEC_INSTR_T;
      IX3_INSTR1_i : in DEC_INSTR_T;
      IX1_PA_RES0_i : in SDWORD_T;
      IX1_PA_RES1_i : in SDWORD_T;
      IX2_PA_RES0_i : in SDWORD_T;
      IX2_PA_RES1_i : in SDWORD_T;
      IX3_PA_RES0_i : in SDWORD_T;
      IX3_PA_RES1_i : in SDWORD_T;
      ID_OPX_NOFWD_i : in SDWORD_T;
      IX1_V_i : in std_logic_vector(2-1 downto 0);
      IX2_V_i : in std_logic_vector(2-1 downto 0);
      IX3_V_i : in std_logic_vector(2-1 downto 0);
      IX1_FWDE_i : in std_logic_vector(2-1 downto 0);
      IX2_FWDE_i : in std_logic_vector(2-1 downto 0);
      IX3_FWDE_i : in std_logic_vector(2-1 downto 0);
      NOREGS_i : in std_logic;
      NOREGD_i : in SDWORD_T;
 
      ID_OPX_o : out SDWORD_T
    );
  end component;
 
  component RV01_PIPE_B is
    port(
      CLK_i : in std_logic;
      OP_i :  in ALU_OP_T;
      SU_i : in std_logic;
      PC0_i : in unsigned(SDLEN-1 downto 0);
      PC1_i : in unsigned(SDLEN-1 downto 0);
      OPA_i : in SDWORD_T;
      OPB_i : in SDWORD_T;
 
      RES_o : out SDWORD_T
    );
  end component;
 
  component RV01_BJXLOG is
    generic(
      JRPE : std_logic := '1'
    );
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      BJ_OP_i : in BJ_OP_T;
      SU_i : in std_logic;
      PC_i : in ADR_T;
      OPA_i : in SDWORD_T;
      OPB_i : in SDWORD_T;
      IMM_i : in SDWORD_T;
      IV_i : in std_logic;
      FSTLL_i : in std_logic;
      MPJRX_i : in std_logic;
 
      BJX_o : out std_logic;
      BJTA_o : out ADR_T
    );
  end component;
 
  component RV01_LSU is
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      IV_i : in std_logic;
      LS_OP_i : in LS_OP_T;
      SU_i : in std_logic;
      OPA_i : in SDWORD_T;
      OPB_i : in SDWORD_T;
      IMM_i : in SDWORD_T;
      LDAT_i : in std_logic_vector(SDLEN-1 downto 0);
 
      RE_o : out std_logic;
      WE_o : out std_logic;
      MALGN_o : out std_logic;
      ADR_o : out unsigned(ALEN-1 downto 0);
      SBE_o : out std_logic_vector(4-1 downto 0);
      SDAT_o : out std_logic_vector(SDLEN-1 downto 0);
      LDATV_o : out std_logic;
      LDAT_o : out SDWORD_T
    );
  end component;
 
  component RV01_SBUF_2W is
    generic(
      NW : natural := 2;
      DEPTH : natural := 4;
      SIMULATION_ONLY : std_logic := '0'
    );
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      CLRB_i : in std_logic;
      KTS_i : in std_logic;
      RE_i : in std_logic_vector(NW-1 downto 0);
      WE_i : in std_logic_vector(NW-1 downto 0);
      BE0_i : in std_logic_vector(4-1 downto 0);
      BE1_i : in std_logic_vector(4-1 downto 0);
      D0_i : in std_logic_vector(SDLEN-1 downto 0);
      D1_i : in std_logic_vector(SDLEN-1 downto 0);
      IX1_V_i : std_logic_vector(2-1 downto 0);
      LS_OP0_i : in LS_OP_T;
      LS_OP1_i : in LS_OP_T;
      DADR0_i : in ADR_T;
      DADR1_i : in ADR_T;
      SADR0_i : in ADR_T;
      SADR1_i : in ADR_T;
 
      BF_o : out std_logic;
      NOPR_o : out std_logic;
      S2LAC_o : out std_logic_vector(2-1 downto 0);
      WE_o : out std_logic;
      LS_OP_o : out LS_OP_T;
      BE_o : out std_logic_vector(4-1 downto 0);
      Q_o : out std_logic_vector(SDLEN-1 downto 0);
      SADR_o : out ADR_T
    );
  end component;
 
  component RV01_REGFILE_32X32_2W is
    port(
      CLK_i : in std_logic;
      RA0_i : in RID_T;
      RA1_i : in RID_T;
      RA2_i : in RID_T;
      RA3_i : in RID_T;
      WA0_i : in RID_T;
      WA1_i : in RID_T;
      WE0_i : in std_logic;
      WE1_i : in std_logic;
      D0_i : in std_logic_vector(SDLEN-1 downto 0);
      D1_i : in std_logic_vector(SDLEN-1 downto 0);
 
      Q0_o : out std_logic_vector(SDLEN-1 downto 0);
      Q1_o : out std_logic_vector(SDLEN-1 downto 0);
      Q2_o : out std_logic_vector(SDLEN-1 downto 0);
      Q3_o : out std_logic_vector(SDLEN-1 downto 0)
    );
  end component;
 
  component RV01_DIVLOG is
    port(
      V_i : in std_logic;
      INSTR_i : in DEC_INSTR_T;
      DIV_V_i : in std_logic;
 
      DIV_STRT_o : out std_logic;
      DIV_QS_o : out std_logic;
      DIV_CLRV_o : out std_logic
    );
  end component;
 
  component RV01_DIVIDER_R2 is
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      STRT_i : in std_logic;
      SU_i : in std_logic;
      QS_i : in std_logic;
      DD_i : in SDWORD_T;
      DR_i : in SDWORD_T;
      CLRD_i : in std_logic;
      CLRV_i : in std_logic;
 
      Q_o : out SDWORD_T;
      QV_o : out std_logic;
      BSY_o : out std_logic
    );
  end component;
 
  component RV01_CSRU is
    generic(
      PXE : std_logic := '1';
      FPU_PRESENT : std_logic := '0';
      NW : natural := 2
    );
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      IX1_V0_i : in std_logic;
      CS_OP_i : in CS_OP_T;
      RS1_i : in RID_T;
      ADR_i : in signed(12-1 downto 0);
      WE_i : in std_logic;
      CSRD_i : in SDWORD_T;
      EXCP_i : in std_logic;
      EPC_i : in unsigned(ALEN-1 downto 0);
      ECAUSE_i : in std_logic_vector(5-1 downto 0);
      EBADR_i : in unsigned(ALEN-1 downto 0);
      ERET_i : in std_logic;
      IX3_V_i : in std_logic_vector(NW-1 downto 0);
      NOPR_i : in std_logic;
      HALT_i : in std_logic;
      STOPCYCLE_i : in std_logic;
      STOPTIME_i : in std_logic;
      MFROMHOST_WE_i : in std_logic;
      MFROMHOST_i : in std_logic_vector(SDLEN-1 downto 0);
      DMODE_i : in std_logic;
      DIE_i : in std_logic;
      CPRE_i : in std_logic;
      CPWE_i : in std_logic;
      CPADR_i : in std_logic_vector(17-1 downto 0);
      CPD_i : in std_logic_vector(SDLEN-1 downto 0);
 
      PXE_o : out std_logic;
      MSTATUS_o : out SDWORD_T;
      MEPC_o : out unsigned(ALEN-1 downto 0);
      MBASE_o : out unsigned(ALEN-1 downto 0);
      MBOUND_o : out unsigned(ALEN-1 downto 0);
      MIBASE_o : out unsigned(ALEN-1 downto 0);
      MIBOUND_o : out unsigned(ALEN-1 downto 0);
      MDBASE_o : out unsigned(ALEN-1 downto 0);
      MDBOUND_o : out unsigned(ALEN-1 downto 0);
      ETVA_o : out ADR_T;
      MTOHOST_o : out std_logic_vector(SDLEN-1 downto 0);
      MTOHOST_OE_o : out std_logic;
      ILLG_o : out std_logic;
      SFT_INT_o : out std_logic;
      TMR_INT_o : out std_logic;
      FFLAGS_o : out std_logic_vector(5-1 downto 0);
      FRM_o : out std_logic_vector(3-1 downto 0);
      IE_o : out std_logic;
      CSRQ_o : out SDWORD_T;
      CPQ_o : out std_logic_vector(SDLEN-1 downto 0)
    );
  end component;
 
  component RV01_DBGLOG_IX2 is
    generic(
      NW : natural := 2
    );
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      V_i : in std_logic_vector(NW-1 downto 0);
      IMNMC0_i : in INST_MNEMONIC_T;
      RFTCH0_i : in std_logic;
      STEP_i : in std_logic;
      HOBRK_i : in std_logic;
      HRQ_i : in std_logic;
 
      STEP_o : out std_logic;
      HALT_o : out std_logic_vector(NW-1 downto 0);
      HIS_o : out std_logic
    );
  end component;
 
  component RV01_HLTLOG_IX2 is
    generic(
      NW : natural := 2
    );
    port(
      IMNMC0_i : in INST_MNEMONIC_T;
      V_i : in std_logic_vector(NW-1 downto 0);
      PC0_i : in unsigned(ALEN-1 downto 0);
      PC1_i : in unsigned(ALEN-1 downto 0);
      HOBRK_i : in std_logic;
      HOADR_i : in std_logic_vector(NW-1 downto 0);
      HADR_i : in unsigned(ALEN-1 downto 0);
      HRQ_i : in std_logic;
 
      HALT_o : out std_logic_vector(NW-1 downto 0);
      HIS_o : out std_logic
    );
  end component;
 
  component RV01_EXCPLOG_IX1 is
    generic(
      NW : natural := 2
    );
    port(
      INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
      MALGN_i : in std_logic_vector(NW-1 downto 0);
      S2LAC_i : in std_logic_vector(NW-1 downto 0);
      B2BAC_i : in std_logic;
      DIV_V_i : in std_logic;
      IDADR_CFLT_i : in std_logic;
 
      PSLP_o : out std_logic;
      INSTR_o : out DEC_INSTR_VEC_T(NW-1 downto 0)
    );
  end component;
 
  component RV01_EXCPLOG_IX2 is
    generic(
      NW : natural := 2
    );
    port(
      V_i : in std_logic_vector(2-1 downto 0); -- slot #0,1 valid flag
      INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0); -- slot #0/1 inst.
      PC0_i : in ADR_T; -- slot #0 pc
      PC1_i : in ADR_T; -- slot #1 pc
      DADR0_i : in ADR_T; -- slot #0 L/S addr.
      DADR1_i : in ADR_T; -- slot #1 L/S addr.
      HALT_i : in std_logic_vector(2-1 downto 0); -- halt request flag
      RSM_i : in std_logic; -- resume flag
      DRSM_i : in std_logic; -- debug resume flag
      EXT_INT_i : in std_logic; -- external int. flag
      SFT_INT_i : in std_logic; -- soft int. flag
      TMR_INT_i : in std_logic; -- timer int. flag 
      ETVA_i : in ADR_T; -- exc. target vector addr.
      MEPC_i : in ADR_T; -- mepc CSR
      DADR0_ERR_i : in std_logic; -- slot #0 L/S addr. err.
      DADR1_ERR_i : in std_logic; -- slot #1 L/S addr. err.
      CSR_ILLG_i : in std_logic;
      IE_i : in std_logic;
      STEP_i : in std_logic;
 
      V_o : out std_logic_vector(2-1 downto 0); -- slot #0,1 valid flag
      EV_o : out std_logic_vector(2-1 downto 0); -- slot #0,1 excp. valid flag
      INSTR_o : out DEC_INSTR_VEC_T(NW-1 downto 0); -- slot #0/1 inst.
      EERTA_o : out ADR_T -- exception, eret and re-fetch target addr.
    );
  end component;
 
  component RV01_EXCPLOG_IX3 is
    generic(
      NW : natural := 2
    );
    port(
      V_i : in std_logic_vector(2-1 downto 0); -- slot #0,1 valid flag
      EV_i : in std_logic_vector(2-1 downto 0); -- slot #0,1 valid flag
      INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0); -- slot #0/1 inst.
      PC0_i : in ADR_T; -- slot #0 pc
      PC1_i : in ADR_T; -- slot #1 pc
      DADR0_i : in ADR_T; -- slot #0 L/S addr.
      DADR1_i : in ADR_T; -- slot #1 L/S addr.
      HALT_i : in std_logic; -- halt flag
      HIS_i : in std_logic; -- halt instruction selector
 
      EXCP_o : out std_logic; -- exc. flag
      ERET_o : out std_logic; -- return from exc. flag
      RFTCH_o : out std_logic; -- re-fetch flag
      KPRD_o : out std_logic_vector(2-1 downto 0); -- slot #0/1 keep pipe reg. data flag
      CLRP_o : out std_logic; -- clear pipe flag
      CLRB_o : out std_logic; -- clear store buffer flag
      CLRD_o : out std_logic; -- clear divider flag
      EPC_o : out ADR_T; -- exc. pc
      ECAUSE_o : out std_logic_vector(5-1 downto 0); -- exc. cause
      EDADR_o : out ADR_T -- exc. L/S addr.
    );
  end component;
 
  component RV01_BPU is
    generic(
      BHT_SIZE : natural := 64;
      PXE : std_logic := '1';
      NW : natural := 2
    );
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      INIT_STRT_i : in std_logic;
      IF_V_i : in std_logic_vector(NW-1 downto 0);
      IF_PC_i : in ADR_VEC_T(NW-1 downto 0);
      IF2_V_i : in std_logic_vector(NW-1 downto 0);
      IF2_PC_i : in ADR_VEC_T(NW-1 downto 0);
      BHT_BTA_i : in ADR_VEC_T(NW-1 downto 0);
      BHT_PC_i : in ADR_VEC_T(NW-1 downto 0);
      BHT_CNT0_i : in std_logic_vector(2-1 downto 0);
      BHT_CNT1_i : in std_logic_vector(2-1 downto 0);
      BHT_WE_i : in std_logic_vector(NW-1 downto 0);
 
      INIT_END_o : out std_logic;
      PBX_o : out std_logic;
      KLL1_o : out std_logic;
      PBTA_o : out unsigned(ALEN-1 downto 0);
      BPVD0_o : out std_logic_vector(3-1 downto 0);
      BPVD1_o : out std_logic_vector(3-1 downto 0)
    );
  end component;
 
  component RV01_BJXLOG_BV is
    generic(
      JRPE : std_logic := '1'
    );
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      BJ_OP_i : in BJ_OP_T;
      SU_i : in std_logic;
      PC_i : in ADR_T;
      OPA_i : in SDWORD_T;
      OPB_i : in SDWORD_T;
      IMM_i : in SDWORD_T;
      IV_i : in std_logic;
      FSTLL_i : in std_logic;
      BPVD_i : std_logic_vector(3-1 downto 0);
      MPJRX_i : in std_logic;
 
      BJX_o : out std_logic;
      BJTA_o : out unsigned(ALEN-1 downto 0);
      BHT_WE_o : out std_logic;
      BHT_TA_o : out ADR_T;
      BHT_PC_o : out ADR_T;
      BHT_CNT_o : out std_logic_vector(2-1 downto 0)
    );
  end component;
 
  component RV01_JRPU is
    generic(
      RAS_DEPTH : natural := 4;
      JRVQ_DEPTH : natural := 2;
      PXE : std_logic := '1';
      NW : natural := 2
    );
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      CLR_i : in std_logic;
      KLL1_i : in std_logic;
      FSTLL_i : in std_logic;
      BJX_i : in std_logic;
      -- prediction inputs
      INSTR_i : in std_logic_vector(ILEN*2-1 downto 0);
      IF2_V_i : in std_logic_vector(NW-1 downto 0);
      IF2_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
      IF2_PC_i : in ADR_VEC_T(NW-1 downto 0);
      -- verification inputs
      IX1_V_i : in std_logic_vector(NW-1 downto 0);
      IX1_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
      IX1_OPA0_i : SDWORD_T;
      IX1_OPA1_i : SDWORD_T;
      IX1_PCP4_i : ADR_VEC_T(NW-1 downto 0);
      -- RAS management
      IX3_V_i : in std_logic_vector(NW-1 downto 0);
      IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
      IX3_PCP4_i : ADR_VEC_T(NW-1 downto 0);
 
      KLL1_o : out std_logic;
      PJRX_o : out std_logic;
      PJRTA_o : out ADR_T;
      MPJRX_o : out std_logic_vector(NW-1 downto 0)
    );
  end component;
 
  component RV01_PIPE_A_ALU is
    port(
      SEL_i :  in std_logic_vector(4-1 downto 0);
      SU_i : in std_logic;
      OP_i : in ALU_OP_T;
      OPA_i : in SDWORD_T;
      OPB_i : in SDWORD_T;
 
      RES_o : out SDWORD_T --  result
    );
  end component;
 
  component RV01_PSTLLOG_2W_P6 is
    generic(
      DXE : std_logic := '1';
      SIMULATION_ONLY : std_logic := '0'
    );
    port(
      CLK_i : in std_logic;
      ID_INSTR_i : in DEC_INSTR_T;
      ID_V_i : in std_logic;
      IX1_INSTR0_i : in DEC_INSTR_T;
      IX1_INSTR1_i : in DEC_INSTR_T;
      IX1_V_i : in std_logic_vector(2-1 downto 0);
      IX1_FWDE_i : in std_logic_vector(2-1 downto 0);
      IX2_INSTR0_i : in DEC_INSTR_T;
      IX2_INSTR1_i : in DEC_INSTR_T;
      IX2_V_i : in std_logic_vector(2-1 downto 0);
      IX2_FWDE_i : in std_logic_vector(2-1 downto 0);
      IX3_INSTR0_i : in DEC_INSTR_T;
      IX3_INSTR1_i : in DEC_INSTR_T;
      IX3_V_i : in std_logic_vector(2-1 downto 0);
      IX3_FWDE_i : in std_logic_vector(2-1 downto 0);
 
      OPA_V_o :  out std_logic;
      OPB_V_o :  out std_logic;
      DSA_o :  out std_logic;
      DSB_o :  out std_logic;
      PSTALL_o : out std_logic
    );
  end component;
 
  component RV01_SHFTU is
    port(
      CTRL_i : in SHF_CTRL;
      SI_i : in SDWORD_T;
      SHFT_i : in unsigned(5-1 downto 0);
      SU_i : in std_logic;
 
      SO_o : out SDWORD_T
    );
  end component;
 
  component RV01_CPU_INIT is
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      STRT_i : in std_logic;
      RSM_i : in std_logic;
      BHT_INIT_END_i : in std_logic;
 
      INIT_STRT_o : out std_logic;
      STRT_o : out std_logic
   );
  end component;
 
  component RV01_DIMSLOG is
    generic(
      IMEM_LOWM : std_logic := '1';
      IMEM_SIZE : natural := 1024*32;
      DMEM_SIZE : natural := 1024*16
    );
    port(
      IX1_OPA0_i : in SDWORD_T;
      IX1_OPA1_i : in SDWORD_T;
      IX1_IMM0_i : in SDWORD_T;
      IX1_IMM1_i : in SDWORD_T;
      IX1_DADR0_i : in ADR_T;
      IX1_DADR1_i : in ADR_T;
      IX3_DADR0_i : in ADR_T;
 
      IX1_DIMS_o : out std_logic_vector(NW-1 downto 0);
      IX3_DIMS_o : out std_logic
  );
  end component;
 
  component RV01_DBGU is
    generic(
      NW : natural := 2
    );
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      HPC_i : in ADR_T;
      MMODE_i : in std_logic;
      NOPR_i : in std_logic;
      -- Debug interface
      HALT_i : in std_logic;
      -- Control port
      CPRE_i : in std_logic;
      CPWE_i : in std_logic;
      CPADR_i : in std_logic_vector(17-1 downto 0);
      CPD_i : in std_logic_vector(SDLEN-1 downto 0);
 
      RST_o : out std_logic;
      HLTRQ_o : out std_logic;
      RSM_o : out std_logic;
      DPC_o : out ADR_T;
      DMODE_o : out std_logic;
      DIE_o : out std_logic;
      HALTD_o : out std_logic;
      STOPTIME_o : out std_logic;
      STOPCYCLE_o : out std_logic;
      SI_o : out std_logic_vector(SDLEN-1 downto 0);
      HOBRK_o : out std_logic;
      STEP_o : out std_logic;
      FRCSI_o : out std_logic;
      -- Control port
      CPQ_o : out std_logic_vector(SDLEN-1 downto 0)
    );
  end component;
 
  component RV01_HLTU is
    generic(
      PXE : std_logic := '1';
      NW : natural := 2
    );
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      IX1_V_i : in std_logic_vector(NW-1 downto 0);
      IX2_V_i : in std_logic_vector(NW-1 downto 0);
      NOPR_i : in std_logic; -- no pending read (in sbuf) flag
      MMODE_i : in std_logic; -- machine mode flag
      HALT_i : in std_logic; -- halt flag
      HPC_i : in ADR_T; -- halt PC
      -- CSR interface
      CS_OP_i : in CS_OP_T;
      RS1_i : in RID_T;
      ADR_i : in signed(12-1 downto 0);
      WE_i : in std_logic;
      CSRD_i : in SDWORD_T;
      -- Control port
      CPRE_i : in std_logic;
      CPWE_i : in std_logic;
      CPADR_i : in std_logic_vector(17-1 downto 0);
      CPD_i : in std_logic_vector(SDLEN-1 downto 0);
 
      HMODE_o : out std_logic; -- halt mode flag
      STRT_o : out std_logic; -- start flag
      STRTPC_o : out ADR_T; -- start PC
      RSM_o : out std_logic; -- resume flag
      HLTURQ_o : out std_logic; -- halt request flag
      HLTOBRK_o : out std_logic; -- halt-on-break enable
      HLTOADR_o : out std_logic_vector(NW-1 downto 0); -- halt-on-address enable
      HLTADR_o : out ADR_T; -- halt address
      -- CSR interface
      CSRQ_o : out SDWORD_T;
      HCSR_o : out std_logic;
      ILLG_o : out std_logic;
      -- Control port
      HCP_o : out std_logic;
      CPQ_o : out std_logic_vector(SDLEN-1 downto 0)
    );
  end component;
 
  component RV01_RESMUX_IX1 is
    generic(
      PXE : std_logic := '1';
      DXE : std_logic := '1';
      NW : natural := 2
    );
    port(
      OPA0_V_i : in std_logic;
      OPA1_V_i : in std_logic;
      OPA0_i : in SDWORD_T;
      OPA1_i : in SDWORD_T;
      OPB0_V_i : in std_logic;
      OPB1_V_i : in std_logic;
      OPB0_i : in SDWORD_T;
      OPB1_i : in SDWORD_T;
      SHF_RES0_i : in SDWORD_T;
      SHF_RES1_i : in SDWORD_T;
      PA0_ALU_RES_i : in SDWORD_T;
      PA1_ALU_RES_i : in SDWORD_T;
      DIV_V_i : in std_logic;
      DIV_RES_i : in SDWORD_T;
      PASEL0_i : in std_logic_vector(4-1 downto 0);
      PASEL1_i : in std_logic_vector(4-1 downto 0);
      FWDE_i : in std_logic_vector(NW-1 downto 0);
      DSA0_i : in std_logic;
      DSB0_i : in std_logic;
      DSA1_i : in std_logic;
      DSB1_i : in std_logic;
      INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
      IX3_DRD0_i : in SDWORD_T;
      IX3_DRD1_i : in SDWORD_T;
      IX3_V_i : in std_logic_vector(NW-1 downto 0);
      IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
 
      FWDX_o : out std_logic_vector(NW-1 downto 0);
      PA0_RES_o : out SDWORD_T;
      PA1_RES_o : out SDWORD_T;
      OPA0_V_o : out std_logic;
      OPA1_V_o : out std_logic;
      OPA0_o : out SDWORD_T;
      OPA1_o : out SDWORD_T;
      OPB0_V_o : out std_logic;
      OPB1_V_o : out std_logic;
      OPB0_o : out SDWORD_T;
      OPB1_o : out SDWORD_T;
      DRD0_V_o : out std_logic;
      DRD1_V_o : out std_logic;
      DRD0_o : out SDWORD_T;
      DRD1_o : out SDWORD_T
    );
  end component;
 
  component RV01_RESMUX_IX2 is
    generic(
      PXE : std_logic := '1';
      DXE : std_logic := '1';
      NW : natural := 2
    );
    port(
      OPA0_V_i : in std_logic;
      OPA1_V_i : in std_logic;
      OPA0_i : in SDWORD_T;
      OPA1_i : in SDWORD_T;
      OPB0_V_i : in std_logic;
      OPB1_V_i : in std_logic;
      OPB0_i : in SDWORD_T;
      OPB1_i : in SDWORD_T;
      DRD0_V_i : in std_logic;
      DRD1_V_i : in std_logic;
      DRD0_i : in SDWORD_T;
      DRD1_i : in SDWORD_T;
      DDAT0_i : in std_logic_vector(SDLEN-1 downto 0);
      DDAT1_i : in std_logic_vector(SDLEN-1 downto 0);
      PA0_ALU_RES_i : in SDWORD_T;
      PA1_ALU_RES_i : in SDWORD_T;
      PB0_RES_i : in SDWORD_T;
      PC1P4_i : in unsigned(SDLEN-1 downto 0);
      PASEL0_i : in std_logic_vector(4-1 downto 0);
      PASEL1_i : in std_logic_vector(4-1 downto 0);
      FWDE_i : in std_logic_vector(NW-1 downto 0);
      INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
      IX3_DRD0_i : in SDWORD_T;
      IX3_DRD1_i : in SDWORD_T;
      IX3_V_i : in std_logic_vector(NW-1 downto 0);
      IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
 
      FWDX_o : out std_logic_vector(NW-1 downto 0);
      PA0_RES_o : out SDWORD_T;
      PA1_RES_o : out SDWORD_T;
      OPA0_V_o : out std_logic;
      OPA1_V_o : out std_logic;
      OPA0_o : out SDWORD_T;
      OPA1_o : out SDWORD_T;
      OPB0_V_o : out std_logic;
      OPB1_V_o : out std_logic;
      OPB0_o : out SDWORD_T;
      OPB1_o : out SDWORD_T;
      DRD0_o : out SDWORD_T;
      DRD1_o : out SDWORD_T
    );
  end component;
 
  component RV01_RESMUX_IX3 is
    generic(
      PXE : std_logic := '1';
      DXE : std_logic := '1';
      NW : natural := 2
    );
    port(
      DRD0_i : in SDWORD_T;
      DRD1_i : in SDWORD_T;
      PA0_ALU_RES_i : in SDWORD_T;
      PA1_ALU_RES_i : in SDWORD_T;
      LDAT0_i : in SDWORD_T;
      LDAT1_i : in SDWORD_T;
      LDAT_V_i : in std_logic_vector(NW-1 downto 0);
      PASEL0_i : in std_logic_vector(4-1 downto 0);
      PASEL1_i : in std_logic_vector(4-1 downto 0);
      FWDE_i : in std_logic_vector(NW-1 downto 0);
      RES_SRC0_i : in RES_SRC_T;
      CSRU_RES_i : in SDWORD_T;
 
      DRD0_o : out SDWORD_T;
      DRD1_o : out SDWORD_T
    );
  end component;
 
  component RV01_CDCOMUX is
    generic(
      DMP : std_logic := '0'
    );
    port(
      CLK_i : in std_logic;
      HCSR_i : in std_logic;
      HCSRQ_i : in SDWORD_T;
      CSRQ_i : in SDWORD_T;
      HILLG_i : in std_logic;
      ILLG_i : in std_logic;
      CP_ADR_MSB_i : in std_logic;
      HCP_i : in std_logic;
      HCPQ_i : in std_logic_vector(SDLEN-1 downto 0);
      CPQ_i : in std_logic_vector(SDLEN-1 downto 0);
      DCPQ_i : in std_logic_vector(SDLEN-1 downto 0);
      STRT_i : in std_logic;
      DRSM_i : in std_logic;
      DPC_i : in ADR_T;
      STRTPC_i : in ADR_T;
 
      ILLG_o : out std_logic;
      CSRU_RES_o : out SDWORD_T;
      CP_Q_o : out std_logic_vector(SDLEN-1 downto 0);
      STRT_o : out std_logic;
      STRTPC_o : out ADR_T
    );
  end component;
 
  component RV01_MISCLOG_IX3 is
    generic(
      PXE : std_logic := '0';
      NW : natural := 2
    );
    port(
      IX1_V0_i : in std_logic;
      IX1_WCSR0_i : in std_logic;
      V_i : in std_logic_vector(NW-1 downto 0);
      DWE_i : in std_logic_vector(NW-1 downto 0);
      KPRD_i : in std_logic_vector(NW-1 downto 0);
      WRD0_i : in std_logic;
      WRD1_i : in std_logic;
      HALT_i : in std_logic_vector(NW-1 downto 0);
      CLRP_i : in std_logic;
      CLRD_i : in std_logic;
      HIS_i : in std_logic;
      PC0_i : in ADR_T;
      PC1_i : in ADR_T;
 
      CP_WE_o : out std_logic;
      SBRE_o : out std_logic_vector(NW-1 downto 0);
      STL_o : out std_logic_vector(NW-1 downto 0);
      WE_o : out std_logic_vector(NW-1 downto 0);
      HALT_o : out std_logic;
      CLRP_o : out std_logic;
      CLRD_o : out std_logic;
      HPC_o : out ADR_T
    );
  end component;
 
  signal ZERO : std_logic := '0';
  signal ONE : std_logic := '1';
 
  signal INIT_STRT : std_logic;
  signal BHT_INIT_END : std_logic;
  signal STRT : std_logic;
  signal IRST : std_logic;
 
  signal IF1_V,IF1_V_q : std_logic_vector(NW-1 downto 0);
  signal IF2_V_q : std_logic_vector(NW-1 downto 0);
  signal IF1_PC : ADR_VEC_T(NW-1 downto 0);
  signal IF1_PC_q : ADR_VEC_T(NW-1 downto 0);
  signal IF1_IADR_MIS : std_logic;
  signal IF1_IADR_MIS_q : std_logic_vector(NW-1 downto 0);
 
  signal IF2_DEC_INSTR : DEC_INSTR_VEC_T(NW-1 downto 0);
  signal IF2_DEC_INSTR_q : DEC_INSTR_VEC_T(NW-1 downto 0);
  signal IF2_OPA_PC : std_logic_vector(NW-1 downto 0);
  signal IF2_OPA_PC_q : std_logic_vector(NW-1 downto 0);
  signal IF2_OPB_IMM : std_logic_vector(NW-1 downto 0);
  signal IF2_OPB_IMM_q : std_logic_vector(NW-1 downto 0);
  signal IF2_PC_q : ADR_VEC_T(NW-1 downto 0);
  signal IF2_INSTR0,IF2_INSTR1 : std_logic_vector(ILEN-1 downto 0);
  signal IF2_V : std_logic_vector(NW-1 downto 0);
  signal IF2_KLL1 : std_logic;
  signal IF2_V_KILL : std_logic;
  signal IF2_PBX : std_logic;
  signal IF2_PBTA : ADR_T;
  signal IF2_BPVD0 : std_logic_vector(3-1 downto 0);
  signal IF2_BPVD1 : std_logic_vector(3-1 downto 0);
  signal IF2_BPVD0_q : std_logic_vector(3-1 downto 0);
  signal IF2_BPVD1_q : std_logic_vector(3-1 downto 0);
  signal IF2_JRKLL1 : std_logic;
  signal IF2_PJRX : std_logic;
  signal IF2_PJRTA : ADR_T;
 
  signal ID_INSTR0,ID_INSTR1 : DEC_INSTR_T;
  signal ID_INSTR_q : DEC_INSTR_VEC_T(NW-1 downto 0);
  signal ID_V,ID_V_q : std_logic_vector(NW-1 downto 0);
  signal ID_ISSUE : std_logic_vector(NW-1 downto 0);
  signal ID_PC_q : ADR_VEC_T(NW-1 downto 0);
  signal ID_OPA0,ID_OPA0_q : SDWORD_T;
  signal ID_OPB0,ID_OPB0_q : SDWORD_T;
  signal ID_OPA1,ID_OPA1_q : SDWORD_T;
  signal ID_OPB1,ID_OPB1_q : SDWORD_T;
  signal ID_PSTALL : std_logic;
  signal ID_PS : std_logic_vector(NW-1 downto 0);
  signal ID_PXE1 : std_logic;
  signal ID_JLRA : ADR_VEC_T(NW-1 downto 0);
  signal ID_FWDE : std_logic_vector(NW-1 downto 0);
  signal ID_FWDE_q : std_logic_vector(NW-1 downto 0);
  signal ID_FWDX_q : std_logic_vector(NW-1 downto 0);
  signal ID_PASEL0,ID_PASEL1 :  std_logic_vector(4-1 downto 0);
  signal ID_PASEL0_q,ID_PASEL1_q :  std_logic_vector(4-1 downto 0);
  signal ID_OPA_PC_q : std_logic_vector(NW-1 downto 0);
  signal ID_DIV_BSY : std_logic;
  signal ID_BPVD0_q : std_logic_vector(3-1 downto 0);
  signal ID_BPVD1_q : std_logic_vector(3-1 downto 0);
  signal ID_OPA0_V : std_logic;
  signal ID_OPB0_V : std_logic;
  signal ID_OPA1_V : std_logic;
  signal ID_OPB1_V : std_logic;
  signal ID_OPA0_V_q : std_logic;
  signal ID_OPB0_V_q : std_logic;
  signal ID_OPA1_V_q : std_logic;
  signal ID_OPB1_V_q : std_logic;
  signal ID_DSA0,ID_DSA0_q : std_logic;
  signal ID_DSB0,ID_DSB0_q : std_logic;
  signal ID_DSA1,ID_DSA1_q : std_logic;
  signal ID_DSB1,ID_DSB1_q : std_logic;
 
  signal IX1_INSTR : DEC_INSTR_VEC_T(NW-1 downto 0);
  signal IX1_INSTR_q : DEC_INSTR_VEC_T(NW-1 downto 0);
  signal IX1_SRST : std_logic;
  signal IX1_BJX : std_logic;
  signal IX1_BJTA : ADR_T;
  signal IX1_BJX0 : std_logic;
  signal IX1_BJTA0 : ADR_T;
  signal IX1_BJX1 : std_logic;
  signal IX1_BJTA1 : ADR_T;
  signal IX1_BJX0_q : std_logic;
  signal IX1_BJTA0_q : ADR_T;
  signal IX1_BJX1_q : std_logic;
  signal IX1_BJTA1_q : ADR_T;
  signal IX1_DWE : std_logic_vector(NW-1 downto 0);
  signal IX1_PDWE : std_logic_vector(NW-1 downto 0);
  signal IX1_DDATO0,IX1_DDATO1 : std_logic_vector(SDLEN-1 downto 0);
  signal IX1_DADR0,IX1_DADR1 : ADR_T;
  signal IX1_DADR0_q,IX1_DADR1_q : ADR_T;
  signal IX1_V,IX1_V_q : std_logic_vector(NW-1 downto 0);
  signal IX1_FWDE_q : std_logic_vector(NW-1 downto 0);
  signal IX1_FWDX_q : std_logic_vector(NW-1 downto 0);
  signal IX1_PA0_RES : SDWORD_T;
  signal IX1_PA1_RES : SDWORD_T;
  signal IX1_DBE0,IX1_DBE1 : std_logic_vector(4-1 downto 0);
  signal IX1_PC0_q,IX1_PC1_q : ADR_T;
  signal IX1_S2LAC : std_logic_vector(2-1 downto 0);
  signal IX1_DIV_STRT,IX1_DIV_QS : std_logic;
  signal IX1_PC0P4,IX1_PC0P4_q : ADR_T;
  signal IX1_PC1P4,IX1_PC1P4_q : ADR_T;
  signal IX1_MALGN : std_logic_vector(NW-1 downto 0);
  signal IX1_SBF : std_logic;
  signal IX1_DWE_q : std_logic_vector(2-1 downto 0);
  signal IX1_DIV_RES : SDWORD_T;
  signal IX1_DIV_V : std_logic;
  signal IX1_DIV_CLRV : std_logic;
  signal IX1_DRD0,IX1_DRD1 : SDWORD_T;
  signal IX1_DRD0_q,IX1_DRD1_q : SDWORD_T;
  signal IX1_DRD0_V,IX1_DRD1_V : std_logic;
  signal IX1_DRD0_V_q,IX1_DRD1_V_q : std_logic;
  signal IX1_NOPR : std_logic;
  signal IX1_CP_WE : std_logic;
  signal IX1_BHT_TA : ADR_VEC_T(NW-1 downto 0);
  signal IX1_BHT_CNT0 : std_logic_vector(2-1 downto 0);
  signal IX1_BHT_CNT1 : std_logic_vector(2-1 downto 0);
  signal IX1_BHT_PWE : std_logic;
  signal IX1_BHT_WE : std_logic_vector(2-1 downto 0);
  signal IX1_PDADR0,IX1_PDADR1 : ADR_T;
  signal IX1_PDIADR0,IX1_PDIADR1 : ADR_T;
  signal IX1_DIMS : std_logic_vector(NW-1 downto 0);
  signal IX1_MPJRX : std_logic_vector(NW-1 downto 0);
  signal IX1_OPA0_V : std_logic;
  signal IX1_OPB0_V : std_logic;
  signal IX1_OPA1_V : std_logic;
  signal IX1_OPB1_V : std_logic;
  signal IX1_OPA0_V_q : std_logic;
  signal IX1_OPB0_V_q : std_logic;
  signal IX1_OPA1_V_q : std_logic;
  signal IX1_OPB1_V_q : std_logic;
  signal IX1_OPA0 : SDWORD_T;
  signal IX1_OPB0 : SDWORD_T;
  signal IX1_OPA1 : SDWORD_T;
  signal IX1_OPB1 : SDWORD_T;
  signal IX1_OPA0_q : SDWORD_T;
  signal IX1_OPB0_q : SDWORD_T;
  signal IX1_OPA1_q : SDWORD_T;
  signal IX1_OPB1_q : SDWORD_T;
  signal IX1_PASEL0_q : std_logic_vector(4-1 downto 0);
  signal IX1_PASEL1_q : std_logic_vector(4-1 downto 0);
  signal IX1_FWDX : std_logic_vector(NW-1 downto 0);
  signal IX1_SHFT0,IX1_SHFT1 :  unsigned(5-1 downto 0);
  signal IX1_SHF_CTRL0,IX1_SHF_CTRL1 : SHF_CTRL;
  signal IX1_SHF_RES0,IX1_SHF_RES1 : SDWORD_T;
  signal IX1_PA0_ALU_RES : SDWORD_T;
  signal IX1_PA1_ALU_RES : SDWORD_T;
  signal IX1_B2BAC : std_logic;
  signal IX1_SHF0_V : std_logic;
  signal IX1_SHF1_V : std_logic;
  signal IX1_KTS : std_logic;
  signal IX1_KTS_q : std_logic;
  signal IX1_PSLP : std_logic;
 
  signal IX2_DRD0,IX2_DRD1 : SDWORD_T;
  signal IX2_PA0_RES : SDWORD_T;
  signal IX2_PA1_RES : SDWORD_T;
  signal IX2_PB0_RES : SDWORD_T;
  signal IX2_PB1_RES : SDWORD_T;
  signal IX2_INSTR : DEC_INSTR_VEC_T(NW-1 downto 0);
  signal IX2_INSTR_q : DEC_INSTR_VEC_T(NW-1 downto 0);
  signal IX2_DRD0_q,IX2_DRD1_q : SDWORD_T;
  signal IX2_DADR0_q,IX2_DADR1_q : ADR_T;
  signal IX2_V,IX2_V_q : std_logic_vector(NW-1 downto 0);
  signal IX2_V_BJX : std_logic_vector(NW-1 downto 0);
  signal IX2_EV,IX2_EV_q : std_logic_vector(NW-1 downto 0);
  signal IX2_FWDE_q : std_logic_vector(NW-1 downto 0);
  signal IX2_FWDX : std_logic_vector(NW-1 downto 0);
  signal IX2_FWDX_q : std_logic_vector(NW-1 downto 0);
  signal IX2_CSRU_RES,IX2_CSRU_RES_q : SDWORD_T;
  signal IX2_PC0_q,IX2_PC1_q : ADR_T;
  signal IX2_ILLG : std_logic;
  signal IX2_LSADR0_q,IX2_LSADR1_q : ADR_T;
  signal IX2_DWE_q : std_logic_vector(NW-1 downto 0);
  signal IX2_MALGN_q : std_logic_vector(NW-1 downto 0);
  signal IX2_EERTA,IX2_EERTA_q : ADR_T;
  signal IX2_OPA0_V : std_logic;
  signal IX2_OPB0_V : std_logic;
  signal IX2_OPA1_V : std_logic;
  signal IX2_OPB1_V : std_logic;
  signal IX2_OPA0 : SDWORD_T;
  signal IX2_OPB0 : SDWORD_T;
  signal IX2_OPA1 : SDWORD_T;
  signal IX2_OPB1 : SDWORD_T;
  signal IX2_OPA0_q : SDWORD_T;
  signal IX2_OPB0_q : SDWORD_T;
  signal IX2_OPA1_q : SDWORD_T;
  signal IX2_OPB1_q : SDWORD_T;
  signal IX2_PASEL0_q : std_logic_vector(4-1 downto 0);
  signal IX2_PASEL1_q : std_logic_vector(4-1 downto 0);
  signal IX2_PA0_RES_X : SDWORD_T;
  signal IX2_PA1_RES_X : SDWORD_T;
  signal IX2_ERR0_q : std_logic;
  signal IX2_ERR1_q : std_logic;
  signal IX2_PA0_ALU_RES : SDWORD_T;
  signal IX2_PA1_ALU_RES : SDWORD_T;
  signal IX2_NOLD0_RES : SDWORD_T;
  signal IX2_NOLD1_RES : SDWORD_T;
  signal IX2_PC0P4_q,IX2_PC1P4_q : ADR_T;
  signal IX2_SBRK0,IX2_HOBRK0 : std_logic;
  signal IX2_HOADR,IX2_HALT,IX2_HALT_q : std_logic_vector(NW-1 downto 0);
  signal IX2_DRSM : std_logic_vector(NW-1 downto 0);
  signal IX2_HIS,IX2_HIS_q : std_logic;
  signal IX2_DHIS,IX2_DHIS_q : std_logic;
  signal IX2_STEP : std_logic;
  signal IX2_BJX : std_logic;
  signal IX2_BJTA : ADR_T;
 
  signal IX3_DRD0,IX3_DRD1 : SDWORD_T;
  signal IX3_DRD0_X,IX3_DRD1_X : SDWORD_T;
  signal IX3_LDAT0_V : std_logic;
  signal IX3_LDAT0 : SDWORD_T;
  signal IX3_LDAT1_V : std_logic;
  signal IX3_LDAT1 : SDWORD_T;
  signal IX3_EXCP : std_logic;
  signal IX3_EPC : ADR_T;
  signal IX3_ECAUSE : std_logic_vector(5-1 downto 0);
  signal IX3_EDADR : ADR_T;
  signal IX3_ERET : std_logic;
  signal IX3_HALT : std_logic;
  signal IX3_STL : std_logic_vector(NW-1 downto 0);
  signal IX3_SBRE : std_logic_vector(NW-1 downto 0);
  signal IX3_DWE : std_logic;
  signal IX3_SDATO : std_logic_vector(SDLEN-1 downto 0);
  signal IX3_DBE : std_logic_vector(4-1 downto 0);
  signal IX3_DADR0 : ADR_T;
  signal IX3_LS_OP : LS_OP_T;
  signal IX3_RFTCH : std_logic;
  signal IX3_EERX : std_logic;
  signal IX3_CLRP : std_logic;
  signal IX3_CLRB : std_logic;
  signal IX3_CLRD : std_logic;
  signal IX3_KPRD : std_logic_vector(NW-1 downto 0);
  signal IX3_WE : std_logic_vector(NW-1 downto 0);
  signal IX3_PA0_ALU_RES : SDWORD_T;
  signal IX3_PA1_ALU_RES : SDWORD_T;
  signal IX3_PDADR0 : ADR_T;
  signal IX3_PDIADR0 : ADR_T;
  signal IX3_DIMS : std_logic;
  signal IX3_HPC : ADR_T;
  signal IX3_CLRP_NOHLT : std_logic;
  signal IX3_CLRD_NOHLT : std_logic;
 
  signal WB_SFT_INT : std_logic;
  signal WB_TMR_INT : std_logic;
  signal WB_RDA0,WB_RDB0 : std_logic_vector(SDLEN-1 downto 0);
  signal WB_RDA1,WB_RDB1 : std_logic_vector(SDLEN-1 downto 0);
  signal WB_PXE : std_logic;
  signal WB_EXCP,WB_EIS : std_logic;
  signal WB_ETVA : ADR_T;
  signal WB_MSTATUS : SDWORD_T;
  signal WB_MEPC : ADR_T;
  signal WB_MBASE : ADR_T;
  signal WB_MBOUND : ADR_T;
  signal WB_MIBASE : ADR_T;
  signal WB_MIBOUND : ADR_T;
  signal WB_MDBASE : ADR_T;
  signal WB_MDBOUND : ADR_T;
  signal WB_FFLAGS : std_logic_vector(5-1 downto 0);
  signal WB_FRM : std_logic_vector(3-1 downto 0);
  signal WB_DHLTRQ : std_logic;
  signal WB_DRSM : std_logic;
  signal WB_DPC : ADR_T;
  signal WB_DMODE : std_logic;
  signal WB_DIE : std_logic;
  signal WB_CHK_ENB : std_logic;
  signal WB_STRT : std_logic;
  signal WB_STRTPC : ADR_T;
  signal WB_RSM : std_logic;
  signal WB_HLTRQ : std_logic;
  signal WB_HLTURQ : std_logic;
  signal WB_HLTOBRK : std_logic;
  signal WB_HLTOADR : std_logic_vector(NW-1 downto 0);
  signal WB_HLTADR : ADR_T;
  signal WB_IE : std_logic;
  signal WB_DRST : std_logic;
  signal WB_HALTD : std_logic;
  signal WB_STOPTIME : std_logic;
  signal WB_STOPCYCLE : std_logic;
  signal WB_DHOBRK : std_logic;
  signal WB_DHOADR : std_logic;
  signal WB_DHADR : ADR_T;
  signal WB_CPQ,WB_DCPQ : std_logic_vector(SDLEN-1 downto 0);
  signal WB_MMODE : std_logic;
  signal WB_DSI : std_logic_vector(SDLEN-1 downto 0);
  signal WB_XSTRT : std_logic;
  signal WB_XSTRTPC : ADR_T;
  signal WB_DSTEP : std_logic;
  signal WB_DFRCSI,IF1_DFRCSI_q : std_logic;
  signal WB_HCSRQ : SDWORD_T;
  signal WB_HCSR : std_logic;
  signal WB_HILLG : std_logic;
  signal WB_HCPQ : std_logic_vector(SDLEN-1 downto 0);
  signal WB_CSRQ : SDWORD_T;
  signal WB_ILLG : std_logic;
  signal WB_HCP : std_logic;
 
  -- debug-only modules
 
  component RV01_ST_CHECKER is
    generic(
      ST_FILENAME : string := "NONE"
   );
    port(
      CLK_i : in std_logic;
      ENB_i : in std_logic;
      LS_OP_i : in LS_OP_T;
      DWE_i : in std_logic;
      BE_i : in std_logic_vector(4-1 downto 0);
      DADR_i : in unsigned(ALEN-1 downto 0);
      DDATO_i : in std_logic_vector(SDLEN-1 downto 0)
    );
  end component;
 
  component RV01_WB_CHECKER is
    generic(
      WB_FILENAME : string := "NONE"
    );
    port(
      CLK_i : in std_logic;
      ENB_i : in std_logic;
      WE0_i : in std_logic;
      WE1_i : in std_logic;
      IX_INSTR0_i : in DEC_INSTR_T;
      IX_INSTR1_i : in DEC_INSTR_T;
      IX_DRD0_i : in SDWORD_T;
      IX_DRD1_i : in SDWORD_T
    );
  end component;
 
  component RV01_STATS is
    port(
      CLK_i : in std_logic;
      RST_i : in std_logic;
      ID_V_i : in std_logic_vector(2-1 downto 0);
      ID_PS_i : in std_logic_vector(2-1 downto 0);
      ID_PXE1_i : std_logic;
      IX2_V_i : in std_logic_vector(2-1 downto 0);
      STRT_i : in std_logic;
      HALT_i : in std_logic
    );
  end component;
 
begin
 
  ----------------------------------------------------
  -- Notes:
  ----------------------------------------------------
 
  -- *** Pipeline organisation ***
  -- RV0101 employs the following 7-stage pipeline:
  -- 1) Instruction Fetch (IF1)
  -- 2) Instruction Fetch (IF2)
  -- 3) Instruction Decode (ID)
  -- 4) Instruction Execute (IX1)
  -- 5) Instruction Execute (IX2)
  -- 6) Instruction Execute (IX3)
  -- 7) Write Back (WB)
 
  -- *** Branch & Jump processing ***
  -- When branch prediction is not enabled, branches and
  -- jumps are processed in IX1 stage and there's a fixed
  -- branch penalty of 2 cycles.
  -- When branch prediction is enabled, branches and jal
  -- instructions are predicted in IF2 stage using a branch
  -- history table (jalr instructions are not predicted
  -- at all). Prediction are verified in IX1 stage, so 
  -- penalty for mis-predicted branches is of 2 cycles.
 
  ----------------------------------------------------
  -- Reset
  ----------------------------------------------------
 
  IRST <= RST_i or WB_DRST;
 
  ----------------------------------------------------
  -- CPU initialization logic
  ----------------------------------------------------
 
  GINIT_1 : if(BRANCH_PREDICTION_ENABLED = '1') generate
 
  -- Branch prediction is enabled: initialize BHT RAM
  -- before starting the CPU.
 
  U_INIT: RV01_CPU_INIT
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      STRT_i => WB_XSTRT,
      RSM_i => ZERO,
      BHT_INIT_END_i => BHT_INIT_END,
 
      INIT_STRT_o => INIT_STRT,
      STRT_o => STRT
   );
 
   end generate;
 
   GINIT_0 : if(BRANCH_PREDICTION_ENABLED = '0') generate
 
   -- Branch prediction is disabled: start the CPU
   -- immediately.
 
   INIT_STRT <= '0';
   STRT <= WB_XSTRT;
 
   end generate;
 
  ----------------------------------------------------
  -- IF1 Stage:
  ----------------------------------------------------
 
  -- Instruction Fetch Logic 
 
  GPX_IF1_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
 
  U_FTCH : RV01_FTCHLOG_2W
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      STRT_i => STRT,
      STRTPC_i => WB_XSTRTPC,
      HALT_i => IX3_HALT,
      BJX_i => IX2_BJX,
      BJTA_i => IX2_BJTA,
      PBX_i => IF2_PBX,
      PBTA_i => IF2_PBTA,
      --KLL1_i => IF2_KLL1,
      KLL1_i => IF2_JRKLL1,
      PJRX_i => IF2_PJRX,
      PJRTA_i => IF2_PJRTA,
      EXCP_i => IX3_EXCP,
      ERET_i => IX3_ERET,
      RFTCH_i => IX3_RFTCH,
      ETVA_i => IX2_EERTA_q,
      PSTALL_i => ID_PSTALL,
      DHALT_i => IX3_HALT,
 
      IFV_o => IF1_V,
      IADR0_o => IF1_PC(0),
      IADR1_o => IF1_PC(1),
      IADR_MIS_o => IF1_IADR_MIS
    );
 
  end generate;
 
  GPX_IF1_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
 
  U_FTCH : RV01_FTCHLOG_1W
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      STRT_i => STRT,
      HALT_i => IX3_HALT,
      STRTPC_i => WB_XSTRTPC,
      BJX_i => IX2_BJX,
      BJTA_i => IX2_BJTA,
      PBX_i => IF2_PBX,
      PBTA_i => IF2_PBTA,
      --KLL1_i => IF2_KLL1,
      KLL1_i => IF2_JRKLL1,
      PJRX_i => IF2_PJRX,
      PJRTA_i => IF2_PJRTA,
      EXCP_i => IX3_EXCP,
      ERET_i => IX3_ERET,
      RFTCH_i => IX3_RFTCH,
      ETVA_i => IX2_EERTA_q,
      PSTALL_i => ID_PSTALL,
      DHALT_i => IX3_HALT,
 
      IFV_o => IF1_V(0),
      IADR0_o => IF1_PC(0),
      IADR_MIS_o => IF1_IADR_MIS
    );
 
  IF1_V(1) <= '0';
  IF1_PC(1) <= (others => '0');
 
  end generate;
 
  -- CPU Halt flag
  HALT_o <= WB_HALTD;
 
  -- Instruction address virtual to physical translation
  IADR_o <= IF1_PC(0);
 
  -- Pipeline Registers
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
 
      if(IRST = '1') then
        IF1_V_q <= "00";
      elsif(IX3_HALT = '1') then
        IF1_V_q <= "00";
      elsif(ID_PSTALL = '0') then
        if(WB_DFRCSI = '1') then
          IF1_V_q <= "01";
        else
          IF1_V_q <= IF1_V;
        end if;
      end if;
 
      if(IRST = '1') then
        IF1_DFRCSI_q <= '0';
      else
        IF1_DFRCSI_q <= WB_DFRCSI;
      end if;
 
      IF1_PC_q(0) <= IF1_PC(0);
      IF1_PC_q(1) <= IF1_PC(1);
      IF1_IADR_MIS_q <= (IF1_IADR_MIS & IF1_IADR_MIS);
 
    end if;
  end process;
 
  -- Exception processing: fetch logic detects address
  -- misalignments and records them into IF_ADR_MIS_q
  -- (each instruction of the pair get its own copy of
  -- the flag, in case instruction #0 is invalid).
 
  GBPE_0 : if(BRANCH_PREDICTION_ENABLED = '0') generate
 
  BHT_INIT_END <= '1';
  IF2_PBX <= '0';
  IF2_KLL1 <= '0';
  IF2_PBTA <= (others => '0');
  IF2_BPVD0 <= (others => '0');
  IF2_BPVD1 <= (others => '0');
 
  end generate;
 
  GBPE_1 : if(BRANCH_PREDICTION_ENABLED = '1') generate
 
  -- Branches (and jal's) prediction unit
 
  U_BPU : RV01_BPU
    generic map(
      BHT_SIZE => BHT_SIZE,
      PXE => PARALLEL_EXECUTION_ENABLED,
      NW => NW
    )
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      INIT_STRT_i => INIT_STRT,
      IF_V_i => IF1_V,
      IF_PC_i => IF1_PC,
      IF2_V_i => IF2_V,
      IF2_PC_i => IF1_PC_q,
      BHT_BTA_i => IX1_BHT_TA,
      BHT_PC_i => ID_PC_q,
      BHT_CNT0_i => IX1_BHT_CNT0,
      BHT_CNT1_i => IX1_BHT_CNT1,
      BHT_WE_i => IX1_BHT_WE,
 
      INIT_END_o => BHT_INIT_END,
      PBX_o => IF2_PBX,
      KLL1_o => IF2_KLL1,
      PBTA_o => IF2_PBTA,
      BPVD0_o => IF2_BPVD0,
      BPVD1_o => IF2_BPVD1
    );
 
  end generate;
 
  GJRPE_1 : if(JALR_PREDICTION_ENABLED = '1') generate
 
  U_JRPU : RV01_JRPU
    generic map(
      RAS_DEPTH => 4,
      JRVQ_DEPTH => 2,
      PXE => PARALLEL_EXECUTION_ENABLED,
      NW => NW
    )
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      CLR_i => IX3_CLRP,
      KLL1_i => IF2_KLL1,
      FSTLL_i => ID_PSTALL,
      BJX_i => IX2_BJX,
      INSTR_i => INSTR_i,
      IF2_V_i => IF1_V_q,
      IF2_INSTR_i => IF2_DEC_INSTR,
      IF2_PC_i => IF1_PC_q,
      IX1_V_i => ID_V_q,
      IX1_INSTR_i => ID_INSTR_q,
      IX1_OPA0_i => ID_OPA0_q,
      IX1_OPA1_i => ID_OPA1_q,
      IX1_PCP4_i(0) => IX1_PC0P4,
      IX1_PCP4_i(1) => IX1_PC1P4,
      IX3_V_i => IX2_V_q,
      IX3_INSTR_i => IX2_INSTR_q,
      IX3_PCP4_i(0) => IX2_PC0P4_q,
      IX3_PCP4_i(1) => IX2_PC1P4_q,
 
      KLL1_o => IF2_JRKLL1,
      PJRX_o => IF2_PJRX,
      PJRTA_o => IF2_PJRTA,
      MPJRX_o => IX1_MPJRX
    );
 
  end generate;
 
  GJRPE_0 : if(JALR_PREDICTION_ENABLED = '0') generate
  IF2_JRKLL1 <= '0';
  IF2_PJRX <= '0';
  IF2_PJRTA <= (others => '0');
  IX1_MPJRX <= "00";
  end generate;
 
  ----------------------------------------------------
  -- IF2 Stage
  ----------------------------------------------------
 
  -- Split instruction memory output into two individual instructions
 
  -- Note: slot #0 instrucion is forced to content of debug unit
  -- Stuff Instruction register when IF1_DFRCSI_q = '1'.
 
  IF2_INSTR0 <=
    INSTR_i(ILEN*1-1 downto ILEN*0) when IF1_DFRCSI_q = '0' else WB_DSI;
 
  IF2_INSTR1 <=
    INSTR_i(ILEN*2-1 downto ILEN*1);
 
  -- Pre-decode individual instructions
 
  U_IDEC0 : RV01_IDEC
    port map(
      INSTR_i => IF2_INSTR0,
      IADR_MIS_i => IF1_IADR_MIS_q(0),
      IADR_ERR_i => IADR_ERR_i,
 
      OPA_PC_o => IF2_OPA_PC(0),
      OPB_IMM_o => IF2_OPB_IMM(0),
      DEC_INSTR_o => IF2_DEC_INSTR(0)
    );
 
  GPX_IF2_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
 
  U_IDEC1 : RV01_IDEC
    port map(
      INSTR_i => IF2_INSTR1,
      IADR_MIS_i => IF1_IADR_MIS_q(1),
      IADR_ERR_i => IADR_ERR_i,
 
      OPA_PC_o => IF2_OPA_PC(1),
      OPB_IMM_o => IF2_OPB_IMM(1),
      DEC_INSTR_o => IF2_DEC_INSTR(1)
    );
 
  end generate;
 
  GPX_IF2_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
 
  IF2_OPA_PC(1) <= '0';
  IF2_OPB_IMM(1) <= '0';
  IF2_DEC_INSTR(1) <= DEC_NIL;
 
  end generate;
 
  -- Exception processing: instruction address errors
  -- are reported by memory sub-system using IADR_ERR_i.
  -- Illegal instructions are detected by decoding logic.
  -- All type of exception raised up to this point are
  -- recorded by IF2_DEC_INSTR*.[EXCP,EIS,ECAUSE].
 
  -- IF2 instruction valid bits (slot #1 instructions gets
  -- invalidated if slot #0 one is a predicted taken
  -- branch/jal or a jalr).
 
  IF2_V(0) <= IF1_V_q(0);
  IF2_V(1) <= IF1_V_q(1) and not(IF2_KLL1) and not(IF2_JRKLL1);
 
  -- IFQ valid bits "kill" flag (instructions in the
  -- queue must be invalidated when a branch/jump is
  -- executed, an exception is raised or an instruction
  -- is re-fetched).
 
  -- Instruction queue (includes pipeline registers
  -- between IF2 and ID stages).
 
  IF2_V_KILL <= IX2_BJX or IX3_CLRP;
 
  U_IFQ : RV01_IFQ
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      ID_HALT_i => IX3_HALT,
      IX_BJX_i => IF2_V_KILL,
      ID_ISSUE_i => ID_ISSUE,
      IF_V_i => IF2_V,
      IF_PC0_i => IF1_PC_q(0),
      IF_PC1_i => IF1_PC_q(1),
      IF_INSTR0_i => IF2_INSTR0,
      IF_INSTR1_i => IF2_INSTR1,
      IF_DEC_INSTR0_i => IF2_DEC_INSTR(0),
      IF_DEC_INSTR1_i => IF2_DEC_INSTR(1),
      IF_OPA_PC0_i => IF2_OPA_PC(0),
      IF_OPA_PC1_i => IF2_OPA_PC(1),
      IF_OPB_IMM0_i => IF2_OPB_IMM(0),
      IF_OPB_IMM1_i => IF2_OPB_IMM(1),
      IF_BPVD0_i => IF2_BPVD0,
      IF_BPVD1_i => IF2_BPVD1,
 
      PSTALL_o => ID_PSTALL,
      ID_V_o => IF2_V_q,
      ID_PC0_o => IF2_PC_q(0),
      ID_PC1_o => IF2_PC_q(1),
      ID_INSTR0_o => open,
      ID_INSTR1_o => open,
      ID_DEC_INSTR0_o => IF2_DEC_INSTR_q(0),
      ID_DEC_INSTR1_o => IF2_DEC_INSTR_q(1),
      ID_OPA_PC0_o => IF2_OPA_PC_q(0),
      ID_OPA_PC1_o => IF2_OPA_PC_q(1),
      ID_OPB_IMM0_o => IF2_OPB_IMM_q(0),
      ID_OPB_IMM1_o => IF2_OPB_IMM_q(1),
      ID_BPVD0_o => IF2_BPVD0_q,
      ID_BPVD1_o => IF2_BPVD1_q
    );
 
  ----------------------------------------------------
  -- ID Stage
  ----------------------------------------------------
 
  -- Pipeline stall logic
 
  U_PSTL0 : RV01_PSTLLOG_2W_P6
    generic map(
      DXE => DELAYED_EXECUTION_ENABLED,
      SIMULATION_ONLY => SIMULATION_ONLY
    )
    port map(
      CLK_i => CLK_i,
      ID_INSTR_i => IF2_DEC_INSTR_q(0),
      ID_V_i => IF2_V_q(0),
      IX1_INSTR0_i => ID_INSTR_q(0),
      IX1_INSTR1_i => ID_INSTR_q(1),
      IX1_V_i => ID_V_q,
      IX1_FWDE_i => ID_FWDX_q,
      IX2_INSTR0_i => IX1_INSTR_q(0),
      IX2_INSTR1_i => IX1_INSTR_q(1),
      IX2_V_i => IX1_V_q,
      IX2_FWDE_i => IX1_FWDX_q,
      IX3_INSTR0_i => IX2_INSTR_q(0),
      IX3_INSTR1_i => IX2_INSTR_q(1),
      IX3_V_i => IX2_V_q,
      IX3_FWDE_i => IX2_FWDX_q,
 
      OPA_V_o => ID_OPA0_V,
      OPB_V_o => ID_OPB0_V,
      DSA_o => ID_DSA0,
      DSB_o => ID_DSB0,
      PSTALL_o => ID_PS(0)
    );
 
  GPX_ID_0_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
 
  U_PSTL1 : RV01_PSTLLOG_2W_P6
    generic map(
      DXE => DELAYED_EXECUTION_ENABLED,
      SIMULATION_ONLY => SIMULATION_ONLY
    )
    port map(
      CLK_i => CLK_i,
      ID_INSTR_i => IF2_DEC_INSTR_q(1),
      ID_V_i => IF2_V_q(1),
      IX1_INSTR0_i => ID_INSTR_q(0),
      IX1_INSTR1_i => ID_INSTR_q(1),
      IX1_V_i => ID_V_q,
      IX1_FWDE_i => ID_FWDX_q,
      IX2_INSTR0_i => IX1_INSTR_q(0),
      IX2_INSTR1_i => IX1_INSTR_q(1),
      IX2_V_i => IX1_V_q,
      IX2_FWDE_i => IX1_FWDX_q,
      IX3_INSTR0_i => IX2_INSTR_q(0),
      IX3_INSTR1_i => IX2_INSTR_q(1),
      IX3_V_i => IX2_V_q,
      IX3_FWDE_i => IX2_FWDX_q,
 
      OPA_V_o => ID_OPA1_V,
      OPB_V_o => ID_OPB1_V,
      DSA_o => ID_DSA1,
      DSB_o => ID_DSB1,
      PSTALL_o => ID_PS(1)
    );
 
  end generate;
 
  GPX_ID_0_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
 
    ID_OPA1_V <= '0';
    ID_OPB1_V <= '0';
    ID_DSA1 <= '0';
    ID_DSB1 <= '0';
    ID_PS(1) <= '0';
 
  end generate;
 
  -- Parallel eXecution logic
 
  GPX_ID_1_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
 
  U_PXLOG : RV01_PXLOG
    port map(
      ID_INSTR0_i => IF2_DEC_INSTR_q(0),
      ID_INSTR1_i => IF2_DEC_INSTR_q(1),
      ID_V_i => IF2_V_q(2-1 downto 0),
      ID_FWDE_i => ID_FWDE,
 
      PXE1_o => ID_PXE1
    );
 
  end generate;
 
  GPX_ID_1_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
 
  ID_PXE1 <= '0';
 
  end generate;
 
  -- Instruction issue logic
 
  U_ISSLOG: RV01_ISSLOG
    generic map(
      NW => NW
    )
    port map(
      V_i => IF2_V_q,
      BJX_i => IX2_BJX,
      PC1_i => IF2_PC_q(1),
      PS_i => ID_PS,
      SBF_i => IX1_SBF,
      DIV_STRT_i => IX1_DIV_STRT,
      DIV_BSY_i => ID_DIV_BSY,
      SEQX_i => IF2_DEC_INSTR_q(0).SEQX,
      PXE_i => WB_PXE,
      PXE1_i => ID_PXE1,
      STEP_i => IX2_STEP,
      PSLP_i => IX1_PSLP,
 
      V_o => ID_V,
      JLRA_o => ID_JLRA,
      ISSUE_o => ID_ISSUE
    );
 
  -- Instruction #0 Operand A forward logic
 
  U_FWDLOGA0 : RV01_FWDLOG_2W_P6
    port map(
      ID_RX_i => IF2_DEC_INSTR_q(0).RS1,
      ID_RRX_i => IF2_DEC_INSTR_q(0).RRS1,
      IX1_INSTR0_i => ID_INSTR_q(0),
      IX2_INSTR0_i => IX1_INSTR_q(0),
      IX3_INSTR0_i => IX2_INSTR_q(0),
      IX1_INSTR1_i => ID_INSTR_q(1),
      IX2_INSTR1_i => IX1_INSTR_q(1),
      IX3_INSTR1_i => IX2_INSTR_q(1),
      IX1_PA_RES0_i => IX1_PA0_RES,
      IX1_PA_RES1_i => IX1_PA1_RES,
      IX2_PA_RES0_i => IX2_PA0_RES,
      IX2_PA_RES1_i => IX2_PA1_RES,
      IX3_PA_RES0_i => IX3_DRD0,
      IX3_PA_RES1_i => IX3_DRD1,
      ID_OPX_NOFWD_i => to_signed(WB_RDA0),
      IX1_V_i => ID_V_q,
      IX2_V_i => IX1_V_q,
      IX3_V_i => IX2_V_q,
      IX1_FWDE_i => ID_FWDX_q,
      IX2_FWDE_i => IX1_FWDX_q,
      IX3_FWDE_i => IX2_FWDX_q,
      NOREGS_i => IF2_OPA_PC_q(0),
      NOREGD_i => to_signed(ID_JLRA(0)),
 
      ID_OPX_o => ID_OPA0
    );
 
  -- Instruction #1 Operand A forward logic
 
  GPX_ID_2_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
 
  U_FWDLOGA1 : RV01_FWDLOG_2W_P6
    port map(
      ID_RX_i => IF2_DEC_INSTR_q(1).RS1,
      ID_RRX_i => IF2_DEC_INSTR_q(1).RRS1,
      IX1_INSTR0_i => ID_INSTR_q(0),
      IX2_INSTR0_i => IX1_INSTR_q(0),
      IX3_INSTR0_i => IX2_INSTR_q(0),
      IX1_INSTR1_i => ID_INSTR_q(1),
      IX2_INSTR1_i => IX1_INSTR_q(1),
      IX3_INSTR1_i => IX2_INSTR_q(1),
      IX1_PA_RES0_i => IX1_PA0_RES,
      IX1_PA_RES1_i => IX1_PA1_RES,
      IX2_PA_RES0_i => IX2_PA0_RES,
      IX2_PA_RES1_i => IX2_PA1_RES,
      IX3_PA_RES0_i => IX3_DRD0,
      IX3_PA_RES1_i => IX3_DRD1,
      ID_OPX_NOFWD_i => to_signed(WB_RDA1),
      IX1_V_i => ID_V_q,
      IX2_V_i => IX1_V_q,
      IX3_V_i => IX2_V_q,
      IX1_FWDE_i => ID_FWDX_q,
      IX2_FWDE_i => IX1_FWDX_q,
      IX3_FWDE_i => IX2_FWDX_q,
      NOREGS_i => IF2_OPA_PC_q(1),
      NOREGD_i => to_signed(ID_JLRA(1)),
 
      ID_OPX_o => ID_OPA1
    );
 
  end generate;
 
  GPX_ID_2_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
 
  ID_OPA1 <= (others => '0');
 
  end generate;
 
  -- Instruction #0 Operand B forward logic
 
  U_FWDLOGB0 : RV01_FWDLOG_2W_P6
    port map(
      ID_RX_i => IF2_DEC_INSTR_q(0).RS2,
      ID_RRX_i => IF2_DEC_INSTR_q(0).RRS2,
      IX1_INSTR0_i => ID_INSTR_q(0),
      IX2_INSTR0_i => IX1_INSTR_q(0),
      IX3_INSTR0_i => IX2_INSTR_q(0),
      IX1_INSTR1_i => ID_INSTR_q(1),
      IX2_INSTR1_i => IX1_INSTR_q(1),
      IX3_INSTR1_i => IX2_INSTR_q(1),
      IX1_PA_RES0_i => IX1_PA0_RES,
      IX1_PA_RES1_i => IX1_PA1_RES,
      IX2_PA_RES0_i => IX2_PA0_RES,
      IX2_PA_RES1_i => IX2_PA1_RES,
      IX3_PA_RES0_i => IX3_DRD0,
      IX3_PA_RES1_i => IX3_DRD1,
      ID_OPX_NOFWD_i => to_signed(WB_RDB0),
      IX1_V_i => ID_V_q,
      IX2_V_i => IX1_V_q,
      IX3_V_i => IX2_V_q,
      IX1_FWDE_i => ID_FWDX_q,
      IX2_FWDE_i => IX1_FWDX_q,
      IX3_FWDE_i => IX2_FWDX_q,
      NOREGS_i => IF2_OPB_IMM_q(0),
      NOREGD_i => IF2_DEC_INSTR_q(0).IMM,
 
      ID_OPX_o => ID_OPB0
    );
 
  -- Instruction #1 Operand B forward logic
 
  GPX_ID_3_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
 
  U_FWDLOGB1 : RV01_FWDLOG_2W_P6
    port map(
      ID_RX_i => IF2_DEC_INSTR_q(1).RS2,
      ID_RRX_i => IF2_DEC_INSTR_q(1).RRS2,
      IX1_INSTR0_i => ID_INSTR_q(0),
      IX2_INSTR0_i => IX1_INSTR_q(0),
      IX3_INSTR0_i => IX2_INSTR_q(0),
      IX1_INSTR1_i => ID_INSTR_q(1),
      IX2_INSTR1_i => IX1_INSTR_q(1),
      IX3_INSTR1_i => IX2_INSTR_q(1),
      IX1_PA_RES0_i => IX1_PA0_RES,
      IX1_PA_RES1_i => IX1_PA1_RES,
      IX2_PA_RES0_i => IX2_PA0_RES,
      IX2_PA_RES1_i => IX2_PA1_RES,
      IX3_PA_RES0_i => IX3_DRD0,
      IX3_PA_RES1_i => IX3_DRD1,
      ID_OPX_NOFWD_i => to_signed(WB_RDB1),
      IX1_V_i => ID_V_q,
      IX2_V_i => IX1_V_q,
      IX3_V_i => IX2_V_q,
      IX1_FWDE_i => ID_FWDX_q,
      IX2_FWDE_i => IX1_FWDX_q,
      IX3_FWDE_i => IX2_FWDX_q,
      NOREGS_i => IF2_OPB_IMM_q(1),
      NOREGD_i => IF2_DEC_INSTR_q(1).IMM,
 
      ID_OPX_o => ID_OPB1
    );
 
  end generate;
 
  GPX_ID_3_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
 
  ID_OPB1 <= (others => '0');
 
  end generate;
 
  -- Pipeline-A (dedicated) pre-decoder
 
  U_PADEC0 : RV01_PIPE_A_DEC
    port map(
      INSTR_i => IF2_DEC_INSTR_q(0),
 
      FWDE_o => ID_FWDE(0),
      SEL_o => ID_PASEL0
    );
 
  GPX_ID_4_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
 
  U_PADEC1 : RV01_PIPE_A_DEC
    port map(
      INSTR_i => IF2_DEC_INSTR_q(1),
 
      FWDE_o => ID_FWDE(1),
      SEL_o => ID_PASEL1
    );
 
  end generate;
 
  GPX_ID_4_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
 
  ID_FWDE(1) <= '0';
  ID_PASEL1 <= (others => '0');
 
  end generate;
 
  -- Pipeline Registers 
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(IRST = '1' or IX3_CLRP = '1') then
        ID_V_q <= "00";
      else
        ID_V_q(0) <= ID_V(0);
        ID_V_q(1) <= ID_V(1) or (IX1_PSLP and not(IX2_BJX));
      end if;
        ID_PC_q(0) <= IF2_PC_q(0);
        ID_INSTR_q(0) <= IF2_DEC_INSTR_q(0);
        ID_OPA0_q <= ID_OPA0;
        ID_OPB0_q <= ID_OPB0;
        ID_FWDE_q(0) <= ID_FWDE(0);
        ID_FWDX_q(0) <= ID_FWDE(0) and ID_OPA0_V and ID_OPB0_V;
        ID_PASEL0_q <= ID_PASEL0;
        ID_BPVD0_q <= IF2_BPVD0_q;
        ID_OPA0_V_q <= ID_OPA0_V;
        ID_OPB0_V_q <= ID_OPB0_V;
        ID_DSA0_q <= ID_DSA0;
        ID_DSB0_q <= ID_DSB0;
      if(IX1_PSLP = '0') then
        ID_PC_q(1) <= IF2_PC_q(1);
        ID_INSTR_q(1) <= IF2_DEC_INSTR_q(1);
        ID_OPA1_q <= ID_OPA1;
        ID_OPB1_q <= ID_OPB1;
        ID_FWDE_q(1) <= ID_FWDE(1);
        ID_FWDX_q(1) <= ID_FWDE(1) and ID_OPA1_V and ID_OPB1_V;
        ID_PASEL1_q <= ID_PASEL1;
        ID_BPVD1_q <= IF2_BPVD1_q;
        ID_OPA1_V_q <= ID_OPA1_V;
        ID_OPB1_V_q <= ID_OPB1_V;
        ID_DSA1_q <= ID_DSA1;
        ID_DSB1_q <= ID_DSB1;
      end if;
    end if;
  end process;
 
  ----------------------------------------------------
  -- IX1 Stage
  ----------------------------------------------------
 
  -- Pipeline-A
 
  -- Delayed Execution pipeline-A
 
  U_PA0ALU_X1: RV01_PIPE_A_ALU
    port map(
      SEL_i => ID_PASEL0_q,
      SU_i => ID_INSTR_q(0).SU,
      OP_i => ID_INSTR_q(0).ALU_OP,
      OPA_i => ID_OPA0_q,
      OPB_i => ID_OPB0_q,
 
      RES_o => IX1_PA0_ALU_RES
    );
 
  GPX_X1_1_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
 
  U_PA1ALU_X1: RV01_PIPE_A_ALU
    port map(
      SEL_i => ID_PASEL1_q,
      SU_i => ID_INSTR_q(1).SU,
      OP_i => ID_INSTR_q(1).ALU_OP,
      OPA_i => ID_OPA1_q,
      OPB_i => ID_OPB1_q,
 
      RES_o => IX1_PA1_ALU_RES
    );
 
  end generate; -- GPX_X1_1_1
 
  IX1_SHFT0 <= to_unsigned(ID_OPB0_q(5-1 downto 0));
 
  process(ID_INSTR_q(0))
  begin
    case ID_INSTR_q(0).ALU_OP is
      when ALU_SHL =>
        IX1_SHF_CTRL0 <= SC_SHL;
      when ALU_SHR =>
        IX1_SHF_CTRL0 <= SC_SHR;
      when others =>
        IX1_SHF_CTRL0 <= SC_NIL;
    end case;
  end process;
 
  U_SHF0 : RV01_SHFTU
    port map(
      CTRL_i => IX1_SHF_CTRL0,
      SI_i => ID_OPA0_q,
      SHFT_i => IX1_SHFT0,
      SU_i => ID_INSTR_q(0).SU,
 
      SO_o => IX1_SHF_RES0
    );
 
  GPX_X1_2_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
 
  IX1_SHFT1 <= to_unsigned(ID_OPB1_q(5-1 downto 0));
 
  process(ID_INSTR_q(1))
  begin
    case ID_INSTR_q(1).ALU_OP is
      when ALU_SHL =>
        IX1_SHF_CTRL1 <= SC_SHL;
      when ALU_SHR =>
        IX1_SHF_CTRL1 <= SC_SHR;
      when others =>
        IX1_SHF_CTRL1 <= SC_NIL;
    end case;
  end process;
 
  U_SHF1 : RV01_SHFTU
    port map(
      CTRL_i => IX1_SHF_CTRL1,
      SI_i => ID_OPA1_q,
      SHFT_i => IX1_SHFT1,
      SU_i => ID_INSTR_q(1).SU,
 
      SO_o => IX1_SHF_RES1
    );
 
  end generate; -- GPX_X1_2_1
 
  GDX1_1 : if(DELAYED_EXECUTION_ENABLED = '1') generate
 
  -- DX Pipe registers (IX1->IX2)
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(IRST = '1') then
        IX1_OPA0_V_q <= '0';
        IX1_OPB0_V_q <= '0';
        IX1_OPA1_V_q <= '0';
        IX1_OPB1_V_q <= '0';
      else
        IX1_OPA0_V_q <= IX1_OPA0_V and not(ID_DSA0_q);
        IX1_OPB0_V_q <= IX1_OPB0_V and not(ID_DSB0_q);
        IX1_OPA1_V_q <= IX1_OPA1_V and not(ID_DSA1_q);
        IX1_OPB1_V_q <= IX1_OPB1_V and not(ID_DSB1_q);
      end if;
      IX1_OPA0_q <= IX1_OPA0;
      IX1_OPB0_q <= IX1_OPB0;
      IX1_OPA1_q <= IX1_OPA1;
      IX1_OPB1_q <= IX1_OPB1;
    end if;
  end process;
 
  end generate;
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      IX1_PASEL0_q <= ID_PASEL0_q;
      IX1_PASEL1_q <= ID_PASEL1_q;
    end if;
  end process;
 
  U_RMUX1 : RV01_RESMUX_IX1
    generic map(
      PXE => PARALLEL_EXECUTION_ENABLED,
      DXE => DELAYED_EXECUTION_ENABLED,
      NW => NW
    )
    port map(
      OPA0_V_i => ID_OPA0_V_q,
      OPA1_V_i => ID_OPA1_V_q,
      OPA0_i => ID_OPA0_q,
      OPA1_i => ID_OPA1_q,
      OPB0_V_i => ID_OPB0_V_q,
      OPB1_V_i => ID_OPB1_V_q,
      OPB0_i => ID_OPB0_q,
      OPB1_i => ID_OPB1_q,
      SHF_RES0_i => IX1_SHF_RES0,
      SHF_RES1_i => IX1_SHF_RES1,
      PA0_ALU_RES_i => IX1_PA0_ALU_RES,
      PA1_ALU_RES_i => IX1_PA1_ALU_RES,
      DIV_V_i => IX1_DIV_V,
      DIV_RES_i => IX1_DIV_RES,
      PASEL0_i => ID_PASEL0_q,
      PASEL1_i => ID_PASEL1_q,
      FWDE_i => ID_FWDE_q,
      DSA0_i => ID_DSA0_q,
      DSB0_i => ID_DSB0_q,
      DSA1_i => ID_DSA1_q,
      DSB1_i => ID_DSB1_q,
      INSTR_i => ID_INSTR_q,
      IX3_DRD0_i => IX3_DRD0,
      IX3_DRD1_i => IX3_DRD1,
      IX3_V_i => IX2_V_q,
      IX3_INSTR_i => IX2_INSTR_q,
 
      FWDX_o => IX1_FWDX,
      PA0_RES_o => IX1_PA0_RES,
      PA1_RES_o => IX1_PA1_RES,
      OPA0_V_o => IX1_OPA0_V,
      OPA1_V_o => IX1_OPA1_V,
      OPA0_o => IX1_OPA0,
      OPA1_o => IX1_OPA1,
      OPB0_V_o => IX1_OPB0_V,
      OPB1_V_o => IX1_OPB1_V,
      OPB0_o => IX1_OPB0,
      OPB1_o => IX1_OPB1,
      DRD0_V_o => IX1_DRD0_V,
      DRD1_V_o => IX1_DRD1_V,
      DRD0_o => IX1_DRD0,
      DRD1_o => IX1_DRD1
    );
 
  -- Pipeline-B
 
  IX1_PC0P4 <= ID_PC_q(0) + 4;
  IX1_PC1P4 <= ID_PC_q(1) + 4;
 
  U_PIPEB : RV01_PIPE_B
    port map(
      CLK_i => CLK_i,
      OP_i => ID_INSTR_q(0).ALU_OP,
      SU_i => ID_INSTR_q(0).SU,
      PC0_i => ID_PC_q(0),
      PC1_i => IX1_PC0P4_q,
      OPA_i => ID_OPA0_q,
      OPB_i => ID_OPB0_q,
 
      RES_o => IX2_PB0_RES
    );
 
  GBJX0 : if BRANCH_PREDICTION_ENABLED = '0' generate
 
  -- Branch/Jump processing logic (pipe #0)
 
  U_BJXLOG0 : RV01_BJXLOG
    generic map(
      JRPE => JALR_PREDICTION_ENABLED
    )
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      BJ_OP_i => ID_INSTR_q(0).BJ_OP,
      SU_i => ID_INSTR_q(0).SU,
      PC_i => ID_PC_q(0),
      OPA_i => ID_OPA0_q,
      OPB_i => ID_OPB0_q,
      IMM_i => ID_INSTR_q(0).IMM,
      IV_i => ID_V_q(0),
      FSTLL_i => ID_PSTALL,
      MPJRX_i => IX1_MPJRX(0),
 
      BJX_o => IX1_BJX0,
      BJTA_o => IX1_BJTA0
    );
 
  GPX_X1_6_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
 
  -- Branch/Jump processing logic (pipe #1)
 
  U_BJXLOG1 : RV01_BJXLOG
    generic map(
      JRPE => JALR_PREDICTION_ENABLED
    )
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      BJ_OP_i => ID_INSTR_q(1).BJ_OP,
      SU_i => ID_INSTR_q(1).SU,
      PC_i => ID_PC_q(1),
      OPA_i => ID_OPA1_q,
      OPB_i => ID_OPB1_q,
      IMM_i => ID_INSTR_q(1).IMM,
      IV_i => ID_V_q(1),
      FSTLL_i => ID_PSTALL,
      MPJRX_i => IX1_MPJRX(1),
 
      BJX_o => IX1_BJX1,
      BJTA_o => IX1_BJTA1
    );
 
  IX1_B2BAC <= '0';
 
  end generate; -- GPX_X1_6_1
 
  GPX_X1_6_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
 
  IX1_BJX1 <= '0';
  IX1_BJTA1 <= (others =>'0');
 
  end generate; -- GPX_X1_6_0
 
  end generate;
 
  GBJX1 : if BRANCH_PREDICTION_ENABLED = '1' generate
 
  -- Branch/Jump processing logic (pipe #0)
 
  U_BJXLOG0 : RV01_BJXLOG_BV
    generic map(
      JRPE => JALR_PREDICTION_ENABLED
    )
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      BJ_OP_i => ID_INSTR_q(0).BJ_OP,
      SU_i => ID_INSTR_q(0).SU,
      PC_i => ID_PC_q(0),
      OPA_i => ID_OPA0_q,
      OPB_i => ID_OPB0_q,
      IMM_i => ID_INSTR_q(0).IMM,
      IV_i => ID_V_q(0),
      FSTLL_i => ID_PSTALL,
      BPVD_i => ID_BPVD0_q,
      MPJRX_i => IX1_MPJRX(0),
 
      BJX_o => IX1_BJX0,
      BJTA_o => IX1_BJTA0,
      BHT_WE_o => IX1_BHT_WE(0),
      BHT_TA_o => IX1_BHT_TA(0),
      BHT_PC_o => open,
      BHT_CNT_o => IX1_BHT_CNT0
    );
 
  GPX_X1_6_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
 
  -- Branch/Jump processing logic (pipe #1)
 
  U_BJXLOG1 : RV01_BJXLOG_BV
    generic map(
      JRPE => JALR_PREDICTION_ENABLED
    )
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      BJ_OP_i => ID_INSTR_q(1).BJ_OP,
      SU_i => ID_INSTR_q(1).SU,
      PC_i => ID_PC_q(1),
      OPA_i => ID_OPA1_q,
      OPB_i => ID_OPB1_q,
      IMM_i => ID_INSTR_q(1).IMM,
      IV_i => ID_V_q(1),
      FSTLL_i => ID_PSTALL,
      BPVD_i => ID_BPVD1_q,
      MPJRX_i => IX1_MPJRX(1),
 
      BJX_o => IX1_BJX1,
      BJTA_o => IX1_BJTA1,
      BHT_WE_o => IX1_BHT_PWE,
      BHT_TA_o => IX1_BHT_TA(1),
      BHT_PC_o => open,
      BHT_CNT_o => IX1_BHT_CNT1
    );
 
    -- IX1 slot #1 BHT write-enable flag must be
    -- cleared if there's a jump or taken branch in slot #0, 
    -- or a branch-2-branch address conflict causing slot #1 re-fetch. 
    IX1_BHT_WE(1) <= IX1_BHT_PWE and not(IX1_BJX0) and not(IX1_B2BAC);
 
    -- branch-2-branch address conflict flag (an even-even, or
    -- odd-odd, branch pair can't be handled by BHT update logic)
    IX1_B2BAC <= (IX1_BHT_WE(0) and IX1_BHT_PWE) when
      (ID_PC_q(0)(2) = ID_PC_q(1)(2)) else '0';
 
  end generate; -- GPX_X1_6_1
 
  GPX_X1_6_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
 
  IX1_BJX1 <= '0';
  IX1_BJTA1 <= (others => '0');
  IX1_BHT_WE(1) <= '0';
  IX1_BHT_TA(1) <= (others => '0');
  IX1_BHT_CNT1 <= (others => '0');
  IX1_B2BAC <= '0';
 
  end generate; -- GPX_X1_6_0
 
  end generate;
 
  -- Branch/Jump eXecute flag
  IX1_BJX <= IX1_BJX0 or IX1_BJX1;
 
  -- Branch/Jump target address mux (slot #0 takes
  -- priority because it holds oldest instruction).
 
  IX1_BJTA <= IX1_BJTA0 when (
    IX1_BJX0 = '1' or PARALLEL_EXECUTION_ENABLED = '0'
  ) else IX1_BJTA1;
 
  -- Instruction valid flags
 
  -- IX1 slot #0 valid flag is just a copy of ID one.
  IX1_V(0) <= ID_V_q(0) and not(IX2_BJX);
 
  -- IX1 slot #1 valid flag must be cleared if there's
  -- a jump or taken branch in slot #0.
  IX1_V(1) <= ID_V_q(1) and not(IX2_BJX);
 
  -- Load/Store logic
 
  U_LSU0 : RV01_LSU
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      IV_i => ID_V_q(0),
      LS_OP_i => ID_INSTR_q(0).LS_OP,
      SU_i => ID_INSTR_q(0).SU,
      OPA_i => ID_OPA0_q,
      OPB_i => ID_OPB0_q,
      IMM_i => ID_INSTR_q(0).IMM,
      LDAT_i => DDAT0_i,
 
      RE_o => DRE_o(0),
      WE_o => IX1_PDWE(0),
      MALGN_o => IX1_MALGN(0),
      ADR_o => IX1_DADR0,
      SBE_o => IX1_DBE0,
      SDAT_o => IX1_DDATO0,
      LDATV_o => IX3_LDAT0_V,
      LDAT_o => IX3_LDAT0
    );
 
  GPX_X1_7_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
 
  U_LSU1 : RV01_LSU
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      IV_i => ID_V_q(1),
      LS_OP_i => ID_INSTR_q(1).LS_OP,
      SU_i => ID_INSTR_q(1).SU,
      OPA_i => ID_OPA1_q,
      OPB_i => ID_OPB1_q,
      IMM_i => ID_INSTR_q(1).IMM,
      LDAT_i => DDAT1_i,
 
      RE_o => DRE_o(1),
      WE_o => IX1_PDWE(1),
      MALGN_o => IX1_MALGN(1),
      ADR_o => IX1_DADR1,
      SBE_o => IX1_DBE1,
      SDAT_o => IX1_DDATO1,
      LDATV_o => IX3_LDAT1_V,
      LDAT_o => IX3_LDAT1
    );
 
  end generate; -- GPX_X1_7_1
 
  GPX_X1_7_0 : if(PARALLEL_EXECUTION_ENABLED = '0') generate
 
  DRE_o(1) <= '0';
  IX1_PDWE(1) <= '0';
  IX1_MALGN(1) <= '0';
  IX1_DADR1 <= (others => '0');
  IX1_DBE1 <= (others => '0');
  IX1_DDATO1 <= (others => '0');
  IX3_LDAT1_V <= '0';
  IX3_LDAT1 <= (others => '0');
 
  end generate; -- GPX_X1_7_0
 
  -- Slot #1 DWE must be cleared if there's
  -- a jump or taken branch in slot #0.
 
  IX1_DWE(0) <= IX1_PDWE(0) and not(IX2_BJX);
  IX1_DWE(1) <= IX1_PDWE(1) and not(IX2_BJX);
 
  -- "Kill Top Store" flag (remove an invalidated
  -- store from store buffer).
 
  IX1_KTS <= IX1_PDWE(1) and IX1_BJX0 and not(IX2_BJX);
 
  -- Data address virtual to address translation
 
  IX1_PDADR0 <= IX1_DADR0 - IMEM_SIZE*4;
  IX1_PDADR1 <= IX1_DADR1 - IMEM_SIZE*4;
  IX1_PDIADR0 <= IX1_DADR0;
  IX1_PDIADR1 <= IX1_DADR1;
  IX3_PDADR0 <= IX3_DADR0 - IMEM_SIZE*4;
  IX3_PDIADR0 <= IX3_DADR0;
 
  DADR0_o <= IX3_PDADR0 when(IX3_DWE = '1') else IX1_PDADR0;
  DADR1_o <= IX1_PDADR1;
 
  DIADR0_o <= IX3_PDIADR0 when(IX3_DWE = '1') else IX1_PDIADR0;
  DIADR1_o <= IX1_PDIADR1;
 
  -- Data/Instructions memory selection logic
 
  U_DIMSLOG : RV01_DIMSLOG
    generic map(
      IMEM_LOWM => IMEM_LOWM,
      IMEM_SIZE => IMEM_SIZE,
      DMEM_SIZE => DMEM_SIZE
    )
    port map(
      IX1_OPA0_i => ID_OPA0_q,
      IX1_OPA1_i => ID_OPA1_q,
      IX1_IMM0_i => ID_INSTR_q(0).IMM,
      IX1_IMM1_i => ID_INSTR_q(1).IMM,
      IX1_DADR0_i => IX1_DADR0,
      IX1_DADR1_i => IX1_DADR1,
      IX3_DADR0_i => IX3_DADR0,
 
      IX1_DIMS_o => IX1_DIMS,
      IX3_DIMS_o => IX3_DIMS
  );
 
  -- When a store is committed, its address and the related
  -- memory selection flag value must be forced on DADR0_o
  -- and DIMS_o(0). 
 
  DIMS_o(0) <= IX3_DIMS when (IX3_DWE = '1') else IX1_DIMS(0);
  DIMS_o(1) <= IX1_DIMS(1) and PARALLEL_EXECUTION_ENABLED;
 
  -- Memory interface signals
 
  DBE_o <= IX3_DBE;
  DWE0_o <= IX3_DWE;
  DDAT0_o <= IX3_SDATO;
 
  -- Store buffer
 
  U_SBUF : RV01_SBUF_2W
    generic map(
      NW => NW,
      DEPTH => 16,
      SIMULATION_ONLY => SIMULATION_ONLY
    )
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      CLRB_i => IX3_CLRP,
      KTS_i => IX1_KTS_q,
      RE_i => IX3_SBRE,
      WE_i => IX1_DWE,
      BE0_i => IX1_DBE0,
      BE1_i => IX1_DBE1,
      D0_i => IX1_DDATO0,
      D1_i => IX1_DDATO1,
      IX1_V_i => ID_V_q,
      LS_OP0_i => ID_INSTR_q(0).LS_OP,
      LS_OP1_i => ID_INSTR_q(1).LS_OP,
      DADR0_i => IX1_DADR0,
      DADR1_i => IX1_DADR1,
      SADR0_i => IX2_DADR0_q,
      SADR1_i => IX2_DADR1_q,
 
      BF_o => IX1_SBF,
      NOPR_o => IX1_NOPR,
      S2LAC_o => IX1_S2LAC,
      WE_o => IX3_DWE,
      LS_OP_o => IX3_LS_OP,
      BE_o => IX3_DBE,
      Q_o => IX3_SDATO,
      SADR_o => IX3_DADR0
    );
 
  -- Divider support logic
 
  U_DIVLOG:  RV01_DIVLOG
    port map(
      V_i => IX1_V(0), --ID_V_q(0),
      INSTR_i => ID_INSTR_q(0),
      DIV_V_i => IX1_DIV_V,
 
      DIV_STRT_o => IX1_DIV_STRT,
      DIV_QS_o => IX1_DIV_QS,
      DIV_CLRV_o => IX1_DIV_CLRV
    );
 
  -- Divider unit
 
  U_DIV : RV01_DIVIDER_R2
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      STRT_i => IX1_DIV_STRT,
      SU_i => ID_INSTR_q(0).SU,
      QS_i => IX1_DIV_QS,
      DD_i => ID_OPA0_q,
      DR_i => ID_OPB0_q,
      CLRD_i => IX3_CLRD,
      CLRV_i => IX1_DIV_CLRV,
 
      Q_o => IX1_DIV_RES,
      QV_o => IX1_DIV_V,
      BSY_o => ID_DIV_BSY
    );
 
  -- Exception processing
 
  U_EXCPLX1 : RV01_EXCPLOG_IX1
    generic map(
      NW => NW
    )
    port map(
      INSTR_i => ID_INSTR_q,
      MALGN_i => IX1_MALGN,
      S2LAC_i => IX1_S2LAC,
      B2BAC_i => IX1_B2BAC,
      DIV_V_i => IX1_DIV_V,
      IDADR_CFLT_i => IDADR_CFLT_i,
 
      PSLP_o => IX1_PSLP,
      INSTR_o => IX1_INSTR
    );
 
  -- Pipeline Registers
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(IRST = '1' or IX3_CLRP = '1') then
        IX1_V_q <= "00";
        IX1_BJX0_q <= '0';
        IX1_BJX1_q <= '0';
        IX1_KTS_q <= '0';
      else
        IX1_V_q(0) <= IX1_V(0);
        IX1_V_q(1) <= IX1_V(1) and not(IX1_PSLP);
        IX1_BJX0_q <= IX1_BJX0;
        IX1_BJX1_q <= IX1_BJX1;
        IX1_KTS_q <= IX1_KTS;
      end if;
        IX1_INSTR_q(0) <= IX1_INSTR(0);
        IX1_FWDE_q(0) <= ID_FWDE_q(0);
        IX1_FWDX_q(0) <= IX1_FWDX(0);
        IX1_PC0P4_q <= IX1_PC0P4;
        IX1_PC0_q <= ID_PC_q(0);
        IX1_DADR0_q <= IX1_DADR0;
        IX1_DWE_q <= IX1_DWE and not('0' & IX1_KTS);
        IX1_DRD0_q <= IX1_DRD0;
        IX1_DRD0_V_q <= IX1_DRD0_V;
        IX1_INSTR_q(1) <= IX1_INSTR(1);
        IX1_FWDE_q(1) <= ID_FWDE_q(1);
        IX1_FWDX_q(1) <= IX1_FWDX(1);
        IX1_PC1P4_q <= IX1_PC1P4;
        IX1_PC1_q <= ID_PC_q(1);
        IX1_DADR1_q <= IX1_DADR1;
        IX1_DRD1_q <= IX1_DRD1;
        IX1_DRD1_V_q <= IX1_DRD1_V;
        IX1_BJTA0_q <= IX1_BJTA0;
        IX1_BJTA1_q <= IX1_BJTA1;
    end if;
  end process;
 
  ----------------------------------------------------
  -- Store Checker & Log File Generator
  ----------------------------------------------------
 
  -- synthesis translate_off
 
  G_ST : if(SIMULATION_ONLY = '1') generate
 
  U_STCHK : RV01_ST_CHECKER
    generic map(
      ST_FILENAME => ST_FILENAME
    )
    port map(
      CLK_i => CLK_i,
      ENB_i => CHK_ENB_i,
      LS_OP_i => IX3_LS_OP,
      DWE_i => IX3_DWE,
      BE_i => IX3_DBE,
      DADR_i => IX3_DADR0,
      DDATO_i => IX3_SDATO
    );
 
  end generate;
 
  -- synthesis translate_on
 
  ----------------------------------------------------
  -- IX2 Stage
  ----------------------------------------------------
 
  -- In stage IX2 results from pipe #0 A and B 
  -- sub-pipes get merged, making all result available
  -- for forwarding.
 
  -- FWDE(n) signal flags that instruction in slot #n
  -- belong to subset enabled to forward results, while
  -- FWDX(n) signal flags that instruction in slot #n
  -- has a result ready for forwarding (i.e. generated
  -- from valid operands).
 
  -- pipe #0 carries also pipe-B instructions which
  -- have FWDE(0) set to zero, but are allowed to
  -- forward results from IX3 stage.
 
  -- Branch/Jump eXecute flag
  IX2_BJX <=
    (IX1_BJX0_q and IX1_V_q(0)) or
    (IX1_BJX1_q and IX1_V_q(1));
 
  -- Branch/Jump target address mux (slot #0 takes
  -- priority because it holds oldest instruction).
 
  IX2_BJTA <= IX1_BJTA0_q when (
    (IX1_BJX0_q = '1' and IX1_V_q(0) = '1') or PARALLEL_EXECUTION_ENABLED = '0'
  ) else IX1_BJTA1_q;
 
  GDX2_1 : if(DELAYED_EXECUTION_ENABLED = '1') generate
 
   U_PA0ALU_X2: RV01_PIPE_A_ALU
    port map(
      SEL_i => IX1_PASEL0_q,
      SU_i => IX1_INSTR_q(0).SU,
      OP_i => IX1_INSTR_q(0).ALU_OP,
      OPA_i => IX1_OPA0_q,
      OPB_i => IX1_OPB0_q,
 
      RES_o => IX2_PA0_ALU_RES
    );
 
  GPX_X2_0_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
 
  U_PA1ALU_X2: RV01_PIPE_A_ALU
    port map(
      SEL_i => IX1_PASEL1_q,
      SU_i => IX1_INSTR_q(1).SU,
      OP_i => IX1_INSTR_q(1).ALU_OP,
      OPA_i => IX1_OPA1_q,
      OPB_i => IX1_OPB1_q,
 
      RES_o => IX2_PA1_ALU_RES
    );
 
  end generate; -- GPX_X2_0_1
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      IX2_OPA0_q <= IX2_OPA0;
      IX2_OPB0_q <= IX2_OPB0;
      IX2_OPA1_q <= IX2_OPA1;
      IX2_OPB1_q <= IX2_OPB1;
    end if;
  end process;
 
  end generate; -- GDX2_1  
 
  U_RMX2 : RV01_RESMUX_IX2
    generic map(
      PXE => PARALLEL_EXECUTION_ENABLED,
      DXE => DELAYED_EXECUTION_ENABLED,
      NW => NW
    )
    port map(
      OPA0_V_i => IX1_OPA0_V_q,
      OPA1_V_i => IX1_OPA1_V_q,
      OPA0_i => IX1_OPA0_q,
      OPA1_i => IX1_OPA1_q,
      OPB0_V_i => IX1_OPB0_V_q,
      OPB1_V_i => IX1_OPB1_V_q,
      OPB0_i => IX1_OPB0_q,
      OPB1_i => IX1_OPB1_q,
      DRD0_V_i => IX1_DRD0_V_q,
      DRD1_V_i => IX1_DRD1_V_q,
      DRD0_i => IX1_DRD0_q,
      DRD1_i => IX1_DRD1_q,
      DDAT0_i => DDAT0_i,
      DDAT1_i => DDAT1_i,
      PA0_ALU_RES_i => IX2_PA0_ALU_RES,
      PA1_ALU_RES_i => IX2_PA1_ALU_RES,
      PB0_RES_i => IX2_PB0_RES,
      PC1P4_i => IX1_PC1P4_q,
      PASEL0_i => IX1_PASEL0_q,
      PASEL1_i => IX1_PASEL1_q,
      FWDE_i => IX1_FWDE_q,
      INSTR_i => IX1_INSTR_q,
      IX3_DRD0_i => IX3_DRD0,
      IX3_DRD1_i => IX3_DRD1,
      IX3_V_i => IX2_V_q,
      IX3_INSTR_i => IX2_INSTR_q,
 
      FWDX_o => IX2_FWDX,
      PA0_RES_o => IX2_PA0_RES,
      PA1_RES_o => IX2_PA1_RES,
      OPA0_V_o => IX2_OPA0_V,
      OPA1_V_o => IX2_OPA1_V,
      OPA0_o => IX2_OPA0,
      OPA1_o => IX2_OPA1,
      OPB0_V_o => IX2_OPB0_V,
      OPB1_V_o => IX2_OPB1_V,
      OPB0_o => IX2_OPB0,
      OPB1_o => IX2_OPB1,
      DRD0_o => IX2_DRD0,
      DRD1_o => IX2_DRD1
    );
 
  -- Exception processing: data address errors are
  -- detected by memory sub-system and reported
  -- using DADR*_ERR_i.
 
  IX2_V_BJX(0) <= IX1_V_q(0);
  IX2_V_BJX(1) <= IX1_V_q(1) and not(IX1_BJX0_q);
 
  U_EXCPLX2 : RV01_EXCPLOG_IX2
    generic map(
      NW => NW
    )
    port map(
      V_i => IX2_V_BJX, --IX1_V_q,
      INSTR_i => IX1_INSTR_q,
      PC0_i => IX1_PC0_q,
      PC1_i => IX1_PC1_q,
      DADR0_i => IX1_DADR0_q,
      DADR1_i => IX1_DADR1_q,
      HALT_i => IX2_HALT,
      RSM_i => WB_RSM,
      DRSM_i => WB_DRSM,
      EXT_INT_i => EXT_INT_i,
      SFT_INT_i => WB_SFT_INT,
      TMR_INT_i => WB_TMR_INT,
      ETVA_i => WB_ETVA,
      MEPC_i => WB_MEPC,
      DADR0_ERR_i => DADR0_ERR_i,
      DADR1_ERR_i => DADR1_ERR_i,
      CSR_ILLG_i => IX2_ILLG,
      IE_i => WB_IE,
      STEP_i => IX2_STEP,
 
      V_o => IX2_V,
      EV_o => IX2_EV,
      INSTR_o => IX2_INSTR,
      EERTA_o => IX2_EERTA
    );
 
  GDM0_1 : if (DM_PRESENT = '1') generate
 
  -- Debug logic
 
  UDBGLOGX2 : RV01_DBGLOG_IX2
    generic map(
      NW => NW
    )
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      V_i => IX1_V_q,
      IMNMC0_i => IX1_INSTR_q(0).IMNMC,
      RFTCH0_i => IX1_INSTR_q(0).RFTCH,
      STEP_i => WB_DSTEP,
      HOBRK_i => WB_DHOBRK,
      HRQ_i => WB_DHLTRQ,
 
      STEP_o => IX2_STEP,
      HALT_o => IX2_HALT,
      HIS_o => IX2_HIS
    );
 
  end generate;
 
  GDM0_0 : if (DM_PRESENT = '0') generate
 
  -- Halting logic
 
  UHLTLOGX2:  RV01_HLTLOG_IX2
    generic map(
      NW => NW
    )
    port map(
      V_i => IX1_V_q,
      IMNMC0_i => IX1_INSTR_q(0).IMNMC,
      PC0_i => IX1_PC0_q,
      PC1_i => IX1_PC1_q,
      HOBRK_i => WB_HLTOBRK,
      HOADR_i => WB_HLTOADR,
      HADR_i => WB_HLTADR,
      HRQ_i => WB_HLTURQ,
 
      HALT_o => IX2_HALT,
      HIS_o => IX2_HIS
    );
 
  IX2_STEP <= '0';
 
  end generate;
 
  -- Pipeline Registers
 
  process(CLK_i)
  begin
    if(CLK_i = '1' and CLK_i'event) then
      if(IRST = '1') then
        IX2_V_q <= "00";
        IX2_EV_q <= "00";
      else
        if(IX3_STL(0) = '0') then
          IX2_V_q(0) <= IX2_V(0) and not(IX3_CLRP);
          IX2_EV_q(0) <= IX2_EV(0) and not(IX3_CLRP);
        end if;
        if(IX3_STL(1) = '0') then
          IX2_V_q(1) <= IX2_V(1) and not(IX3_CLRP);
          IX2_EV_q(1) <= IX2_EV(1) and not(IX3_CLRP);
        end if;
      end if;
      if(IRST = '1') then
        IX2_DWE_q <= "00";
        IX2_HALT_q <= "00";
      elsif(IX3_STL(0) = '0') then
        IX2_INSTR_q(0) <= IX2_INSTR(0);
        IX2_PC0_q <= IX1_PC0_q;
        IX2_FWDE_q(0) <= IX1_FWDE_q(0);
        IX2_FWDX_q(0) <= IX2_FWDX(0);
        IX2_DRD0_q <= IX2_DRD0;
        IX2_DADR0_q <= IX1_DADR0_q;
        IX2_CSRU_RES_q <= IX2_CSRU_RES;
        IX2_DWE_q(0) <= IX1_DWE_q(0);
        IX2_HALT_q(0) <= IX2_HALT(0) and not(IX3_CLRP);
        IX2_PASEL1_q <= IX1_PASEL1_q;
      end if;
      if(IX3_STL(1) = '0') then
        IX2_INSTR_q(1) <= IX2_INSTR(1);
        IX2_PC1_q <= IX1_PC1_q;
        IX2_FWDE_q(1) <= IX1_FWDE_q(1);
        IX2_FWDX_q(1) <= IX2_FWDX(1);
        IX2_DRD1_q <= IX2_DRD1;
        IX2_DADR1_q <= IX1_DADR1_q;
        IX2_DWE_q(1) <= IX1_DWE_q(1);
        IX2_HALT_q(1) <= IX2_HALT(1) and not(IX3_CLRP);
        IX2_PASEL0_q <= IX1_PASEL0_q;
      end if;
      if(IX3_STL = "00") then
        IX2_EERTA_q <= IX2_EERTA;
      end if;
      IX2_HIS_q <= IX2_HIS;
      IX2_PC0P4_q <= IX1_PC0P4_q;
      IX2_PC1P4_q <= IX1_PC1P4_q;
    end if;
  end process;
 
  ----------------------------------------------------
  -- IX3 Stage
  ----------------------------------------------------
 
  -- Stage IX3 is used to perform data alignment operations
  -- for LB* and LH* instructions and for exception 
  -- processing.
 
  GDX3_1 : if(DELAYED_EXECUTION_ENABLED = '1') generate
 
  U_PA0ALU_X3: RV01_PIPE_A_ALU
    port map(
      SEL_i => IX2_PASEL0_q,
      SU_i => IX2_INSTR_q(0).SU,
      OP_i => IX2_INSTR_q(0).ALU_OP,
      OPA_i => IX2_OPA0_q,
      OPB_i => IX2_OPB0_q,
 
      RES_o => IX3_PA0_ALU_RES
    );
 
  GPX_X3_0_1 : if(PARALLEL_EXECUTION_ENABLED = '1') generate
 
  U_PA1ALU_X3: RV01_PIPE_A_ALU
    port map(
      SEL_i => IX2_PASEL1_q,
      SU_i => IX2_INSTR_q(1).SU,
      OP_i => IX2_INSTR_q(1).ALU_OP,
      OPA_i => IX2_OPA1_q,
      OPB_i => IX2_OPB1_q,
 
      RES_o => IX3_PA1_ALU_RES
    );
 
  end generate; -- GPX_X3_0_1
 
  end generate;
 
  -- Result mux
 
  U_RMX3: RV01_RESMUX_IX3
    generic map(
      PXE => PARALLEL_EXECUTION_ENABLED,
      DXE => DELAYED_EXECUTION_ENABLED,
      NW => NW
    )
    port map(
      DRD0_i => IX2_DRD0_q,
      DRD1_i => IX2_DRD1_q,
      PA0_ALU_RES_i => IX3_PA0_ALU_RES,
      PA1_ALU_RES_i => IX3_PA1_ALU_RES,
      LDAT0_i => IX3_LDAT0,
      LDAT1_i => IX3_LDAT1,
      LDAT_V_i(0) => IX3_LDAT0_V,
      LDAT_V_i(1) => IX3_LDAT1_V,
      PASEL0_i => IX2_PASEL0_q,
      PASEL1_i => IX2_PASEL1_q,
      FWDE_i => IX2_FWDE_q,
      RES_SRC0_i => IX2_INSTR_q(0).RES_SRC,
      CSRU_RES_i => IX2_CSRU_RES_q,
 
      DRD0_o => IX3_DRD0,
      DRD1_o => IX3_DRD1
    );
 
  -- Exception logic
 
  U_EXCPLX3 : RV01_EXCPLOG_IX3
    generic map(
      NW => NW
    )
    port map(
      V_i  => IX2_V_q,
      EV_i  => IX2_EV_q,
      INSTR_i  => IX2_INSTR_q,
      PC0_i => IX2_PC0_q,
      PC1_i => IX2_PC1_q,
      DADR0_i => IX2_DADR0_q,
      DADR1_i => IX2_DADR1_q,
      HALT_i => IX3_HALT,
      HIS_i => IX2_HIS_q,
 
      EXCP_o => IX3_EXCP,
      ERET_o => IX3_ERET,
      RFTCH_o => IX3_RFTCH,
      KPRD_o => IX3_KPRD,
      CLRP_o => IX3_CLRP_NOHLT,
      CLRB_o => IX3_CLRB,
      CLRD_o => IX3_CLRD_NOHLT,
      EPC_o => IX3_EPC,
      ECAUSE_o => IX3_ECAUSE,
      EDADR_o => IX3_EDADR
    );
 
  -- Miscellaneous logic
 
  U_MLOGX3 : RV01_MISCLOG_IX3
    generic map(
      PXE => PARALLEL_EXECUTION_ENABLED,
      NW => NW
    )
    port map(
      IX1_V0_i => ID_V_q(0),
      IX1_WCSR0_i => ID_INSTR_q(0).WCSR,
      V_i => IX2_V_q ,
      DWE_i => IX2_DWE_q,
      KPRD_i => IX3_KPRD,
      WRD0_i => IX2_INSTR_q(0).WRD,
      WRD1_i => IX2_INSTR_q(1).WRD,
      HALT_i => IX2_HALT_q,
      CLRP_i => IX3_CLRP_NOHLT,
      CLRD_i => IX3_CLRD_NOHLT,
      HIS_i => IX2_HIS_q,
      PC0_i => IX2_PC0_q,
      PC1_i => IX2_PC1_q,
 
      CP_WE_o => IX1_CP_WE,
      SBRE_o => IX3_SBRE,
      STL_o => IX3_STL,
      WE_o => IX3_WE,
      HALT_o => IX3_HALT,
      CLRP_o => IX3_CLRP,
      CLRD_o => IX3_CLRD,
      HPC_o => IX3_HPC
    );
 
  ----------------------------------------------------
  -- WB Stage
  ----------------------------------------------------
 
  -- Register File
 
  U_REGF : RV01_REGFILE_32X32_2W
    port map(
      CLK_i => CLK_i,
      RA0_i => IF2_DEC_INSTR_q(0).RS1,
      RA1_i => IF2_DEC_INSTR_q(0).RS2,
      RA2_i => IF2_DEC_INSTR_q(1).RS1,
      RA3_i => IF2_DEC_INSTR_q(1).RS2,
      WA0_i => IX2_INSTR_q(0).RD,
      WA1_i => IX2_INSTR_q(1).RD,
      WE0_i => IX3_WE(0),
      WE1_i => IX3_WE(1),
      D0_i => to_std_logic_vector(IX3_DRD0),
      D1_i => to_std_logic_vector(IX3_DRD1),
 
      Q0_o => WB_RDA0,
      Q1_o => WB_RDB0,
      Q2_o => WB_RDA1,
      Q3_o => WB_RDB1
    );
 
  -- CSR's management Unit
 
  U_CSRU : RV01_CSRU
    generic map(
      PXE => PARALLEL_EXECUTION_ENABLED,
      FPU_PRESENT => FPU_PRESENT,
      NW => NW
    )
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      IX1_V0_i => ID_V_q(0),
      CS_OP_i => ID_INSTR_q(0).CS_OP,
      RS1_i => ID_INSTR_q(0).RS1,
      ADR_i => ID_INSTR_q(0).IMM(12-1 downto 0),
      WE_i => IX1_CP_WE,
      CSRD_i => ID_OPA0_q,
      EXCP_i => IX3_EXCP,
      EPC_i => IX3_EPC,
      ECAUSE_i => IX3_ECAUSE,
      EBADR_i => IX3_EDADR,
      ERET_i => IX3_ERET,
      IX3_V_i => IX2_V_q,
      NOPR_i => IX1_NOPR,
      HALT_i => IX2_HALT(0),
      STOPCYCLE_i => WB_STOPCYCLE,
      STOPTIME_i => WB_STOPTIME,
      MFROMHOST_WE_i => MFROMHOST_WE_i,
      MFROMHOST_i => MFROMHOST_i,
      DMODE_i => WB_DMODE,
      DIE_i => WB_DIE,
      CPRE_i => CP_RE_i,
      CPWE_i => CP_WE_i,
      CPADR_i => CP_ADR_i,
      CPD_i => CP_D_i,
 
      PXE_o => WB_PXE,
      MSTATUS_o => WB_MSTATUS,
      MEPC_o => WB_MEPC,
      MBASE_o => WB_MBASE,
      MBOUND_o => WB_MBOUND,
      MIBASE_o => WB_MIBASE,
      MIBOUND_o => WB_MIBOUND,
      MDBASE_o => WB_MDBASE,
      MDBOUND_o => WB_MDBOUND,
      ETVA_o => WB_ETVA,
      MTOHOST_o => MTOHOST_o,
      MTOHOST_OE_o => MTOHOST_OE_o,
      ILLG_o => WB_ILLG,
      SFT_INT_o => WB_SFT_INT,
      TMR_INT_o => WB_TMR_INT,
      FFLAGS_o => WB_FFLAGS,
      FRM_o => WB_FRM,
      IE_o => WB_IE,
      CSRQ_o => WB_CSRQ,
      -- Control port
      CPQ_o => WB_CPQ
    );
 
  WB_MMODE <= '1' when (
    WB_MSTATUS(2 downto 1) = "11"
  ) else '0';
 
  -- Debug module
 
  GDM1_1 : if(DM_PRESENT = '1') generate
 
  -- Debug module
 
  U_DBGU : RV01_DBGU
    generic map(
      NW => 2
    )
    port map(
      CLK_i => CLK_i,
      RST_i => RST_i, -- pay attention!
      HPC_i => IX3_HPC, --IX3_DHPC,
      MMODE_i => WB_MMODE,
      NOPR_i => IX1_NOPR,
      HALT_i => IX3_HALT, --IX3_DHALT,
      CPRE_i => CP_RE_i,
      CPWE_i => CP_WE_i,
      CPADR_i => CP_ADR_i,
      CPD_i => CP_D_i,
 
      RST_o => WB_DRST,
      HLTRQ_o => WB_DHLTRQ,
      RSM_o => WB_DRSM,
      DPC_o => WB_DPC,
      DMODE_o => WB_DMODE,
      DIE_o => WB_DIE,
      HALTD_o => WB_HALTD,
      STOPTIME_o => WB_STOPTIME,
      STOPCYCLE_o => WB_STOPCYCLE,
      SI_o => WB_DSI,
      HOBRK_o => WB_DHOBRK,
      STEP_o => WB_DSTEP,
      FRCSI_o => WB_DFRCSI,
      CPQ_o => WB_DCPQ
    );
 
  -- Halt module (disabled)
 
  WB_HALTD <= '0';
  WB_STRT <= '0';
  WB_STRTPC <= (others => '0');
  WB_RSM <= '0';
  WB_HLTURQ <= '0';
  WB_HLTOBRK <= '0';
  WB_HLTOADR<= (others => '0');
  WB_HLTADR <= (others => '0');
  WB_HCSRQ <= (others => '0');
  WB_HCSR <= '0';
  WB_HILLG <= '0';
  WB_HCP <= '0';
  WB_HCPQ <= (others => '0');
 
  end generate;
 
  GDM1_0 : if(DM_PRESENT = '0') generate
 
  -- Debug module  (disabled)
 
  WB_DRST <= '0';
  WB_DHLTRQ <= '0';
  WB_DRSM <= '0';
  WB_DPC <= (others => '0');
  WB_DMODE <= '0';
  WB_DIE <= '1';
  WB_STOPTIME <= '0';
  WB_STOPCYCLE <= '0';
  WB_DSI <= (others => '0');
  WB_DHOBRK <= '0';
  WB_DSTEP <= '0';
  WB_DFRCSI <= '0';
  WB_DCPQ <= (others => '0');
 
  -- Halt module
 
  U_HLTU : RV01_HLTU
    generic map(
      PXE => PARALLEL_EXECUTION_ENABLED,
      NW => NW
    )
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      IX1_V_i => ID_V_q,
      IX2_V_i => IX1_V_q,
      NOPR_i => IX1_NOPR,
      MMODE_i => WB_MMODE,
      HALT_i => IX3_HALT,
      HPC_i => IX3_HPC,
      CS_OP_i => ID_INSTR_q(0).CS_OP,
      RS1_i => ID_INSTR_q(0).RS1,
      ADR_i => ID_INSTR_q(0).IMM(12-1 downto 0),
      WE_i => IX1_CP_WE,
      CSRD_i => ID_OPA0_q,
      CPRE_i => CP_RE_i,
      CPWE_i => CP_WE_i,
      CPADR_i => CP_ADR_i,
      CPD_i => CP_D_i,
 
      HMODE_o => WB_HALTD,
      STRT_o => WB_STRT,
      STRTPC_o => WB_STRTPC,
      RSM_o => WB_RSM,
      HLTURQ_o => WB_HLTURQ,
      HLTOBRK_o => WB_HLTOBRK,
      HLTOADR_o => WB_HLTOADR,
      HLTADR_o => WB_HLTADR,
      CSRQ_o => WB_HCSRQ,
      HCSR_o => WB_HCSR,
      ILLG_o => WB_HILLG,
      HCP_o => WB_HCP,
      CPQ_o => WB_HCPQ
    );
 
  end generate;
 
  -- Mux CSRU and HLTU/DBGU commmon output signals
 
  U_CDCOMUX : RV01_CDCOMUX
    generic map(
      DMP => DM_PRESENT
    )
    port map(
      CLK_i => CLK_i,
      HCSR_i => WB_HCSR,
      HCSRQ_i => WB_HCSRQ,
      CSRQ_i => WB_CSRQ,
      HILLG_i => WB_HILLG,
      ILLG_i => WB_ILLG,
      CP_ADR_MSB_i => CP_ADR_i(16),
      HCP_i => WB_HCP,
      HCPQ_i => WB_HCPQ,
      CPQ_i => WB_CPQ,
      DCPQ_i => WB_DCPQ,
      STRT_i => WB_STRT,
      DRSM_i => WB_DRSM,
      DPC_i => WB_DPC,
      STRTPC_i => WB_STRTPC,
 
      ILLG_o => IX2_ILLG,
      CSRU_RES_o => IX2_CSRU_RES,
      CP_Q_o => CP_Q_o,
      STRT_o => WB_XSTRT,
      STRTPC_o => WB_XSTRTPC
    );
 
  ----------------------------------------------------
  -- Write-Back Checker
  ----------------------------------------------------
 
  -- synthesis translate_off
 
  G_WB : if(SIMULATION_ONLY = '1') generate
 
  WB_CHK_ENB <= CHK_ENB_i and not(WB_DMODE);
 
  U_WBCHK : RV01_WB_CHECKER
    generic map(
      WB_FILENAME => WB_FILENAME
    )
    port map(
      CLK_i => CLK_i,
      ENB_i => WB_CHK_ENB,
      WE0_i => IX3_WE(0),
      WE1_i => IX3_WE(1),
      IX_INSTR0_i => IX2_INSTR_q(0),
      IX_INSTR1_i => IX2_INSTR_q(1),
      IX_DRD0_i => IX3_DRD0,
      IX_DRD1_i => IX3_DRD1
    );
 
  end generate;
 
  -- synthesis translate_on
 
  ----------------------------------------------------
  -- Statistics
  ----------------------------------------------------
 
  -- synthesis translate_off
 
  G_STAT : if(SIMULATION_ONLY = '1') generate
 
  U_STAT : RV01_STATS
    port map(
      CLK_i => CLK_i,
      RST_i => IRST,
      ID_V_i => IF2_V_q,
      ID_PS_i(0) => ID_PS(0),
      ID_PS_i(1) => ID_PS(1),
      ID_PXE1_i => ID_PXE1,
      IX2_V_i => IX2_V_q,
      STRT_i => STRT,
      HALT_i => IX3_HALT
    );
 
  end generate;
 
  -- synthesis translate_on
 
end ARC;
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[/] [rv01_riscv_core/] [trunk/] [VHDL/] [RV01_cpu_2w_p6.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	madsilicon	`-----------------------------------------------------------------`
2			`-- --`
3			`-----------------------------------------------------------------`
4			`-- --`
5			`-- Copyright (C) 2017 Stefano Tonello --`
6			`-- --`
7			`-- This source file may be used and distributed without --`
8			`-- restriction provided that this copyright statement is not --`
9			`-- removed from the file and that any derivative work contains --`
10			`-- the original copyright notice and the associated disclaimer.--`
11			`-- --`
12			-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
13			`-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --`
14			`-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --`
15			`-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --`
16			`-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --`
17			`-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --`
18			`-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --`
19			`-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --`
20			`-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --`
21			`-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --`
22			`-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --`
23			`-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --`
24			`-- POSSIBILITY OF SUCH DAMAGE. --`
25			`-- --`
26			`-----------------------------------------------------------------`
27
28			`---------------------------------------------------------------`
29			`-- RV01 CPU module`
30			`---------------------------------------------------------------`
31
32			`library IEEE;`
33			`use IEEE.std_logic_1164.all;`
34			`use IEEE.numeric_std.all;`
35			`use STD.textio.all;`
36
37			`library work;`
38			`use work.RV01_CONSTS_PKG.all;`
39			`use work.RV01_TYPES_PKG.all;`
40			`use WORK.RV01_FUNCS_PKG.all;`