Subversion Repositories rv01_riscv_core

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-- Copyright (C) 2016 Stefano Tonello                          --

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---------------------------------------------------------------

-- RV01 debug logic (IX2 stage)

---------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

library work;

use work.RV01_CONSTS_PKG.all;

use work.RV01_TYPES_PKG.all;

use work.RV01_IDEC_PKG.all;

entity RV01_DBGLOG_IX2 is

  generic(

    NW : natural := 2

  );

  port(

    CLK_i : in std_logic;

    RST_i : in std_logic;

    V_i : in std_logic_vector(NW-1 downto 0);

    IMNMC0_i : in INST_MNEMONIC_T;

    RFTCH0_i : in std_logic;

    STEP_i : in std_logic;

    HOBRK_i : in std_logic;

    HRQ_i : in std_logic;

    STEP_o : out std_logic;

    HALT_o : out std_logic_vector(NW-1 downto 0);

    HIS_o : out std_logic

  );

end RV01_DBGLOG_IX2;

architecture ARC of RV01_DBGLOG_IX2 is

  signal BRK0,STEP_q : std_logic;

begin

  -- sbreak instruction flag

  BRK0 <= '1' when (IMNMC0_i = IM_SBREAK) else '0';

  -- step flag register  

  process(CLK_i)

  begin

    if(CLK_i = '1' and CLK_i'event) then

      if(RST_i = '1') then

        STEP_q <= '0';

      elsif(STEP_i = '1') then

        STEP_q <= '1';

      elsif(V_i(0) = '1' and RFTCH0_i = '0') then -- or V_i(1) = '1') then

        STEP_q <= '0';

      end if;

    end if;

  end process;

  STEP_o <= STEP_q;

  -- Step flag is set by debug module (asserting STEP_i)

  -- when single-step execution is enabled and reset when

  -- the first valid instruction reaches IX3 stage.

  -- This flag allows first instruction to reach IX3 to 

  -- be executed normally, while second one triggers

  -- a halting condition.

  -- halt flags

  -- Halt flag is set for slot #0 instruction when

  -- instruction is valid and step flag is cleared, if:

  -- 1) there's a pending halt request, OR

  -- 2) instruction is a sbreak and halt-on-break is enabled.

  HALT_o(0) <= (V_i(0) and not(STEP_q)) when (

    (HRQ_i = '1')  or

    (HOBRK_i = '1' and BRK0 = '1')

  ) else '0';

  -- Halt flag is set for slot #0 instruction when

  -- instruction is valid and step flag is cleared or

  -- instruction #0 is valid, if there's a pending 

  --halt request.

  HALT_o(1) <= (V_i(1) and (not(STEP_q) or V_i(1))) and

    HRQ_i;

  -- halt instruction selector

  HIS_o <= not(V_i(0)) when (STEP_q = '0') else '1';

end ARC;