Subversion Repositories rv01_riscv_core

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-- Copyright (C) 2017 Stefano Tonello                          --

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---------------------------------------------------------------

-- RV01 Data/Instruction Memory Selection Logic

---------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

library WORK;

use WORK.RV01_CONSTS_PKG.all;

use WORK.RV01_TYPES_PKG.all;

--use WORK.RV01_CFG_PKG.all;

entity RV01_DIMSLOG is

  generic(

    IMEM_LOWM : std_logic := '1';

    IMEM_SIZE : natural := 1024*32;

    DMEM_SIZE : natural := 1024*16

  );

  port(

    IX1_OPA0_i : in SDWORD_T;

    IX1_OPA1_i : in SDWORD_T;

    IX1_IMM0_i : in SDWORD_T;

    IX1_IMM1_i : in SDWORD_T;

    IX1_DADR0_i : in ADR_T;

    IX1_DADR1_i : in ADR_T;

    IX3_DADR0_i : in ADR_T;

    IX1_DIMS_o : out std_logic_vector(2-1 downto 0);

    IX3_DIMS_o : out std_logic

  );

end RV01_DIMSLOG;

architecture ARC of RV01_DIMSLOG is

  component RV01_COMP32 is

    port(

      A_i : in std_logic_vector(3-1 downto 0);

      S_o : out std_logic;

      C_o : out std_logic

    );

  end component;

  component RV01_ADDER_F is

    generic(

      LEN1 : integer := 16;

      LEN2 : integer := 16

    );

    port(

      OPA_i : in signed(LEN1+LEN2-1 downto 0);

      OPB_i : in signed(LEN1+LEN2-1 downto 0);

      CI_i : in std_logic;

      SUM_o : out signed(LEN1+LEN2-1 downto 0)

    );

  end component;

  subtype B3_T is std_logic_vector(3-1 downto 0);

  type D2A_T is array(SDLEN-1 downto 0) of B3_T;

  signal A0,A1 : D2A_T;

  signal ZERO : std_logic := '0';

  signal MEMSIZE,TMP0,TMP1 : SDWORD_T;

  signal S0,C0,S1,C1 : signed(SDLEN downto 0);

begin

  ---------------------------------------------------

  -- Data/Instructions memory selection flags logic

  -- (select type of memory referenced by data physical

  -- addresses).

  --

  -- Three flags are generated: two for instructions in

  -- stage IX1 (they are needed to process loads) and 

  -- one for slot #0 instruction in IX3 stage (this is

  -- needed to process stores from the store buffer).

  -- In order to speed-up IX1 selection flags value 

  -- generation, instead of subtracting IMEM_SIZE (or

  -- DMEM_SIZE) from immediate address (something 

  -- requiring two cascaded adders), IMEM_SIZE (or

  -- DMEM_SIZE), IX1_OPA*_i and IX1_IMM*_i are summed

  -- up using a 3:2 compressing stage followed by a

  -- regular adder.

  ---------------------------------------------------

  G1: if IMEM_LOWM = '1' generate

  -- Instruction memory is located in lower portion

  -- of address space

  MEMSIZE <= to_signed(-IMEM_SIZE*4,SDLEN);

  -- This is the original code...

  --IX1_DIMS_o(0) <= '1' when IX1_DADR0_i/4 >= IMEM_SIZE else '0';

  -- 3:2 compressing stage

  GC0 : for k in 0 to SDLEN-1 generate

  A0(k)(0) <= IX1_OPA0_i(k);

  A0(k)(1) <= IX1_IMM0_i(k);

  A0(k)(2) <= MEMSIZE(k);

  U_COMP : RV01_COMP32

    port map(

      A_i => A0(k),

      S_o => S0(k),

      C_o => C0(k+1)

    );

  end generate;

  S0(SDLEN) <= '0';

  C0(0) <= '0';

  -- regular adder 

  TMP0 <= S0(SDLEN-1 downto 0) + C0(SDLEN-1 downto 0);

  IX1_DIMS_o(0) <= not(TMP0(SDLEN-1));

  -- This is the original code...

  --IX1_DIMS_o(1) <= '1' when IX1_DADR1_i/4 >= IMEM_SIZE else '0';

  -- 3:2 compressing stage

  GC1 : for k in 0 to SDLEN-1 generate

  A1(k)(0) <= IX1_OPA1_i(k);

  A1(k)(1) <= IX1_IMM1_i(k);

  A1(k)(2) <= MEMSIZE(k);

  U_COMP : RV01_COMP32

    port map(

      A_i => A1(k),

      S_o => S1(k),

      C_o => C1(k+1)

    );

  end generate;

  S1(SDLEN) <= '0';

  C1(0) <= '0';

  -- regular adder 

  TMP1 <= S1(SDLEN-1 downto 0) + C1(SDLEN-1 downto 0);

  IX1_DIMS_o(1) <= not(TMP1(SDLEN-1));

  IX3_DIMS_o <= '1' when IX3_DADR0_i/4 >= IMEM_SIZE else '0';

  end generate;

  ---------------------------------------------------

  G0: if IMEM_LOWM = '0' generate

  -- Instruction memory is located in upper portion

  -- of address space

  MEMSIZE <= to_signed(-DMEM_SIZE*4,SDLEN);

  -- This is the original code...

  --IX1_DIMS_o(0) <= '1' when IX1_DADR0_i/4 < DMEM_SIZE else '0';

  -- 3:2 compressing stage

  GC0 : for k in 0 to SDLEN-1 generate

  A0(k)(0) <= IX1_OPA0_i(k);

  A0(k)(1) <= IX1_IMM0_i(k);

  A0(k)(2) <= MEMSIZE(k);

  U_COMP : RV01_COMP32

    port map(

      A_i => A0(k),

      S_o => S0(k),

      C_o => C0(k+1)

    );

  end generate;

  S0(SDLEN) <= '0';

  C0(0) <= '0';

  -- regular adder 

  TMP0 <= S0(SDLEN-1 downto 0) + C0(SDLEN-1 downto 0);

  IX1_DIMS_o(0) <= TMP0(SDLEN-1);

  -- This is the original code...

  --IX1_DIMS_o(1) <= '1' when IX1_DADR1_i/4 < DMEM_SIZE else '0';

  -- 3:2 compressing stage

  GC1 : for k in 0 to SDLEN-1 generate

  A1(k)(0) <= IX1_OPA1_i(k);

  A1(k)(1) <= IX1_IMM1_i(k);

  A1(k)(2) <= MEMSIZE(k);

  U_COMP : RV01_COMP32

    port map(

      A_i => A1(k),

      S_o => S1(k),

      C_o => C1(k+1)

    );

  end generate;

  S1(SDLEN) <= '0';

  C1(0) <= '0';

  -- regular adder 

  TMP1 <= S1(SDLEN-1 downto 0) + C1(SDLEN-1 downto 0);

  IX1_DIMS_o(1) <= TMP1(SDLEN-1);

  IX3_DIMS_o <= '1' when IX3_DADR0_i/4 < DMEM_SIZE else '0';

  end generate;

  ---------------------------------------------------

end ARC;