Subversion Repositories rv01_riscv_core

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-- Copyright (C) 2015 Stefano Tonello                          --

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-- RV01 division support logic

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library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

library WORK;

use WORK.RV01_CONSTS_PKG.all;

use WORK.RV01_TYPES_PKG.all;

use WORK.RV01_ARITH_PKG.all;

use work.RV01_IDEC_PKG.all;

use work.RV01_OP_PKG.all;

entity RV01_DIVLOG is

  port(

    V_i : in std_logic;

    INSTR_i : in DEC_INSTR_T;

    DIV_V_i : in std_logic;

    DIV_STRT_o : out std_logic;

    DIV_QS_o : out std_logic;

    DIV_CLRV_o : out std_logic

  );

end RV01_DIVLOG;

architecture ARC of RV01_DIVLOG is

begin

  -- Division start flag: a new division can start

  -- if current instruction is valid, is of

  -- division/reminder type and there's no result

  -- ready (if there's a result ready, instruction

  -- has been already re-fetched and therefore there

  -- is no need to re-execute it).

  DIV_STRT_o <= (V_i and not(DIV_V_i)) when (

    INSTR_i.ALU_OP = ALU_DIV or

    INSTR_i.ALU_OP = ALU_REM

  ) else '0';

  -- Division Quotient/Reminder result selection flag

  DIV_QS_o <= '1' when (

    INSTR_i.ALU_OP = ALU_DIV

  ) else '0';

  -- Clear division result valid flag: if current

  -- instruction is valid, is of division/reminder

  -- type and there's a result ready, result valid

  -- flag can be cleared.  

  DIV_CLRV_o <= (V_i and DIV_V_i) when (

    INSTR_i.ALU_OP = ALU_DIV or

    INSTR_i.ALU_OP = ALU_REM

  ) else '0';

end ARC;