1 |
2 |
madsilicon |
-----------------------------------------------------------------
|
2 |
|
|
-- --
|
3 |
|
|
-----------------------------------------------------------------
|
4 |
|
|
-- --
|
5 |
|
|
-- Copyright (C) 2015 Stefano Tonello --
|
6 |
|
|
-- --
|
7 |
|
|
-- This source file may be used and distributed without --
|
8 |
|
|
-- restriction provided that this copyright statement is not --
|
9 |
|
|
-- removed from the file and that any derivative work contains --
|
10 |
|
|
-- the original copyright notice and the associated disclaimer.--
|
11 |
|
|
-- --
|
12 |
|
|
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
|
13 |
|
|
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
|
14 |
|
|
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
15 |
|
|
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
|
16 |
|
|
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
|
17 |
|
|
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
|
18 |
|
|
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
|
19 |
|
|
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
|
20 |
|
|
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
|
21 |
|
|
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
|
22 |
|
|
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
|
23 |
|
|
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
|
24 |
|
|
-- POSSIBILITY OF SUCH DAMAGE. --
|
25 |
|
|
-- --
|
26 |
|
|
-----------------------------------------------------------------
|
27 |
|
|
|
28 |
|
|
---------------------------------------------------------------
|
29 |
|
|
-- RV01 Exception processing logic (IX1 stage)
|
30 |
|
|
---------------------------------------------------------------
|
31 |
|
|
|
32 |
|
|
library IEEE;
|
33 |
|
|
use IEEE.std_logic_1164.all;
|
34 |
|
|
use IEEE.numeric_std.all;
|
35 |
|
|
|
36 |
|
|
library work;
|
37 |
|
|
use work.RV01_CONSTS_PKG.all;
|
38 |
|
|
use work.RV01_TYPES_PKG.all;
|
39 |
|
|
use work.RV01_OP_PKG.all;
|
40 |
|
|
use work.RV01_IDEC_PKG.all;
|
41 |
|
|
use work.RV01_CSR_PKG.all;
|
42 |
|
|
--use work.RV01_CFG_B_PKG.all;
|
43 |
|
|
|
44 |
|
|
entity RV01_EXCPLOG_IX1 is
|
45 |
|
|
generic(
|
46 |
|
|
NW : natural := 2
|
47 |
|
|
);
|
48 |
|
|
port(
|
49 |
|
|
INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0); -- slot #0/1 inst.
|
50 |
|
|
MALGN_i : in std_logic_vector(NW-1 downto 0); -- slot #0,1 misalign flag
|
51 |
|
|
S2LAC_i : in std_logic_vector(NW-1 downto 0); -- slot #0,1 store-2-load conflict flag
|
52 |
|
|
B2BAC_i : in std_logic; -- branch-2-branch conflict flag
|
53 |
|
|
DIV_V_i : in std_logic; -- division valid result flag
|
54 |
|
|
IDADR_CFLT_i : in std_logic; -- inst. mem. concurrent data access flag
|
55 |
|
|
|
56 |
|
|
PSLP_o : out std_logic;
|
57 |
|
|
INSTR_o : out DEC_INSTR_VEC_T(NW-1 downto 0) -- slot #0/1 inst.
|
58 |
|
|
);
|
59 |
|
|
end RV01_EXCPLOG_IX1;
|
60 |
|
|
|
61 |
|
|
architecture ARC of RV01_EXCPLOG_IX1 is
|
62 |
|
|
|
63 |
|
|
signal INSTR : DEC_INSTR_VEC_T(NW-1 downto 0);
|
64 |
|
|
signal PSLP : std_logic;
|
65 |
|
|
|
66 |
|
|
function is_store(OP : LS_OP_T) return std_logic is
|
67 |
|
|
variable S : std_logic;
|
68 |
|
|
begin
|
69 |
|
|
if(OP = LS_SB or OP = LS_SH or OP = LS_SW) then
|
70 |
|
|
S := '1';
|
71 |
|
|
else
|
72 |
|
|
S := '0';
|
73 |
|
|
end if;
|
74 |
|
|
return(S);
|
75 |
|
|
end function;
|
76 |
|
|
|
77 |
|
|
function is_load(OP : LS_OP_T) return std_logic is
|
78 |
|
|
variable S : std_logic;
|
79 |
|
|
begin
|
80 |
|
|
if(OP = LS_LB or OP = LS_LH or OP = LS_LW) then
|
81 |
|
|
S := '1';
|
82 |
|
|
else
|
83 |
|
|
S := '0';
|
84 |
|
|
end if;
|
85 |
|
|
return(S);
|
86 |
|
|
end function;
|
87 |
|
|
|
88 |
|
|
begin
|
89 |
|
|
|
90 |
|
|
------------------------------------
|
91 |
|
|
-- Notes
|
92 |
|
|
------------------------------------
|
93 |
|
|
|
94 |
|
|
-- This module handles exceptions and re-fetching conditions
|
95 |
|
|
-- generated in stage IX1.
|
96 |
|
|
-- Exceptions: misaligned L/S address.
|
97 |
|
|
-- Re-fetching conditions:
|
98 |
|
|
-- 1) Store-to-load address conflict.
|
99 |
|
|
-- 2) Branch address conflict (even-even or odd-odd).
|
100 |
|
|
-- 3) Division.
|
101 |
|
|
-- 4) Concurrent L/S access to inst. memory.
|
102 |
|
|
|
103 |
|
|
-- Exception may affect both instructions, division
|
104 |
|
|
-- re-fetching can affect only slot #0 instruction, and
|
105 |
|
|
-- the other re-fetching condition can affect only slot #1
|
106 |
|
|
-- instruction.
|
107 |
|
|
|
108 |
|
|
process(INSTR_i,MALGN_i,S2LAC_i,B2BAC_i,DIV_V_i,IDADR_CFLT_i)
|
109 |
|
|
variable DIV_RFTCH,LOAD_RFTCH : std_logic;
|
110 |
|
|
begin
|
111 |
|
|
|
112 |
|
|
INSTR(0) <= INSTR_i(0);
|
113 |
|
|
if(INSTR_i(0).IMNMC = IM_SCALL and INSTR_i(0).EXCP = '0') then
|
114 |
|
|
INSTR(0).EXCP <= '1';
|
115 |
|
|
INSTR(0).ECAUSE <= UMCALL;
|
116 |
|
|
elsif(INSTR_i(0).IMNMC = IM_SBREAK and INSTR_i(0).EXCP = '0') then
|
117 |
|
|
INSTR(0).EXCP <= '1';
|
118 |
|
|
INSTR(0).ECAUSE <= BRKPNT;
|
119 |
|
|
elsif(MALGN_i(0) = '1' and INSTR_i(0).EXCP = '0') then
|
120 |
|
|
INSTR(0).EXCP <= '1';
|
121 |
|
|
if(is_store(INSTR_i(0).LS_OP) = '1') then
|
122 |
|
|
INSTR(0).ECAUSE <= SADRMIS;
|
123 |
|
|
else
|
124 |
|
|
INSTR(0).ECAUSE <= LADRMIS;
|
125 |
|
|
end if;
|
126 |
|
|
end if;
|
127 |
|
|
|
128 |
|
|
INSTR(1) <= INSTR_i(1);
|
129 |
|
|
if(INSTR_i(1).IMNMC = IM_SCALL and INSTR_i(1).EXCP = '0') then
|
130 |
|
|
INSTR(1).EXCP <= '1';
|
131 |
|
|
INSTR(1).ECAUSE <= UMCALL;
|
132 |
|
|
elsif(INSTR_i(1).IMNMC = IM_SBREAK and INSTR_i(1).EXCP = '0') then
|
133 |
|
|
INSTR(1).EXCP <= '1';
|
134 |
|
|
INSTR(1).ECAUSE <= BRKPNT;
|
135 |
|
|
elsif(MALGN_i(1) = '1' and INSTR_i(1).EXCP = '0') then
|
136 |
|
|
INSTR(1).EXCP <= '1';
|
137 |
|
|
if(is_store(INSTR_i(1).LS_OP) = '1') then
|
138 |
|
|
INSTR(1).ECAUSE <= SADRMIS;
|
139 |
|
|
else
|
140 |
|
|
INSTR(1).ECAUSE <= LADRMIS;
|
141 |
|
|
end if;
|
142 |
|
|
end if;
|
143 |
|
|
|
144 |
|
|
-- Division re-fetch flag
|
145 |
|
|
if(
|
146 |
|
|
INSTR_i(0).ALU_OP = ALU_DIV or
|
147 |
|
|
INSTR_i(0).ALU_OP = ALU_REM
|
148 |
|
|
) then
|
149 |
|
|
DIV_RFTCH := not(DIV_V_i);
|
150 |
|
|
else
|
151 |
|
|
DIV_RFTCH := '0';
|
152 |
|
|
end if;
|
153 |
|
|
|
154 |
|
|
-- Concurrent access (to inst. memory) re-fetch flag
|
155 |
|
|
if(
|
156 |
|
|
INSTR_i(1).LS_OP = LS_LB or
|
157 |
|
|
INSTR_i(1).LS_OP = LS_LH or
|
158 |
|
|
INSTR_i(1).LS_OP = LS_LW
|
159 |
|
|
) then
|
160 |
|
|
LOAD_RFTCH := IDADR_CFLT_i;
|
161 |
|
|
else
|
162 |
|
|
LOAD_RFTCH := '0';
|
163 |
|
|
end if;
|
164 |
|
|
|
165 |
|
|
PSLP <= LOAD_RFTCH;
|
166 |
|
|
|
167 |
|
|
-- Re-fetch flags
|
168 |
|
|
INSTR(0).RFTCH <= S2LAC_i(0) or DIV_RFTCH;
|
169 |
|
|
--INSTR(1).RFTCH <= S2LAC_i(1) or LOAD_RFTCH or B2BAC_i;
|
170 |
|
|
INSTR(1).RFTCH <= S2LAC_i(1) or B2BAC_i;
|
171 |
|
|
end process;
|
172 |
|
|
|
173 |
|
|
PSLP_o <= PSLP;
|
174 |
|
|
INSTR_o <= INSTR;
|
175 |
|
|
|
176 |
|
|
end ARC;
|