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madsilicon |
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-- --
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-----------------------------------------------------------------
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-- --
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-- Copyright (C) 2017 Stefano Tonello --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer.--
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-- --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
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-- POSSIBILITY OF SUCH DAMAGE. --
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-- --
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-----------------------------------------------------------------
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---------------------------------------------------------------
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-- RV01 Instruction Fecthing Logic (scalar version)
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---------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.RV01_CONSTS_PKG.all;
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use work.RV01_TYPES_PKG.all;
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use work.RV01_CSR_PKG.all;
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entity RV01_FTCHLOG_1W is
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port(
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CLK_i : in std_logic;
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RST_i : in std_logic;
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STRT_i : in std_logic;
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STRTPC_i : in ADR_T;
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HALT_i : in std_logic;
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BJX_i : in std_logic;
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BJTA_i : in ADR_T;
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PBX_i : in std_logic;
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PBTA_i : in ADR_T;
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KLL1_i : in std_logic;
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PJRX_i : std_logic;
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PJRTA_i : in ADR_T;
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EXCP_i : in std_logic;
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ERET_i : in std_logic;
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RFTCH_i : in std_logic;
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ETVA_i : in ADR_T;
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PSTALL_i : in std_logic;
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-- Debug interface
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DHALT_i : in std_logic;
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IFV_o : out std_logic;
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IADR0_o : out ADR_T;
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IADR_MIS_o : out std_logic
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);
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end RV01_FTCHLOG_1W;
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architecture ARC of RV01_FTCHLOG_1W is
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signal PC,PC_q : unsigned(ALEN-3 downto 0);
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signal PC_NS : unsigned(ALEN-3 downto 0);
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signal PCP4,PCP4_q : unsigned(ALEN-3 downto 0);
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signal HALT_q : std_logic;
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signal FC : std_logic;
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signal PC_NS_FC : unsigned(ALEN-3 downto 0);
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begin
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-- Halt flag register
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process(CLK_i)
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begin
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if(CLK_i = '1' and CLK_i'event) then
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if(RST_i = '1' or HALT_i = '1') then
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HALT_q <= '1';
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elsif(STRT_i = '1') then
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HALT_q <= '0';
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end if;
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end if;
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end process;
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-- Instructions are always fetched from a word address, so
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-- that PC LS 2 bits are guaranteed to be zero and are
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-- therefore not physically implemented.
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-- Fetched instruction #0 is always valid, unless processor is
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-- halted or fetch address is odd.
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IFV_o <= not(HALT_q) or STRT_i;
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-- PC register reset value is set to reset exception vector
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-- "low" address.
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-- PC register is incremented only if pipeline is not
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-- stalled (i.e. when PSTALL_i = '0').
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-- PC+4 value is pre-calculated in current cycle and stored
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-- into PCP4 to remove addition from address critical path.
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-- Program Counter register
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process(CLK_i)
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begin
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if(CLK_i = '1' and CLK_i'event) then
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if(RST_i = '1') then
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PC_q <= to_unsigned(0,SDLEN-2);
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PCP4_q <= to_unsigned(1,SDLEN-2);
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elsif((HALT_q = '0') or (STRT_i = '1')) then
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PC_q <= PC;
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PCP4_q <= PCP4;
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end if;
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end if;
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end process;
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-- PC plus 4
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PCP4 <= PC_NS + 1 when (
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PSTALL_i = '0' or
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EXCP_i = '1' or
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ERET_i = '1' or
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RFTCH_i = '1'
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) else PCP4_q;
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-- Flow change flag (non sequential fetch)
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FC <= EXCP_i or ERET_i or RFTCH_i or BJX_i;
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-- PC no-stall value
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process(PBX_i,PJRX_i,FC,PC_NS_FC,PBTA_i,PJRTA_i,PSTALL_i,PC_q,KLL1_i)
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begin
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if(PBX_i = '1' and FC = '0' and PSTALL_i = '0' and KLL1_i = '0') then
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PC_NS <= PBTA_i(ALEN-1 downto 2);
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elsif(PJRX_i = '1' and FC = '0' and PSTALL_i = '0') then
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PC_NS <= PJRTA_i(ALEN-1 downto 2);
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elsif(FC = '1' or PSTALL_i = '0') then
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PC_NS <= PC_NS_FC;
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else
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PC_NS <= PC_q;
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end if;
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end process;
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-- Current cycle PC value mux
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-- ETVA_i can be true exception vector, an address from CSR MEPC,
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-- a re-fetch address, debug memory address or a resume address.
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-- STRTPC_i can be the reset vector or an address from CSR MRV01HA.
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process(STRT_i,EXCP_i,ERET_i,RFTCH_i,ETVA_i,BJX_i,BJTA_i,
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PCP4_q,DHALT_i,STRTPC_i)
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begin
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if(
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BJX_i = '1' and
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(EXCP_i = '0' and ERET_i = '0' and RFTCH_i = '0' and DHALT_i = '0')
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) then
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-- Note: the complicated if-condition allows to remove one
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-- muxing level on BJTA_i path.
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PC_NS_FC <= BJTA_i(ALEN-1 downto 2);
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elsif(
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EXCP_i = '1' or ERET_i = '1' or RFTCH_i = '1' or DHALT_i = '1'
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) then
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PC_NS_FC <= ETVA_i(ALEN-1 downto 2);
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elsif(STRT_i = '1') then
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PC_NS_FC <= STRTPC_i(ALEN-1 downto 2);
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else
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PC_NS_FC <= PCP4_q;
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end if;
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end process;
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-- Current cycle PC
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PC <= PC_NS;
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-- Fetch address
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IADR0_o <= PC & "00";
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-- A misaligned instruction address can be generated only
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-- by a B/J instruction.
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process(BJX_i,PBX_i,PJRX_i,BJTA_i,PJRTA_i,PBTA_i)
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begin
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IADR_MIS_o <= '0';
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if(BJX_i = '1' and BJTA_i(1 downto 0) /= "00") then
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IADR_MIS_o <= '1';
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elsif(PBX_i = '1' and PBTA_i(1 downto 0) /= "00" and KLL1_i = '0') then
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IADR_MIS_o <= '1';
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elsif(PJRX_i = '1' and PJRTA_i(1 downto 0) /= "00") then
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IADR_MIS_o <= '1';
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end if;
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end process;
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end ARC;
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