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madsilicon |
-----------------------------------------------------------------
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-- --
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-----------------------------------------------------------------
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-- --
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-- Copyright (C) 2015 Stefano Tonello --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer.--
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-- --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
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-- POSSIBILITY OF SUCH DAMAGE. --
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-- --
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-----------------------------------------------------------------
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---------------------------------------------------------------
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-- RV01 halt logic (IX2 stage)
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---------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.RV01_CONSTS_PKG.all;
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use work.RV01_TYPES_PKG.all;
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use work.RV01_IDEC_PKG.all;
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entity RV01_HLTLOG_IX2 is
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generic(
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NW : natural := 2
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);
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port(
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V_i : in std_logic_vector(NW-1 downto 0);
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IMNMC0_i : in INST_MNEMONIC_T;
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PC0_i : in unsigned(ALEN-1 downto 0);
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PC1_i : in unsigned(ALEN-1 downto 0);
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HOBRK_i : in std_logic;
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HOADR_i : in std_logic_vector(NW-1 downto 0);
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HADR_i : in unsigned(ALEN-1 downto 0);
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HRQ_i : in std_logic;
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HALT_o : out std_logic_vector(NW-1 downto 0);
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HIS_o : out std_logic
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);
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end RV01_HLTLOG_IX2;
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architecture ARC of RV01_HLTLOG_IX2 is
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signal BRK0,HOBRK0 : std_logic;
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signal HOADR : std_logic_vector(NW-1 downto 0);
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begin
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-- Halt via HLT_i/HOBRK_i/HOADR_i/HADR_i interface.
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-- Instruction execution is halted on the first valid
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-- instruction which:
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-- 1) is a sbreak (if HOBRK_i = '1'), OR
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-- 2) fetch address matches HADR_i (if HOADR_i = '1'), OR
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-- 3) reaches IX3 when HRQ_i = '1'.
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-- Halting may occurs with some delay with respect to HLT_i
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-- assertion because it's "triggered" by a valid instruction.
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-- Instruction execution restarts when RSM_q and STRT_q are both '1'.
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-- Restarting is immediate.
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-- sbreak instruction flag
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BRK0 <= '1' when (IMNMC0_i = IM_SBREAK) else '0';
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-- halt-on-break flag
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HOBRK0 <= HOBRK_i and BRK0;
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-- halt-on-address flags
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HOADR(0) <= HOADR_i(0) when (PC0_i = HADR_i) else '0';
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HOADR(1) <= HOADR_i(1) when (PC1_i = HADR_i) else '0';
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-- final halt flags
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HALT_o(0) <= V_i(0) and (HOBRK0 or HOADR(0) or HRQ_i);
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HALT_o(1) <= V_i(1) and (HOADR(1) or HRQ_i);
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-- halt instruction selector
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HIS_o <= '0' when (
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HOBRK0 = '1' or
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HOADR(0) = '1' or
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(V_i(0) = '1' and HRQ_i = '1')
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) else '1';
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end ARC;
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