Subversion Repositories rv01_riscv_core

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-- Copyright (C) 2015 Stefano Tonello                          --

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-- RV01 instruction issue logic

---------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

library WORK;

use WORK.RV01_CONSTS_PKG.all;

use WORK.RV01_TYPES_PKG.all;

use WORK.RV01_ARITH_PKG.all;

entity RV01_ISSLOG is

  generic(

    NW : natural := 2

  );

  port(

    V_i : in std_logic_vector(NW-1 downto 0);

    BJX_i : in std_logic;

    PC1_i : in ADR_T;

    PS_i : in std_logic_vector(NW-1 downto 0);

    SBF_i : in std_logic;

    DIV_STRT_i : in std_logic;

    DIV_BSY_i : in std_logic;

    SEQX_i : in std_logic;

    PXE_i : in std_logic;

    PXE1_i : in std_logic;

    STEP_i : in std_logic;

    PSLP_i : in std_logic;

    V_o : out std_logic_vector(NW-1 downto 0);

    JLRA_o : out ADR_VEC_T(NW-1 downto 0);

    ISSUE_o : out std_logic_vector(NW-1 downto 0)

  );

end RV01_ISSLOG;

architecture ARC of RV01_ISSLOG is

  signal ISSUE : std_logic_vector(NW-1 downto 0);

begin

  -- Jump & link instructions return address

  -- J&L instructions need pc(instr0)+4 (coincident

  -- with pc(instr1)) and pc(instr1)+4.

  JLRA_o(0) <= PC1_i;

  JLRA_o(1) <= PC1_i + 4;

  -- Instruction issue flags

  -- Instr. #0 is issued if:

  -- 1) there's no stall due to a data dependencies AND

  -- 2) store buffer is not full AND

  -- 3) no division (multi-cycle operation) is in progress.

  ISSUE(0) <= '1' when (

    (PS_i(0) = '0') and

    (SBF_i = '0') and

    (PSLP_i = '0') and

    (DIV_STRT_i = '0' and DIV_BSY_i = '0')

  ) else '0';

  -- Instr. #1 is issued if:

  -- 1) there's no stall due to data dependencies AND

  -- 2) isntr. #0 is issued too (in-order issue rule) AND

  -- 3  isntr. #0 doesn't need to be executed sequentially AND

  -- 4) instr #1 can execute in parallel with instr. #1 AND

  -- 5) parallel instruction execution is enabled.

  --ISSUE(1) <= 

  --   not(PS1_i) and

  --   ISSUE(0) and 

  --   not(SEQX_i) and 

  --   PXE1_i and

  --   PXE_i and

  --   not(STEP_i)

  -- ...same code of above, but restructured to improve timing.

  ISSUE(1) <=

    (PXE1_i and PXE_i and not(V_i(0) and SEQX_i) and not(STEP_i))

     when (

      (PS_i(1) = '0') and

      (PSLP_i = '0') and

      (ISSUE(0) = '1')

    ) else '0';

  -- If there's a taken branch, or a jump, in IX1,

  -- instructions in ID are nullified.

  V_o(0) <= V_i(0) and not(BJX_i) and ISSUE(0);

  V_o(1) <= V_i(1) and not(BJX_i) and ISSUE(1);

  ISSUE_o <= ISSUE;

end ARC;