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madsilicon |
-----------------------------------------------------------------
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-- --
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-----------------------------------------------------------------
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-- --
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-- Copyright (C) 2017 Stefano Tonello --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer.--
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-- --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
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-- POSSIBILITY OF SUCH DAMAGE. --
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-- --
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-----------------------------------------------------------------
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---------------------------------------------------------------
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-- RV01 JALR Prediction Unit
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---------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.RV01_CONSTS_PKG.all;
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use work.RV01_TYPES_PKG.all;
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use work.RV01_FUNCS_PKG.all;
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use work.RV01_IDEC_PKG.all;
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use work.RV01_OP_PKG.all;
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entity RV01_JRPU is
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generic(
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RAS_DEPTH : natural := 4;
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JRVQ_DEPTH : natural := 2;
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PXE : std_logic := '1';
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NW : natural := 2
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);
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port(
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CLK_i : in std_logic;
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RST_i : in std_logic;
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CLR_i : in std_logic;
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KLL1_i : in std_logic;
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FSTLL_i : in std_logic;
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BJX_i : in std_logic;
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-- prediction inputs
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INSTR_i : in std_logic_vector(ILEN*2-1 downto 0);
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IF2_V_i : in std_logic_vector(NW-1 downto 0);
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IF2_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
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IF2_PC_i : in ADR_VEC_T(NW-1 downto 0);
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-- verification inputs
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IX1_V_i : in std_logic_vector(NW-1 downto 0);
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IX1_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
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IX1_OPA0_i : SDWORD_T;
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IX1_OPA1_i : SDWORD_T;
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IX1_PCP4_i : ADR_VEC_T(NW-1 downto 0);
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-- RAS management
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IX3_V_i : in std_logic_vector(NW-1 downto 0);
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IX3_INSTR_i : in DEC_INSTR_VEC_T(NW-1 downto 0);
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IX3_PCP4_i : ADR_VEC_T(NW-1 downto 0);
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KLL1_o : out std_logic;
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PJRX_o : out std_logic;
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PJRTA_o : out ADR_T;
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MPJRX_o : out std_logic_vector(NW-1 downto 0)
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);
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end RV01_JRPU;
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architecture ARC of RV01_JRPU is
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component RV01_STACK is
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generic(
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DEPTH : natural := 4;
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WIDTH : natural := 32
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);
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port(
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CLK_i : in std_logic;
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RST_i : in std_logic;
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CLR_i : in std_logic;
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PUSH_i : in std_logic;
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POP_i : in std_logic;
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D_i : in std_logic_vector(WIDTH-1 downto 0);
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SE_o : out std_logic;
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SF_o : out std_logic;
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Q_o : out std_logic_vector(WIDTH-1 downto 0)
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);
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end component;
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component RV01_QUEUE is
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generic(
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DEPTH : natural := 2;
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WIDTH : natural := 32
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);
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port(
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CLK_i : in std_logic;
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RST_i : in std_logic;
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CLR_i : in std_logic;
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RE_i : in std_logic;
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WE_i : in std_logic;
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D_i : in std_logic_vector(WIDTH-1 downto 0);
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QE_o : out std_logic;
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QF_o : out std_logic;
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Q_o : out std_logic_vector(WIDTH-1 downto 0)
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);
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end component;
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signal CLRS : std_logic := '0';
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signal RAS_PUSH,RAS_POP,RAS_FPOP_q : std_logic;
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signal RAS_SE,RAS_SF : std_logic;
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signal RAS_D,RAS_Q : std_logic_vector(SDLEN-1 downto 0);
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signal IX1_JRTA,PJRTA : ADR_T;
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signal RAS_RE,RAS_RF : std_logic;
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signal IF2_JAL : std_logic_vector(NW-1 downto 0);
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signal IF2_PJALR : std_logic_vector(NW-1 downto 0);
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signal IX1_JAL : std_logic_vector(NW-1 downto 0);
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signal IX1_NORA_JAL : std_logic_vector(NW-1 downto 0);
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signal IX1_JALR : std_logic_vector(NW-1 downto 0);
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signal IX3_JAL : std_logic_vector(NW-1 downto 0);
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signal IX3_NORA_JAL : std_logic_vector(NW-1 downto 0);
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signal IX3_JALR : std_logic_vector(NW-1 downto 0);
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signal VJALR : std_logic_vector(NW-1 downto 0);
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signal VQ_RE,VQ_WE : std_logic;
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signal VQ_QE,VQ_QF : std_logic;
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signal VQ_D,VQ_Q : std_logic_vector(SDLEN-1 downto 0);
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signal VJRTA : ADR_T;
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signal IF2_PJRX,IF2_NK_PJRX,IX1_JRX,IX3_JRX,PJRVX : std_logic;
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signal MPJRX : std_logic_vector(NW-1 downto 0);
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signal VJRX : std_logic;
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signal MTCH : std_logic_vector(NW-1 downto 0);
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signal SJC_q : natural range 0 to 2;
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signal INSTR0,INSTR1: std_logic_vector(ILEN-1 downto 0);
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signal OPCODE0,OPCODE1: std_logic_vector(7-1 downto 0);
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signal RD0,RD1 : RID_T;
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signal IMM0,IMM1: unsigned(12-1 downto 0);
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signal IF2_JAL_X : std_logic_vector(NW-1 downto 0);
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signal IF2_PJALR_X : std_logic_vector(NW-1 downto 0);
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begin
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------------------------------------
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-- Note
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------------------------------------
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-- Predicted JALR are only those used
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-- to return from a function call, which
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-- have r0 as rd (and zero immediate
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-- operand).
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-- JAL and JALR instructions supplying
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-- prediction info are those used in
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-- starting a function call, which have
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-- rd different from r0 (and zero
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-- immediate operand).
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-- Jalr instructions involved in the
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-- prediction mechanism are those used to
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-- return from a function call and therefore
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-- always have immediate field set to zero
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-- and write return address to r0.
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-- In other words, only instruction of the
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-- type jalr r0,rn,0 are predicted using
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-- the RAS.
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-- *** Prediction ***
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-- When a jalr instruction of the type of
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-- above reaches IF2, a jump is executed at
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-- address output by the RAS, unless the RAS
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-- is empty (in such case no jump is
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-- performed).
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-- *** RAS push ***
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-- When a jalr instruction of the type
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-- jalr rm,rn,0, or a jal instruction of the
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-- type jal rn,0, reaches IX1,it's return
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-- address (PC+4) is pushed on the RAS.
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-- *** RAS pop ***
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-- Every prediction triggers a RAS pop.
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-- Idea: push RAS in IX1 and remove speculative
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-- entries when a B-J mis-prediction occurs or
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-- when clearing pipe. VQ must be emptied in the
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-- same events.
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------------------------------------
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-- RAS
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------------------------------------
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U_RAS : RV01_STACK
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generic map(
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DEPTH => RAS_DEPTH,
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WIDTH => SDLEN
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)
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port map(
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CLK_i => CLK_i,
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RST_i => RST_i,
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CLR_i => CLRS,
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PUSH_i => RAS_PUSH,
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POP_i => RAS_POP,
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D_i => RAS_D,
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SE_o => RAS_SE,
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SF_o => RAS_SF,
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Q_o => RAS_Q
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);
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-- RAS is popped when a prediction occurs.
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RAS_POP <= (IF2_NK_PJRX and not(FSTLL_i) and not(IF2_JAL(0))) or RAS_FPOP_q;
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-- RAS data output is jalr predicted TA
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PJRTA <= to_unsigned(RAS_Q);
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-- RAS is pushed when a suitable jal or
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-- jalr instruction reaches IX1 stage.
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RAS_PUSH <= IX1_JRX;
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-- RAS data input is a TA supplied by a
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-- jal or jalr instruction.
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RAS_D <= to_std_logic_vector(IX1_JRTA);
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------------------------------------
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-- JR Verification queue
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------------------------------------
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U_JRVQ : RV01_QUEUE
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generic map(
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DEPTH => JRVQ_DEPTH,
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WIDTH => SDLEN
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)
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port map(
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CLK_i => CLK_i,
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RST_i => RST_i,
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CLR_i => CLR_i,
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RE_i => VQ_RE,
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WE_i => VQ_WE,
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D_i => VQ_D,
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QE_o => VQ_QE,
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QF_o => VQ_QF,
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Q_o => VQ_Q
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);
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-- VQ is written when a jalr prediction occurs.
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VQ_WE <= IF2_NK_PJRX and not(FSTLL_i) and not(IF2_JAL(0));
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-- VQ data input is RAS data output
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VQ_D <= RAS_Q;
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-- VQ is read when a prediction is verified.
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VQ_RE <= PJRVX and not(VQ_QE);
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-- VQ data output is the TA to compared with
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-- the actual TA.
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VJRTA <= to_unsigned(VQ_Q);
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------------------------------------
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-- Speculative Jump Count
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------------------------------------
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-- RAS is pushed speculatively, as
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-- instructions in IX1 may be nullified
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-- later (because of a mis-prediction
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-- detected in IX2 or an interrupt-like
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-- event raised in IX3).
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-- A count of speculative entries is kept
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-- in order to force-pop them from RAS
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-- in case the related instructions get
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-- nullified.
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-- Every entry is treated as speculative
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-- when it's pushed on RAS, thus incrementing
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-- the count.
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-- The count is decremented when:
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-- 1) a predictable jalr reaches IX3 stage.
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-- 2) a jalr prediction occurs.
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-- 3) a forced pop occurs.
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process(CLK_i)
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begin
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if(CLK_i = '1' and CLK_i'event) then
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if(RST_i = '1' or CLR_i = '1') then
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SJC_q <= 0;
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elsif(RAS_PUSH = '1') then
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SJC_q <= SJC_q + 1;
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elsif(
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(SJC_q > 0) and
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(
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IX3_JRX = '1' or
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(IF2_NK_PJRX = '1' and FSTLL_i = '0' and IF2_JAL(0) = '0') or
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RAS_FPOP_q = '1'
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)
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) then
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SJC_q <= SJC_q - 1;
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end if;
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end if;
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end process;
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------------------------------------
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-- RAS recovery
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315 |
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------------------------------------
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process(CLK_i)
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318 |
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begin
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319 |
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if(CLK_i = '1' and CLK_i'event) then
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if(RST_i = '1') then
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RAS_FPOP_q <= '0';
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elsif((BJX_i = '1' or not(MPJRX = "00")) and SJC_q > 0) then
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RAS_FPOP_q <= '1';
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elsif(RAS_FPOP_q = '1' and SJC_q <= 1) then
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RAS_FPOP_q <= '0';
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end if;
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end if;
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end process;
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------------------------------------
|
331 |
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-- IF2 stage logic (prediction)
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332 |
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------------------------------------
|
333 |
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334 |
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-- Note: only predictable JALR instructions
|
335 |
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-- are considered here!
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336 |
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INSTR0 <= INSTR_i(ILEN-1 downto 0);
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INSTR1 <= INSTR_i(ILEN*2-1 downto ILEN);
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339 |
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340 |
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OPCODE0 <= INSTR0(6 downto 0);
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341 |
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OPCODE1 <= INSTR1(6 downto 0);
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342 |
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343 |
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RD0 <= to_integer(to_unsigned(INSTR0(11 downto 7)));
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344 |
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RD1 <= to_integer(to_unsigned(INSTR1(11 downto 7)));
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345 |
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346 |
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IMM0 <= to_unsigned(INSTR0(31 downto 20));
|
347 |
|
|
IMM1 <= to_unsigned(INSTR1(31 downto 20));
|
348 |
|
|
|
349 |
|
|
-- slot #0 jalr instruction flag
|
350 |
|
|
IF2_PJALR(0) <= IF2_V_i(0) when (
|
351 |
|
|
OPCODE0 = OP_JALR and
|
352 |
|
|
RD0 = 0 and
|
353 |
|
|
IMM0 = 0
|
354 |
|
|
) else '0';
|
355 |
|
|
|
356 |
|
|
-- slot #1 jalr instruction flag
|
357 |
|
|
IF2_PJALR(1) <= (IF2_V_i(1) and PXE) when (
|
358 |
|
|
OPCODE1 = OP_JALR and
|
359 |
|
|
RD1 = 0 and
|
360 |
|
|
IMM1 = 0
|
361 |
|
|
) else '0';
|
362 |
|
|
|
363 |
|
|
-- slot #0 jal instruction flag
|
364 |
|
|
IF2_JAL(0) <= IF2_V_i(0) when (
|
365 |
|
|
OPCODE0 = OP_JAL
|
366 |
|
|
) else '0';
|
367 |
|
|
|
368 |
|
|
-- slot #1 jal instruction flag
|
369 |
|
|
IF2_JAL(1) <= (IF2_V_i(1) and PXE) when (
|
370 |
|
|
OPCODE1 = OP_JAL
|
371 |
|
|
) else '0';
|
372 |
|
|
|
373 |
|
|
---- slot #0 jalr instruction flag
|
374 |
|
|
--IF2_PJALR_X(0) <= IF2_V_i(0) when (
|
375 |
|
|
-- IF2_INSTR_i(0).BJ_OP = BJ_JALR and
|
376 |
|
|
-- IF2_INSTR_i(0).WRD = '0' and
|
377 |
|
|
-- IF2_INSTR_i(0).IMM = 0
|
378 |
|
|
--) else '0';
|
379 |
|
|
|
380 |
|
|
---- slot #0 jal instruction flag
|
381 |
|
|
--IF2_JAL_X(0) <= IF2_V_i(0) when (
|
382 |
|
|
-- IF2_INSTR_i(0).BJ_OP = BJ_JAL
|
383 |
|
|
--) else '0';
|
384 |
|
|
|
385 |
|
|
--GPXE0_1 : if(PXE = '1') generate
|
386 |
|
|
---- slot #1 jalr instruction flag
|
387 |
|
|
--IF2_PJALR_X(1) <= IF2_V_i(1) when (
|
388 |
|
|
-- IF2_INSTR_i(1).BJ_OP = BJ_JALR and
|
389 |
|
|
-- IF2_INSTR_i(1).WRD = '0' and
|
390 |
|
|
-- IF2_INSTR_i(1).IMM = 0
|
391 |
|
|
--) else '0';
|
392 |
|
|
|
393 |
|
|
-- slot #1 jal instruction flag
|
394 |
|
|
--IF2_JAL_X(1) <= IF2_V_i(1) when (
|
395 |
|
|
-- IF2_INSTR_i(1).BJ_OP = BJ_JAL
|
396 |
|
|
--) else '0';
|
397 |
|
|
|
398 |
|
|
--end generate;
|
399 |
|
|
|
400 |
|
|
--GPXE0_0 : if(PXE = '0') generate
|
401 |
|
|
--IF2_PJALR_X(1) <= '0';
|
402 |
|
|
--IF2_JAL_X(1) <= '0';
|
403 |
|
|
--end generate;
|
404 |
|
|
|
405 |
|
|
-- A jump is actually predicted if:
|
406 |
|
|
-- 1) RAS is not empty, AND
|
407 |
|
|
-- 2.a) instruction #0 is a valid
|
408 |
|
|
-- P-JALR, OR
|
409 |
|
|
-- 2.b) instruction #0 is not a
|
410 |
|
|
-- valid JAL (which would nullify
|
411 |
|
|
-- instruction #1 and instruction
|
412 |
|
|
-- #1 is a valid P-JALR
|
413 |
|
|
-- AND
|
414 |
|
|
-- 3) fetching is not stalled, AND
|
415 |
|
|
-- 4) instruction #0 is not a taken branch.
|
416 |
|
|
|
417 |
|
|
IF2_NK_PJRX <= not(RAS_SE) and
|
418 |
|
|
(IF2_PJALR(0) or (IF2_PJALR(1) and not(KLL1_i)));
|
419 |
|
|
|
420 |
|
|
IF2_PJRX <= not(RAS_SE) and
|
421 |
|
|
(IF2_PJALR(0) or IF2_PJALR(1));
|
422 |
|
|
|
423 |
|
|
-- Predicted Jump-register execute flag
|
424 |
|
|
PJRX_o <= IF2_PJRX;
|
425 |
|
|
|
426 |
|
|
-- predicted JALR target address
|
427 |
|
|
PJRTA_o <= PJRTA;
|
428 |
|
|
|
429 |
|
|
-- If instruction #0 is predicted jump
|
430 |
|
|
-- instruction #1 must be nullified.
|
431 |
|
|
|
432 |
|
|
KLL1_o <= IF2_PJALR(0); -- not actually used?
|
433 |
|
|
|
434 |
|
|
------------------------------------
|
435 |
|
|
-- IX1 stage logic (Verification)
|
436 |
|
|
------------------------------------
|
437 |
|
|
|
438 |
|
|
-- Note: the JALR instructions subject to
|
439 |
|
|
-- verification are the same candidate
|
440 |
|
|
-- for prediction.
|
441 |
|
|
|
442 |
|
|
-- slot #0 jalr instruction flag
|
443 |
|
|
VJALR(0) <= IX1_V_i(0) when (
|
444 |
|
|
IX1_INSTR_i(0).BJ_OP = BJ_JALR and
|
445 |
|
|
IX1_INSTR_i(0).WRD = '0' and
|
446 |
|
|
IX1_INSTR_i(0).IMM = 0
|
447 |
|
|
) else '0';
|
448 |
|
|
|
449 |
|
|
-- Check if instruction #0 return address
|
450 |
|
|
-- matches VQ output.
|
451 |
|
|
|
452 |
|
|
MTCH(0) <= not(VQ_QE) when (IX1_OPA0_i = to_signed(VQ_Q)) else '0';
|
453 |
|
|
|
454 |
|
|
GPXE1_1 : if(PXE = '1') generate
|
455 |
|
|
-- slot #1 jalr instruction flag
|
456 |
|
|
VJALR(1) <= IX1_V_i(1) when (
|
457 |
|
|
IX1_INSTR_i(1).BJ_OP = BJ_JALR and
|
458 |
|
|
IX1_INSTR_i(1).WRD = '0' and
|
459 |
|
|
IX1_INSTR_i(1).IMM = 0
|
460 |
|
|
) else '0';
|
461 |
|
|
|
462 |
|
|
-- Check if instruction #1 return address
|
463 |
|
|
-- matches VQ output.
|
464 |
|
|
|
465 |
|
|
MTCH(1) <= not(VQ_QE) when (IX1_OPA1_i = to_signed(VQ_Q)) else '0';
|
466 |
|
|
end generate;
|
467 |
|
|
|
468 |
|
|
GPXE1_0 : if(PXE = '0') generate
|
469 |
|
|
VJALR(1) <= '0';
|
470 |
|
|
MTCH(1) <= '0';
|
471 |
|
|
end generate;
|
472 |
|
|
|
473 |
|
|
-- A mis-prediction occurs if:
|
474 |
|
|
-- 1) instr. #0 is a P-JALR but RA doesn't
|
475 |
|
|
-- match, OR
|
476 |
|
|
-- 2) instr. #0 is NOT a P-JALR, and instr.
|
477 |
|
|
-- #1 is a P-JALR but RA doesn't match.
|
478 |
|
|
|
479 |
|
|
MPJRX(0) <= '1' when (
|
480 |
|
|
(VJALR(0) = '1' and MTCH(0) = '0') or
|
481 |
|
|
(IX1_V_i(0) = '1' and IX1_INSTR_i(0).BJ_OP = BJ_JALR and
|
482 |
|
|
(IX1_INSTR_i(0).WRD = '1' or IX1_INSTR_i(0).IMM /= 0)
|
483 |
|
|
)
|
484 |
|
|
) else '0';
|
485 |
|
|
|
486 |
|
|
MPJRX(1) <= '1' when (
|
487 |
|
|
--(IX1_NORA_JAL(0) = '0' and VJALR(0) = '0' and VJALR(1) = '1' and MTCH(1) = '0') or
|
488 |
|
|
(VJALR(0) = '0' and VJALR(1) = '1' and MTCH(1) = '0') or
|
489 |
|
|
(IX1_V_i(1) = '1' and IX1_INSTR_i(1).BJ_OP = BJ_JALR and
|
490 |
|
|
(IX1_INSTR_i(1).WRD = '1' or IX1_INSTR_i(1).IMM /= 0)
|
491 |
|
|
)
|
492 |
|
|
) else '0';
|
493 |
|
|
|
494 |
|
|
-- This signal is used to remove VQ oldest entry.
|
495 |
|
|
PJRVX <= '1' when (
|
496 |
|
|
VJALR(0) = '1' or VJALR(1) = '1'
|
497 |
|
|
) else '0';
|
498 |
|
|
|
499 |
|
|
-- Mis-predicted JALR flag
|
500 |
|
|
MPJRX_o <= MPJRX;
|
501 |
|
|
|
502 |
|
|
------------------------------------
|
503 |
|
|
-- IX3 stage logic (RAS pushing)
|
504 |
|
|
------------------------------------
|
505 |
|
|
|
506 |
|
|
-- Note: JALR instructions used to
|
507 |
|
|
-- supply prediction info are of type
|
508 |
|
|
-- different from those used for
|
509 |
|
|
-- prediction, as they have rd != r0.
|
510 |
|
|
|
511 |
|
|
-- JAL instructions with rd = r0
|
512 |
|
|
-- are detected by IX1_NORA_JAL()
|
513 |
|
|
-- flags.
|
514 |
|
|
|
515 |
|
|
-- slot #0 jalr instruction flag
|
516 |
|
|
IX3_JALR(0) <= IX3_V_i(0) when (
|
517 |
|
|
IX3_INSTR_i(0).BJ_OP = BJ_JALR and
|
518 |
|
|
IX3_INSTR_i(0).WRD = '1'
|
519 |
|
|
) else '0';
|
520 |
|
|
|
521 |
|
|
-- slot #0 jal instruction flag
|
522 |
|
|
IX3_JAL(0) <= IX3_V_i(0) when (
|
523 |
|
|
IX3_INSTR_i(0).BJ_OP = BJ_JAL and
|
524 |
|
|
IX3_INSTR_i(0).WRD = '1'
|
525 |
|
|
) else '0';
|
526 |
|
|
|
527 |
|
|
-- slot #0 no-RA jal instruction flag
|
528 |
|
|
IX3_NORA_JAL(0) <= IX3_V_i(0) when (
|
529 |
|
|
IX3_INSTR_i(0).BJ_OP = BJ_JAL and
|
530 |
|
|
IX3_INSTR_i(0).WRD = '0'
|
531 |
|
|
) else '0';
|
532 |
|
|
|
533 |
|
|
-- slot #1 jalr instruction flag
|
534 |
|
|
IX3_JALR(1) <= (IX3_V_i(1) and PXE) when (
|
535 |
|
|
IX3_INSTR_i(1).BJ_OP = BJ_JALR and
|
536 |
|
|
IX3_INSTR_i(1).WRD = '1'
|
537 |
|
|
) else '0';
|
538 |
|
|
|
539 |
|
|
-- slot #1 jal instruction flag
|
540 |
|
|
IX3_JAL(1) <= (IX3_V_i(1) and PXE) when (
|
541 |
|
|
IX3_INSTR_i(1).BJ_OP = BJ_JAL and
|
542 |
|
|
IX3_INSTR_i(1).WRD = '1'
|
543 |
|
|
) else '0';
|
544 |
|
|
|
545 |
|
|
-- slot #1 no-RA jal instruction flag
|
546 |
|
|
IX3_NORA_JAL(1) <= (IX3_V_i(1) and PXE) when (
|
547 |
|
|
IX3_INSTR_i(1).BJ_OP = BJ_JAL and
|
548 |
|
|
IX3_INSTR_i(1).WRD = '0'
|
549 |
|
|
) else '0';
|
550 |
|
|
|
551 |
|
|
------------------------------------
|
552 |
|
|
|
553 |
|
|
-- slot #0 jalr instruction flag
|
554 |
|
|
IX1_JALR(0) <= IX1_V_i(0) when (
|
555 |
|
|
IX1_INSTR_i(0).BJ_OP = BJ_JALR and
|
556 |
|
|
IX1_INSTR_i(0).WRD = '1'
|
557 |
|
|
) else '0';
|
558 |
|
|
|
559 |
|
|
-- slot #0 jal instruction flag
|
560 |
|
|
IX1_JAL(0) <= IX1_V_i(0) when (
|
561 |
|
|
IX1_INSTR_i(0).BJ_OP = BJ_JAL and
|
562 |
|
|
IX1_INSTR_i(0).WRD = '1'
|
563 |
|
|
) else '0';
|
564 |
|
|
|
565 |
|
|
-- slot #0 no-RA jal instruction flag
|
566 |
|
|
IX1_NORA_JAL(0) <= IX1_V_i(0) when (
|
567 |
|
|
IX1_INSTR_i(0).BJ_OP = BJ_JAL and
|
568 |
|
|
IX1_INSTR_i(0).WRD = '0'
|
569 |
|
|
) else '0';
|
570 |
|
|
|
571 |
|
|
-- slot #1 jalr instruction flag
|
572 |
|
|
IX1_JALR(1) <= (IX1_V_i(1) and PXE) when (
|
573 |
|
|
IX1_INSTR_i(1).BJ_OP = BJ_JALR and
|
574 |
|
|
IX1_INSTR_i(1).WRD = '1'
|
575 |
|
|
) else '0';
|
576 |
|
|
|
577 |
|
|
-- slot #1 jal instruction flag
|
578 |
|
|
IX1_JAL(1) <= (IX1_V_i(1) and PXE) when (
|
579 |
|
|
IX1_INSTR_i(1).BJ_OP = BJ_JAL and
|
580 |
|
|
IX1_INSTR_i(1).WRD = '1'
|
581 |
|
|
) else '0';
|
582 |
|
|
|
583 |
|
|
-- slot #1 no-RA jal instruction flag
|
584 |
|
|
IX1_NORA_JAL(1) <= (IX1_V_i(1) and PXE) when (
|
585 |
|
|
IX1_INSTR_i(1).BJ_OP = BJ_JAL and
|
586 |
|
|
IX1_INSTR_i(1).WRD = '0'
|
587 |
|
|
) else '0';
|
588 |
|
|
|
589 |
|
|
-- IX1 JALR execute flag
|
590 |
|
|
IX1_JRX <=
|
591 |
|
|
(IX1_JALR(0) or IX1_JAL(0)) or
|
592 |
|
|
(not(IX1_NORA_JAL(0)) and(IX1_JALR(1) or IX1_JAL(1)));
|
593 |
|
|
|
594 |
|
|
-- JALR return address
|
595 |
|
|
IX1_JRTA <= IX1_PCP4_i(0) when (
|
596 |
|
|
IX1_JALR(0) = '1' or IX1_JAL(0) = '1'
|
597 |
|
|
) else IX1_PCP4_i(1);
|
598 |
|
|
|
599 |
|
|
-- IX3 JALR execute flag
|
600 |
|
|
IX3_JRX <=
|
601 |
|
|
(IX3_JALR(0) or IX3_JAL(0)) or
|
602 |
|
|
(not(IX3_NORA_JAL(0)) and(IX3_JALR(1) or IX3_JAL(1)));
|
603 |
|
|
|
604 |
|
|
end ARC;
|