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[/] [rv01_riscv_core/] [trunk/] [VHDL/] [RV01_logicu.vhd] - Blame information for rev 2

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1 2 madsilicon
-----------------------------------------------------------------
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--                                                             --
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-----------------------------------------------------------------
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--                                                             --
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-- Copyright (C) 2015 Stefano Tonello                          --
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--                                                             --
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-- This source file may be used and distributed without        --
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-- restriction provided that this copyright statement is not   --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer.--
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--                                                             --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY         --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  --
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-- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
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-- POSSIBILITY OF SUCH DAMAGE.                                 --
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--                                                             --
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-----------------------------------------------------------------
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---------------------------------------------------------------
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-- RV01 logic (boolean) unit
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---------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library WORK;
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use WORK.RV01_CONSTS_PKG.all;
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use WORK.RV01_TYPES_PKG.all;
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use WORK.RV01_ARITH_PKG.all;
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entity RV01_LOGICU is
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  port(
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    CTRL_i : in LOG_CTRL;
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    OPA_i : in SDWORD_T;
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    OPB_i : in SDWORD_T;
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    RES_o : out SDWORD_T
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  );
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end RV01_LOGICU;
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architecture ARC of RV01_LOGICU is
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begin
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  process(CTRL_i,OPA_i,OPB_i)
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  begin
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    case CTRL_i is
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      when LC_AND =>
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        RES_o(SDLEN-1 downto 0) <= (OPA_i and OPB_i);
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      when LC_OR =>
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        RES_o(SDLEN-1 downto 0) <= (OPA_i or OPB_i);
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      when others => --LC_XOR
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        RES_o(SDLEN-1 downto 0) <= (OPA_i xor OPB_i);
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    end case;
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  end process;
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end ARC;

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