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madsilicon |
-----------------------------------------------------------------
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-- --
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-----------------------------------------------------------------
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-- --
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-- Copyright (C) 2015 Stefano Tonello --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer.--
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-- --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
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-- POSSIBILITY OF SUCH DAMAGE. --
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-- --
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-----------------------------------------------------------------
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---------------------------------------------------------------
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-- 32-bit leading 0's detector
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---------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library WORK;
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--use work.RV01_CONSTS_PKG.all;
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--use work.RV01_TYPES_PKG.all;
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use WORK.RV01_FUNCS_PKG.all;
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--use WORK.RV01_ARITH_PKG.all;
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entity RV01_LZD32 is
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generic(
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WIDTH : natural := 32
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);
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port(
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A_i : in std_logic_vector(WIDTH-1 downto 0);
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CNT_o : out std_logic_vector(6-1 downto 0)
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);
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end RV01_LZD32;
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architecture ARC of RV01_LZD32 is
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constant MAXZ : natural := 32;
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constant ONE : unsigned(WIDTH-1 downto 0) := to_unsigned(1,WIDTH);
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function CHK(
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U : unsigned(WIDTH-1 downto 0);
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N : natural range 0 to WIDTH-1
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) return std_logic is
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begin
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if((U srl N) = ONE) then
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return('1');
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else
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return('0');
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end if;
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end function;
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signal CNT : natural range 0 to WIDTH;
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begin
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process(A_i)
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variable TMP : std_logic_vector(MAXZ-1 downto 0);
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begin
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for i in 0 to MAXZ-1 loop
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TMP(i) := CHK(to_unsigned(A_i),i);
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end loop;
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case TMP is
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when "10000000000000000000000000000000"=> CNT <= 0;
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when "01000000000000000000000000000000"=> CNT <= 1;
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when "00100000000000000000000000000000"=> CNT <= 2;
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when "00010000000000000000000000000000"=> CNT <= 3;
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when "00001000000000000000000000000000"=> CNT <= 4;
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when "00000100000000000000000000000000"=> CNT <= 5;
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when "00000010000000000000000000000000"=> CNT <= 6;
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when "00000001000000000000000000000000"=> CNT <= 7;
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when "00000000100000000000000000000000"=> CNT <= 8;
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when "00000000010000000000000000000000"=> CNT <= 9;
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when "00000000001000000000000000000000"=> CNT <= 10;
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when "00000000000100000000000000000000"=> CNT <= 11;
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when "00000000000010000000000000000000"=> CNT <= 12;
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when "00000000000001000000000000000000"=> CNT <= 13;
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when "00000000000000100000000000000000"=> CNT <= 14;
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when "00000000000000010000000000000000"=> CNT <= 15;
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when "00000000000000001000000000000000"=> CNT <= 16;
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when "00000000000000000100000000000000"=> CNT <= 17;
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when "00000000000000000010000000000000"=> CNT <= 18;
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when "00000000000000000001000000000000"=> CNT <= 19;
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when "00000000000000000000100000000000"=> CNT <= 20;
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when "00000000000000000000010000000000"=> CNT <= 21;
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when "00000000000000000000001000000000"=> CNT <= 22;
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when "00000000000000000000000100000000"=> CNT <= 23;
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when "00000000000000000000000010000000"=> CNT <= 24;
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when "00000000000000000000000001000000"=> CNT <= 25;
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when "00000000000000000000000000100000"=> CNT <= 26;
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when "00000000000000000000000000010000"=> CNT <= 27;
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when "00000000000000000000000000001000"=> CNT <= 28;
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when "00000000000000000000000000000100"=> CNT <= 29;
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when "00000000000000000000000000000010"=> CNT <= 30;
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when "00000000000000000000000000000001"=> CNT <= 31;
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when others => CNT <= 32;
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end case;
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end process;
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CNT_o <= to_std_logic_vector(to_unsigned(CNT,6));
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end ARC;
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