Subversion Repositories rv01_riscv_core

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-- Copyright (C) 2016 Stefano Tonello                          --

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-- RV01 Misc Logic IX3

---------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

library work;

use work.RV01_CONSTS_PKG.all;

use work.RV01_TYPES_PKG.all;

use work.RV01_IDEC_PKG.all;

entity RV01_MISCLOG_IX3 is

  generic(

    PXE : std_logic := '0';

    NW : natural := 2

  );

  port(

    IX1_V0_i : in std_logic;

    IX1_WCSR0_i : in std_logic;

    V_i : in std_logic_vector(NW-1 downto 0);

    DWE_i : in std_logic_vector(NW-1 downto 0);

    KPRD_i : in std_logic_vector(NW-1 downto 0);

    WRD0_i : in std_logic;

    WRD1_i : in std_logic;

    HALT_i : in std_logic_vector(NW-1 downto 0);

    CLRP_i : in std_logic;

    CLRD_i : in std_logic;

    HIS_i : in std_logic;

    PC0_i : in ADR_T;

    PC1_i : in ADR_T;

    CP_WE_o : out std_logic;

    SBRE_o : out std_logic_vector(NW-1 downto 0);

    STL_o : out std_logic_vector(NW-1 downto 0);

    WE_o : out std_logic_vector(NW-1 downto 0);

    HALT_o : out std_logic;

    CLRP_o : out std_logic;

    CLRD_o : out std_logic;

    HPC_o : out ADR_T

  );

end RV01_MISCLOG_IX3;

architecture ARC of RV01_MISCLOG_IX3 is

  signal HALT : std_logic;

begin

  -- CP write enable flag

  -- (WARNING: CSR's are written in IX1, rather than in IX3!)

  CP_WE_o <=

    IX1_V0_i and IX1_WCSR0_i;

  -- store buffer read enable

  SBRE_o(0) <=

    V_i(0) and DWE_i(0);

  SBRE_o(1) <=

    V_i(1) and DWE_i(1) and PXE;

  -- stall flags

  STL_o(0) <= KPRD_i(0);

  STL_o(1) <= KPRD_i(1);

  -- Register File write-enable flags

  WE_o(0) <= V_i(0) and WRD0_i;

  WE_o(1) <= V_i(1) and WRD1_i;

  -- processor halt flag

  HALT <= HALT_i(0) or HALT_i(1);

  HALT_o <= HALT;

  -- clear pipe flag

  CLRP_o <= CLRP_i or HALT;

  -- clear divider flag

  CLRD_o <= CLRD_i or HALT;

  -- halt PC

  HPC_o <= PC0_i when (HIS_i = '0') else PC1_i;

end ARC;