OpenCores
URL https://opencores.org/ocsvn/rv01_riscv_core/rv01_riscv_core/trunk

Subversion Repositories rv01_riscv_core

[/] [rv01_riscv_core/] [trunk/] [VHDL/] [RV01_queue.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 madsilicon 
-----------------------------------------------------------------
2 
--                                                             --
3 
-----------------------------------------------------------------
4 
--                                                             --
5 
-- Copyright (C) 2017 Stefano Tonello                          --
6 
--                                                             --
7 
-- This source file may be used and distributed without        --
8 
-- restriction provided that this copyright statement is not   --
9 
-- removed from the file and that any derivative work contains --
10 
-- the original copyright notice and the associated disclaimer.--
11 
--                                                             --
12 
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY         --
13 
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   --
14 
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   --
15 
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      --
16 
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         --
17 
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    --
18 
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   --
19 
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        --
20 
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  --
21 
-- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  --
22 
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  --
23 
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         --
24 
-- POSSIBILITY OF SUCH DAMAGE.                                 --
25 
--                                                             --
26 
-----------------------------------------------------------------
27 
 
28 
---------------------------------------------------------------
29 
-- RV01 JALR Verification Queue
30 
---------------------------------------------------------------
31 
 
32 
library IEEE;
33 
use IEEE.std_logic_1164.all;
34 
use IEEE.numeric_std.all;
35 
 
36 
library work;
37 
use work.RV01_CONSTS_PKG.all;
38 
use work.RV01_TYPES_PKG.all;
39 
use work.RV01_FUNCS_PKG.all;
40 
 
41 
entity RV01_QUEUE is
42 
  generic(
43 
    DEPTH : natural := 2;
44 
    WIDTH : natural := 32
45 
  );
46 
  port(
47 
    CLK_i : in std_logic;
48 
    RST_i : in std_logic;
49 
    CLR_i : in std_logic;
50 
    RE_i : in std_logic;
51 
    WE_i : in std_logic;
52 
    D_i : in std_logic_vector(WIDTH-1 downto 0);
53 
 
54 
    QE_o : out std_logic;
55 
    QF_o : out std_logic;
56 
    Q_o : out std_logic_vector(WIDTH-1 downto 0)
57 
  );
58 
end RV01_QUEUE;
59 
 
60 
architecture ARC of RV01_QUEUE is
61 
 
62 
   subtype QUEUE_ENTRY_T is std_logic_vector(WIDTH-1 downto 0);
63 
   type QUEUE_ENTRY_VEC_T is array (natural range<>) of QUEUE_ENTRY_T;
64 
 
65 
   signal Q,Q_q : QUEUE_ENTRY_VEC_T(DEPTH-1 downto 0);
66 
   signal HP,HP_q : natural range 0 to DEPTH;
67 
   signal QE_q,QF_q : std_logic;
68 
 
69 
begin
70 
 
71 
  ------------------------------------
72 
  -- Head pointer registers.
73 
  ------------------------------------
74 
 
75 
  process(CLK_i)
76 
  begin
77 
    if(CLK_i = '1' and CLK_i'event) then
78 
      if(RST_i = '1' or CLR_i = '1') then
79 
        HP_q <= 0;
80 
      elsif(WE_i = '1' and RE_i = '0') then
81 
        HP_q <= HP_q + 1;
82 
      elsif(RE_i = '1' and WE_i = '0') then
83 
        HP_q <= HP_q - 1;
84 
      end if;
85 
    end if;
86 
  end process;
87 
 
88 
  ------------------------------------
89 
  -- Queue update logic.
90 
  ------------------------------------
91 
 
92 
  process(Q_q,HP_q,RE_i,WE_i,D_i)
93 
  begin
94 
    for k in 0 to DEPTH-1 loop
95 
      Q(k) <= Q_q(k);
96 
      if(RE_i = '1') then
97 
        if(k < DEPTH-1) then
98 
          Q(k) <= Q_q(k+1);
99 
        else
100 
          Q(k) <= (others => '0');
101 
        end if;
102 
      end if;
103 
      if(WE_i = '1' and RE_i = '0') then
104 
        if(k = HP_q) then
105 
          Q(k) <= D_i;
106 
        end if;
107 
      elsif(WE_i = '1' and RE_i = '1') then
108 
        if(k = HP_q-1) then
109 
          Q(k) <= D_i;
110 
        end if;
111 
      end if;
112 
    end loop;
113 
  end process;
114 
 
115 
  ------------------------------------
116 
  -- Queue registers.
117 
  ------------------------------------
118 
 
119 
  process(CLK_i)
120 
  begin
121 
    if(CLK_i = '1' and CLK_i'event) then
122 
      for k in 0 to DEPTH-1 loop
123 
        Q_q(k) <= Q(k);
124 
      end loop;
125 
    end if;
126 
  end process;
127 
 
128 
  ------------------------------------
129 
  -- Queue Empty flag register.
130 
  ------------------------------------
131 
 
132 
  process(CLK_i)
133 
  begin
134 
    if(CLK_i = '1' and CLK_i'event) then
135 
      if(RST_i = '1' or CLR_i = '1') then
136 
        QE_q <= '0';
137 
      elsif((HP_q = 0 and WE_i = '0') or (HP_q = 1 and RE_i = '1')) then
138 
        QE_q <= '1';
139 
      else
140 
        QE_q <= '0';
141 
      end if;
142 
    end if;
143 
  end process;
144 
 
145 
  ------------------------------------
146 
  -- Queue Full flag register.
147 
  ------------------------------------
148 
 
149 
  process(CLK_i)
150 
  begin
151 
    if(CLK_i = '1' and CLK_i'event) then
152 
      if(RST_i = '1' or CLR_i = '1') then
153 
        QF_q <= '0';
154 
      elsif((HP_q = DEPTH and RE_i = '0') or (HP_q = DEPTH-1 and WE_i = '1')) then
155 
        QF_q <= '1';
156 
      else
157 
        QF_q <= '0';
158 
      end if;
159 
    end if;
160 
  end process;
161 
 
162 
  ------------------------------------
163 
  -- Outputs
164 
  ------------------------------------
165 
 
166 
  QE_o <= QE_q;
167 
 
168 
  QF_o <= QF_q;
169 
 
170 
  Q_o <= Q_q(0);
171 
 
172 
end ARC;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.