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madsilicon |
-----------------------------------------------------------------
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-- --
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-----------------------------------------------------------------
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-- --
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-- Copyright (C) 2017 Stefano Tonello --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer.--
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-- --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
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-- POSSIBILITY OF SUCH DAMAGE. --
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-- --
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-----------------------------------------------------------------
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------------------------------------------------------------
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-- synchronous write, synchronous-read 1 read/write port RAM
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-- with separated input and output data buses
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------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.RV01_CONSTS_PKG.all;
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use work.RV01_TYPES_PKG.all;
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use work.RV01_FUNCS_PKG.all;
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entity RV01_RAM_1RW is
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generic(
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-- I/O data bus width
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DWIDTH : integer := 16;
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-- word count
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WCOUNT : integer := 256;
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STYLE : string := "auto"
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);
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port(
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CLK_i : in std_logic;
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A_i : in unsigned(log2(WCOUNT)-1 downto 0);
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D_i : in std_logic_vector(DWIDTH-1 downto 0);
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WE_i : in std_logic;
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Q_o : out std_logic_vector(DWIDTH-1 downto 0)
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);
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end RV01_RAM_1RW;
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architecture ARC of RV01_RAM_1RW is
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type MEM_TYPE is array (WCOUNT-1 downto 0) of std_logic_vector(DWIDTH-1 downto 0);
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signal RAM_DATA : MEM_TYPE;
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attribute ram_style: string;
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attribute ram_style of RAM_DATA : signal is STYLE;
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begin
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process(CLK_i)
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begin
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if(CLK_i = '1' and CLK_i'event)then
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if WE_i = '1' then
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RAM_DATA(to_integer(A_i)) <= D_i;
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end if;
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Q_o <= RAM_DATA(to_integer(A_i));
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end if;
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end process;
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end ARC;
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------------------------------------------------------------
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-- synchronous write, synchronous-read 1 read/write port,
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-- plus 1 read-only port, RAM, with separated input and
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-- output data buses
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------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.RV01_CONSTS_PKG.all;
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use work.RV01_TYPES_PKG.all;
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use work.RV01_FUNCS_PKG.all;
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entity RV01_RAM_1RW1R is
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generic(
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-- I/O data bus width
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DWIDTH : integer := 16;
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-- word count
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WCOUNT : integer := 256;
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STYLE : string := "auto"
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);
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port(
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CLK_i : in std_logic;
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A_i : in unsigned(log2(WCOUNT)-1 downto 0);
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DPRA_i : in unsigned(log2(WCOUNT)-1 downto 0);
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D_i : in std_logic_vector(DWIDTH-1 downto 0);
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WE_i : in std_logic;
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Q_o : out std_logic_vector(DWIDTH-1 downto 0);
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DPQ_o : out std_logic_vector(DWIDTH-1 downto 0)
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);
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end RV01_RAM_1RW1R;
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architecture ARC of RV01_RAM_1RW1R is
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type MEM_TYPE is array (WCOUNT-1 downto 0) of std_logic_vector(DWIDTH-1 downto 0);
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signal RAM_DATA : MEM_TYPE;
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attribute ram_style: string;
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attribute ram_style of RAM_DATA : signal is STYLE;
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begin
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process(CLK_i)
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begin
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if(CLK_i = '1' and CLK_i'event)then
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if WE_i = '1' then
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RAM_DATA(to_integer(A_i)) <= D_i;
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end if;
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Q_o <= RAM_DATA(to_integer(A_i));
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DPQ_o <= RAM_DATA(to_integer(DPRA_i));
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end if;
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end process;
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end ARC;
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------------------------------------------------------------
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-- synchronous write, synchronous-read 1 read/write port,
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-- plus 1 read-only port, RAM, with separated input and
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-- output data buses.
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-- This version supports byte-selectable writes, and
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-- therefore WIDTH generic value must be a multiple of 8.
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------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.RV01_CONSTS_PKG.all;
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use work.RV01_TYPES_PKG.all;
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use work.RV01_FUNCS_PKG.all;
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entity RV01_RAM_1RW1R_BE is
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generic(
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-- I/O data bus width
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DWIDTH : integer := 16;
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-- word count
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WCOUNT : integer := 256;
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STYLE : string := "auto"
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);
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port(
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CLK_i : in std_logic;
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A_i : in unsigned(log2(WCOUNT)-1 downto 0);
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DPRA_i : in unsigned(log2(WCOUNT)-1 downto 0);
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D_i : in std_logic_vector(DWIDTH-1 downto 0);
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BE_i : in std_logic_vector(DWIDTH/8-1 downto 0);
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WE_i : in std_logic;
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Q_o : out std_logic_vector(DWIDTH-1 downto 0);
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DPQ_o : out std_logic_vector(DWIDTH-1 downto 0)
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);
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end RV01_RAM_1RW1R_BE;
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architecture ARC of RV01_RAM_1RW1R_BE is
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constant BW : integer := 8;
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type MEM_TYPE is array (WCOUNT-1 downto 0) of std_logic_vector(DWIDTH-1 downto 0);
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signal RAM_DATA : MEM_TYPE;
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attribute ram_style: string;
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attribute ram_style of RAM_DATA : signal is STYLE;
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begin
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process(CLK_i)
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variable TMP : std_logic_vector(DWIDTH-1 downto 0);
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begin
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if(CLK_i = '1' and CLK_i'event)then
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if WE_i = '1' then
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TMP := RAM_DATA(to_integer(A_i));
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for i in 0 to DWIDTH/BW-1 loop
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if(BE_i(i) = '1') then
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TMP(BW*(i+1)-1 downto BW*i) := D_i(BW*(i+1)-1 downto BW*i);
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end if;
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end loop;
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RAM_DATA(to_integer(A_i)) <= TMP;
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end if;
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Q_o <= RAM_DATA(to_integer(A_i));
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DPQ_o <= RAM_DATA(to_integer(DPRA_i));
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end if;
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end process;
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end ARC;
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------------------------------------------------------------
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-- synchronous write, synchronous-read 1 read/write port,
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-- RAM, with separated input and output data buses.
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213 |
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-- This version supports byte-selectable writes, and
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-- therefore WIDTH generic value must be a multiple of 8.
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------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.RV01_CONSTS_PKG.all;
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use work.RV01_TYPES_PKG.all;
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use work.RV01_FUNCS_PKG.all;
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entity RV01_RAM_1RW_BE is
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generic(
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-- I/O data bus width
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DWIDTH : integer := 16;
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-- word count
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WCOUNT : integer := 256;
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STYLE : string := "auto"
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);
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port(
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CLK_i : in std_logic;
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A_i : in unsigned(log2(WCOUNT)-1 downto 0);
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D_i : in std_logic_vector(DWIDTH-1 downto 0);
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BE_i : in std_logic_vector(DWIDTH/8-1 downto 0);
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WE_i : in std_logic;
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Q_o : out std_logic_vector(DWIDTH-1 downto 0)
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);
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end RV01_RAM_1RW_BE;
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architecture ARC of RV01_RAM_1RW_BE is
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constant BW : integer := 8;
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type MEM_TYPE is array (WCOUNT-1 downto 0) of std_logic_vector(DWIDTH-1 downto 0);
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signal RAM_DATA : MEM_TYPE;
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attribute ram_style: string;
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attribute ram_style of RAM_DATA : signal is STYLE;
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begin
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process(CLK_i)
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variable TMP : std_logic_vector(DWIDTH-1 downto 0);
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begin
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if(CLK_i = '1' and CLK_i'event)then
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if WE_i = '1' then
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TMP := RAM_DATA(to_integer(A_i));
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for i in 0 to DWIDTH/BW-1 loop
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if(BE_i(i) = '1') then
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TMP(BW*(i+1)-1 downto BW*i) := D_i(BW*(i+1)-1 downto BW*i);
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end if;
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end loop;
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RAM_DATA(to_integer(A_i)) <= TMP;
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end if;
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Q_o <= RAM_DATA(to_integer(A_i));
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end if;
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end process;
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end ARC;
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