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madsilicon |
-----------------------------------------------------------------
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-- --
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-----------------------------------------------------------------
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-- --
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-- Copyright (C) 2015 Stefano Tonello --
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-- --
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-- This source file may be used and distributed without --
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-- restriction provided that this copyright statement is not --
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-- removed from the file and that any derivative work contains --
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-- the original copyright notice and the associated disclaimer.--
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-- --
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY --
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED --
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR --
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, --
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES --
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR --
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT --
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --
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-- POSSIBILITY OF SUCH DAMAGE. --
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-- --
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-----------------------------------------------------------------
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---------------------------------------------------------------
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-- RV01 32x32 Register File
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---------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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use work.RV01_CONSTS_PKG.all;
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use work.RV01_TYPES_PKG.all;
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entity RV01_REGFILE_32X32_2W is
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port(
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CLK_i : in std_logic;
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RA0_i : in RID_T;
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RA1_i : in RID_T;
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RA2_i : in RID_T;
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RA3_i : in RID_T;
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WA0_i : in RID_T;
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WA1_i : in RID_T;
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WE0_i : in std_logic;
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WE1_i : in std_logic;
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D0_i : in std_logic_vector(SDLEN-1 downto 0);
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D1_i : in std_logic_vector(SDLEN-1 downto 0);
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Q0_o : out std_logic_vector(SDLEN-1 downto 0);
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Q1_o : out std_logic_vector(SDLEN-1 downto 0);
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Q2_o : out std_logic_vector(SDLEN-1 downto 0);
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Q3_o : out std_logic_vector(SDLEN-1 downto 0)
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);
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end RV01_REGFILE_32X32_2W;
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architecture ARC of RV01_REGFILE_32X32_2W is
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subtype WORD_T is std_logic_vector(SDLEN-1 downto 0);
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type MEM_T is array (REGNUM-1 downto 0) of WORD_T;
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signal REG_q : MEM_T;
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begin
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-- sync. write
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process(CLK_i)
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begin
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if(CLK_i = '1' and CLK_i'event) then
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if(WE0_i = '1') then
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REG_q(WA0_i) <= D0_i;
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end if;
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if(WE1_i = '1') then
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REG_q(WA1_i) <= D1_i;
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end if;
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end if;
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end process;
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-- async. read
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Q0_o <= REG_q(RA0_i) when not(RA0_i = 0) else (others => '0');
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Q1_o <= REG_q(RA1_i) when not(RA1_i = 0) else (others => '0');
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Q2_o <= REG_q(RA2_i) when not(RA2_i = 0) else (others => '0');
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Q3_o <= REG_q(RA3_i) when not(RA3_i = 0) else (others => '0');
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end ARC;
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