Subversion Repositories rv01_riscv_core

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-- Copyright (C) 2015 Stefano Tonello                          --

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-- RV01 shift unit

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library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

library WORK;

use WORK.RV01_CONSTS_PKG.all;

use WORK.RV01_TYPES_PKG.all;

use WORK.RV01_FUNCS_PKG.all;

use WORK.RV01_ARITH_PKG.all;

entity RV01_SHFTU is

  port(

    CTRL_i : in SHF_CTRL;

    SI_i : in SDWORD_T;

    SHFT_i : in unsigned(5-1 downto 0);

    SU_i : in std_logic;

    SO_o : out SDWORD_T

  );

end RV01_SHFTU;

architecture ARC of RV01_SHFTU is

  signal SHFT : SHORT_SHIFT_T;

  signal LSO : SDWORD_T;

  signal RSOS : SDWORD_T;

  signal RSOU : SDWORD_T;

begin

  -- get shift amount

  SHFT <= to_integer(SHFT_i);

  -- 32-bit left shifter

  LSO <= shift_left32(SI_i,SHFT);

  -- 32-bit signed right shifter

  RSOS <= shift_right32(SI_i,SHFT);

  -- 32-bit unsigned right shifter

  RSOU <= to_signed(shift_right32(to_unsigned(SI_i),SHFT));

  SO_o <=

    LSO when (CTRL_i = SC_SHL) else

    RSOS when (CTRL_i = SC_SHR and SU_i = '1') else

    RSOU;

end ARC;