Subversion Repositories rv01_riscv_core

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-- Copyright (C) 2016 Stefano Tonello                          --

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-- RV01 self-test module test-bench

---------------------------------------------------------------

---------------------------------------------------------------

-- Notes:

---------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use STD.textio.all;

library work;

entity RV01_SELFTEST_TB is

end RV01_SELFTEST_TB;

architecture ARC of RV01_SELFTEST_TB is

  component RV01_SELFTEST is

    port(

      CLK_i : in std_logic; -- clock

      RST_i : in std_logic; -- reset

      DONE_o : out std_logic; -- test complete

      PASS_o : out std_logic -- test pass

    );

  end component;

  signal CLK : std_logic := '0';

  signal RST : std_logic := '1';

  signal DONE : std_logic;

  signal PASS : std_logic;

begin

  ---------------------------------------------------

  -- Clock & Reset signals

  ---------------------------------------------------

  CLK <= not(CLK) after 10 ns;

  RST <= '0' after 20 ns;

  ---------------------------------------------------

  -- Self-test module instance

  ---------------------------------------------------

  U_DUT : RV01_SELFTEST

    port map(

      CLK_i => CLK,

      RST_i => RST,

      DONE_o => DONE,

      PASS_o => PASS

    );

end ARC;