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[/] [s1_core/] [trunk/] [hdl/] [behav/] [testbench/] [testbench.v] - Blame information for rev 103

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/*
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 * Simply RISC S1 Testbench
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 *
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 * (C) 2007 Simply RISC LLP
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 * AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
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 *
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 * LICENSE:
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 * This is a Free Hardware Design; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License
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 * version 2 as published by the Free Software Foundation.
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 * The above named program is distributed in the hope that it will
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 * be useful, but WITHOUT ANY WARRANTY; without even the implied
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 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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 * See the GNU General Public License for more details.
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 *
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 * DESCRIPTION:
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 * This is the testbench for the functional verification of the
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 * S1 Core: it makes and instance of the S1 module to make it
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 * possible to access one or more memory harnesses.
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 */
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`include "s1_defs.h"
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module testbench ();
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  /*
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   * Wires
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   */
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  // Interrupt Requests
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  wire[63:0] sys_irq;
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  // Wishbone Master inputs / Wishbone Slave ouputs
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  wire wb_ack;                                 // Ack
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  wire[(`WB_DATA_WIDTH-1):0] wb_datain;        // Data In
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  // Wishbone Master outputs / Wishbone Slave inputs
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  wire wb_cycle;                               // Cycle Start
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  wire wb_strobe;                              // Strobe Request
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  wire wb_we_o;                                // Write Enable
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  wire[`WB_ADDR_WIDTH-1:0] wb_addr;            // Address Bus
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  wire[`WB_DATA_WIDTH-1:0] wb_dataout;         // Data Out
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  wire[`WB_DATA_WIDTH/8-1:0] wb_sel;           // Select Output
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  // Separate Cycle, Strobe and Ack wires for ROM and RAM memory harnesses
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  wire wb_cycle_ram;
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  wire wb_cycle_rom;
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  wire wb_strobe_ram;
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  wire wb_strobe_rom;
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  wire wb_ack_ram;
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  wire wb_ack_rom;
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  // Decode the address and select the proper memory bank
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  assign wb_cycle_rom  = ( (wb_addr[39:12]==28'hFFF0000) ? wb_cycle : 0 );
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  assign wb_strobe_rom = ( (wb_addr[39:12]==28'hFFF0000) ? wb_strobe : 0 );
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  assign wb_cycle_ram  = ( (wb_addr[39:16]==24'h000004) ? wb_cycle : 0 );
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  assign wb_strobe_ram = ( (wb_addr[39:16]==24'h000004) ? wb_strobe : 0 );
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  assign wb_ack = wb_ack_ram | wb_ack_rom;
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  /*
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   * Registers
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   */
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  // System signals
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  reg sys_clock;
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  reg sys_reset;
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  /*
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   * Behavior
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   */
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  always #1 sys_clock = ~sys_clock;
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  assign sys_irq = 64'b0;
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  initial begin
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    // Display start message
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    $display("INFO: TBENCH: Starting Simply RISC S1 Core simulation...");
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    // Create VCD trace file
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    $dumpfile("trace.vcd");
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    $dumpvars();
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    // Run the simulation
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    sys_clock <= 1'b1;
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    sys_reset <= 1'b1;
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    #1000
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    sys_reset <= 1'b0;
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    #49000
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    $display("INFO: TBENCH: Completed Simply RISC S1 Core simulation!");
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    $finish;
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  end
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  /*
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   * Module instances
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   */
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  // Simply RISC S1 Core
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  s1_top s1_top_0 (
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    // System inputs
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    .sys_clock_i(sys_clock),
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    .sys_reset_i(sys_reset),
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    .sys_irq_i(sys_irq),
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    // Wishbone Master inputs
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    .wbm_ack_i(wb_ack),
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    .wbm_data_i(wb_datain),
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    // Wishbone Master outputs
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    .wbm_cycle_o(wb_cycle),
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    .wbm_strobe_o(wb_strobe),
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    .wbm_we_o(wb_we),
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    .wbm_addr_o(wb_addr),
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    .wbm_data_o(wb_dataout),
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    .wbm_sel_o(wb_sel)
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  );
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  // Wishbone memory harness used as ROM
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  mem_harness rom_harness (
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    // System inputs
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    .sys_clock_i(sys_clock),
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    .sys_reset_i(sys_reset),
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    // Wishbone Slave inputs
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    .wbs_addr_i(wb_addr),
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    .wbs_data_i(wb_dataout),
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    .wbs_cycle_i(wb_cycle_rom),
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    .wbs_strobe_i(wb_strobe_rom),
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    .wbs_sel_i(wb_sel),
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    .wbs_we_i(wb_we),
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    // Wishbone Slave outputs
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    .wbs_data_o(wb_datain),
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    .wbs_ack_o(wb_ack_rom)
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  );
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  // Wishbone memory harness used as RAM
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  mem_harness ram_harness (
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    // System inputs
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    .sys_clock_i(sys_clock),
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    .sys_reset_i(sys_reset),
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    // Wishbone Slave inputs
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    .wbs_addr_i(wb_addr),
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    .wbs_data_i(wb_dataout),
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    .wbs_cycle_i(wb_cycle_ram),
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    .wbs_strobe_i(wb_strobe_ram),
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    .wbs_sel_i(wb_sel),
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    .wbs_we_i(wb_we),
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    // Wishbone Slave outputs
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    .wbs_data_o(wb_datain),
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    .wbs_ack_o(wb_ack_ram)
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  );
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  /*
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   * Parameters for memory harnesses
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   */
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  // ROM has Physical Address range [0xFFF0000000:0xFFF0000FFF]
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  // so size is 4 KByte and requires 12 address bits
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  // 3 of which are ignored being a 64-bit memory => addr_bits=9
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  // (it was section RED_SEC in the official OpenSPARC-T1 testbench)
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  defparam rom_harness.addr_bits = 9;
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  defparam rom_harness.memfilename = "rom_harness.hex";
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  defparam rom_harness.memdefaultcontent = 64'h0100000001000000;
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  // RAM has Physical Address range [0x0000040000:0x000004FFFF]
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  // so size is 64 KByte and requires 16 address bits
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  // 3 of which are ignored being a 64-bit memory => addr_bits=13
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  // (it was section RED_EXT_SEC in the official OpenSPARC-T1 testbench)
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  defparam ram_harness.addr_bits = 13;
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  defparam ram_harness.memfilename = "ram_harness.hex";
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  defparam ram_harness.memdefaultcontent = 64'h0100000001000000;
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endmodule

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