1 |
4 |
fafa1971 |
/*
|
2 |
|
|
* Simply RISC S1 Testbench
|
3 |
|
|
*
|
4 |
|
|
* (C) 2007 Simply RISC LLP
|
5 |
|
|
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
|
6 |
|
|
*
|
7 |
|
|
* LICENSE:
|
8 |
|
|
* This is a Free Hardware Design; you can redistribute it and/or
|
9 |
|
|
* modify it under the terms of the GNU General Public License
|
10 |
|
|
* version 2 as published by the Free Software Foundation.
|
11 |
|
|
* The above named program is distributed in the hope that it will
|
12 |
|
|
* be useful, but WITHOUT ANY WARRANTY; without even the implied
|
13 |
|
|
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
14 |
|
|
* See the GNU General Public License for more details.
|
15 |
|
|
*
|
16 |
|
|
* DESCRIPTION:
|
17 |
|
|
* This is the testbench for the functional verification of the
|
18 |
|
|
* S1 Core: it makes and instance of the S1 module to make it
|
19 |
|
|
* possible to access one or more memory harnesses.
|
20 |
|
|
*/
|
21 |
|
|
|
22 |
|
|
`include "s1_defs.h"
|
23 |
|
|
|
24 |
|
|
module testbench ();
|
25 |
|
|
|
26 |
|
|
/*
|
27 |
|
|
* Wires
|
28 |
|
|
*/
|
29 |
|
|
|
30 |
|
|
// Interrupt Requests
|
31 |
|
|
wire[63:0] sys_irq;
|
32 |
|
|
|
33 |
|
|
// Wishbone Master inputs / Wishbone Slave ouputs
|
34 |
|
|
wire wb_ack; // Ack
|
35 |
|
|
wire[(`WB_DATA_WIDTH-1):0] wb_datain; // Data In
|
36 |
|
|
|
37 |
|
|
// Wishbone Master outputs / Wishbone Slave inputs
|
38 |
|
|
wire wb_cycle; // Cycle Start
|
39 |
|
|
wire wb_strobe; // Strobe Request
|
40 |
|
|
wire wb_we_o; // Write Enable
|
41 |
|
|
wire[`WB_ADDR_WIDTH-1:0] wb_addr; // Address Bus
|
42 |
|
|
wire[`WB_DATA_WIDTH-1:0] wb_dataout; // Data Out
|
43 |
|
|
wire[`WB_DATA_WIDTH/8-1:0] wb_sel; // Select Output
|
44 |
|
|
|
45 |
|
|
// Separate Cycle wires for memory harnesses
|
46 |
|
|
wire wb_cycle_RED_EXT_SEC;
|
47 |
|
|
wire wb_cycle_HTRAPS;
|
48 |
|
|
wire wb_cycle_TRAPS;
|
49 |
|
|
wire wb_cycle_HPRIV_RESET;
|
50 |
|
|
wire wb_cycle_KERNEL_text;
|
51 |
|
|
wire wb_cycle_KERNEL_data;
|
52 |
|
|
wire wb_cycle_MAIN;
|
53 |
|
|
wire wb_cycle_RED_SEC;
|
54 |
|
|
|
55 |
|
|
// Separate Strobe wires for memory harnesses
|
56 |
|
|
wire wb_strobe_RED_EXT_SEC;
|
57 |
|
|
wire wb_strobe_HTRAPS;
|
58 |
|
|
wire wb_strobe_TRAPS;
|
59 |
|
|
wire wb_strobe_HPRIV_RESET;
|
60 |
|
|
wire wb_strobe_KERNEL_text;
|
61 |
|
|
wire wb_strobe_KERNEL_data;
|
62 |
|
|
wire wb_strobe_MAIN;
|
63 |
|
|
wire wb_strobe_RED_SEC;
|
64 |
|
|
|
65 |
|
|
// Separate Ack wires for memory harnesses
|
66 |
|
|
wire wb_ack_RED_EXT_SEC;
|
67 |
|
|
wire wb_ack_HTRAPS;
|
68 |
|
|
wire wb_ack_TRAPS;
|
69 |
|
|
wire wb_ack_HPRIV_RESET;
|
70 |
|
|
wire wb_ack_KERNEL_text;
|
71 |
|
|
wire wb_ack_KERNEL_data;
|
72 |
|
|
wire wb_ack_MAIN;
|
73 |
|
|
wire wb_ack_RED_SEC;
|
74 |
|
|
|
75 |
|
|
/*
|
76 |
|
|
* Registers
|
77 |
|
|
*/
|
78 |
|
|
|
79 |
|
|
// System signals
|
80 |
|
|
reg sys_clock;
|
81 |
|
|
reg sys_reset;
|
82 |
|
|
|
83 |
|
|
/*
|
84 |
|
|
* Behavior
|
85 |
|
|
*/
|
86 |
|
|
|
87 |
|
|
always #1 sys_clock = ~sys_clock;
|
88 |
|
|
assign sys_irq = 64'b0;
|
89 |
|
|
|
90 |
|
|
initial begin
|
91 |
|
|
|
92 |
|
|
// Display start message
|
93 |
|
|
$display("INFO: TBENCH: Starting Simply RISC S1 Core simulation...");
|
94 |
|
|
|
95 |
|
|
// Create VCD trace file
|
96 |
|
|
$dumpfile("trace.vcd");
|
97 |
|
|
$dumpvars();
|
98 |
|
|
|
99 |
|
|
// Run the simulation
|
100 |
|
|
sys_clock <= 1'b1;
|
101 |
|
|
sys_reset <= 1'b1;
|
102 |
|
|
#100
|
103 |
|
|
sys_reset <= 1'b0;
|
104 |
|
|
#9900
|
105 |
|
|
$display("INFO: TBENCH: Completed Simply RISC S1 Core simulation!");
|
106 |
|
|
$finish;
|
107 |
|
|
|
108 |
|
|
end
|
109 |
|
|
|
110 |
|
|
/*
|
111 |
|
|
* Simply RISC S1 module instance
|
112 |
|
|
*/
|
113 |
|
|
|
114 |
|
|
s1_top s1_top_0 (
|
115 |
|
|
|
116 |
|
|
// System inputs
|
117 |
|
|
.sys_clock_i(sys_clock),
|
118 |
|
|
.sys_reset_i(sys_reset),
|
119 |
|
|
.sys_irq_i(sys_irq),
|
120 |
|
|
|
121 |
|
|
// Wishbone Master inputs
|
122 |
|
|
.wbm_ack_i(wb_ack),
|
123 |
|
|
.wbm_data_i(wb_datain),
|
124 |
|
|
|
125 |
|
|
// Wishbone Master outputs
|
126 |
|
|
.wbm_cycle_o(wb_cycle),
|
127 |
|
|
.wbm_strobe_o(wb_strobe),
|
128 |
|
|
.wbm_we_o(wb_we),
|
129 |
|
|
.wbm_addr_o(wb_addr),
|
130 |
|
|
.wbm_data_o(wb_dataout),
|
131 |
|
|
.wbm_sel_o(wb_sel)
|
132 |
|
|
|
133 |
|
|
);
|
134 |
|
|
|
135 |
|
|
/*
|
136 |
|
|
* Memory Harnesses with Wishbone Slave interface
|
137 |
|
|
*/
|
138 |
|
|
|
139 |
|
|
// Section '.RED_EXT_SEC', segment 'text' - From PA 0000040000 to 0000047FFF and then together with
|
140 |
|
|
// Section '.RED_EXT_SEC', segment 'data' - From PA 000004C000 to 000004FFFF => 16-3=13 addr_bits
|
141 |
|
|
defparam mem_RED_EXT_SEC.addr_bits = 13;
|
142 |
|
|
defparam mem_RED_EXT_SEC.memfilename = "mem_RED_EXT_SEC.image";
|
143 |
|
|
defparam mem_RED_EXT_SEC.memdefaultcontent = 64'h0100000001000000;
|
144 |
|
|
|
145 |
|
|
// Section '.HTRAPS', segment 'text' - From PA 0000080000 to 0000087FFF and then together with
|
146 |
|
|
// Section '.HTRAPS', segment 'data' - From PA 000008C000 to 000008FFFF (zeroes) => 16-3=13 addr_bits
|
147 |
|
|
defparam mem_HTRAPS.addr_bits = 13;
|
148 |
|
|
defparam mem_HTRAPS.memfilename = "mem_HTRAPS.image";
|
149 |
|
|
defparam mem_HTRAPS.memdefaultcontent = 64'h0100000001000000;
|
150 |
|
|
|
151 |
|
|
// Section '.TRAPS', segment 'text' - From PA 1000120000 to 1000127FFF and then together with
|
152 |
|
|
// Section '.TRAPS', segment 'data' - From PA 100012C000 to 100012FFFF (zeroes) => 16-3=13 addr_bits
|
153 |
|
|
defparam mem_TRAPS.addr_bits = 13;
|
154 |
|
|
defparam mem_TRAPS.memfilename = "mem_TRAPS.image";
|
155 |
|
|
defparam mem_TRAPS.memdefaultcontent = 64'h0100000001000000;
|
156 |
|
|
|
157 |
|
|
// Section '.HPRIV_RESET', segment 'text' - From PA 1000144000 to 1000144FFF => 12-3=9 addr_bits
|
158 |
|
|
defparam mem_HPRIV_RESET.addr_bits = 9;
|
159 |
|
|
defparam mem_HPRIV_RESET.memfilename = "mem_HPRIV_RESET.image";
|
160 |
|
|
defparam mem_HPRIV_RESET.memdefaultcontent = 64'h0100000001000000;
|
161 |
|
|
|
162 |
|
|
// Section '.KERNEL', segment 'text' - From PA 1101834000 to 1101834FFF => 12-3=9 addr_bits
|
163 |
|
|
defparam mem_KERNEL_text.addr_bits = 9;
|
164 |
|
|
defparam mem_KERNEL_text.memfilename = "mem_KERNEL_text.image";
|
165 |
|
|
defparam mem_KERNEL_text.memdefaultcontent = 64'h0100000001000000;
|
166 |
|
|
|
167 |
|
|
// Section '.KERNEL', segment 'data' - From PA 1101C34000 to 1101C34FFF => 12-3=9 addr_bits
|
168 |
|
|
defparam mem_KERNEL_data.addr_bits = 9;
|
169 |
|
|
defparam mem_KERNEL_data.memfilename = "mem_KERNEL_data.image";
|
170 |
|
|
defparam mem_KERNEL_data.memdefaultcontent = 64'h0000000000000000;
|
171 |
|
|
|
172 |
|
|
// Section '.MAIN', segment 'text' - From PA 1130000000 to 113000FFFF => 16-3=13 addr_bits
|
173 |
|
|
// Section '.MAIN', segment 'data' - From PA 1170000000 but should be empty
|
174 |
|
|
// Section '.USER_HEAP', segment 'data' - From PA 1178020000 but should be empty
|
175 |
|
|
// Section '.MAIN', segment 'bss' - From PA 1178030000 but should be empty
|
176 |
|
|
defparam mem_MAIN.addr_bits = 13;
|
177 |
|
|
defparam mem_MAIN.memfilename = "mem_MAIN.image";
|
178 |
|
|
defparam mem_MAIN.memdefaultcontent = 64'h0100000001000000;
|
179 |
|
|
|
180 |
|
|
// Section '.RED_SEC', segment 'text' - From PA FFF0000000 to FFF0000FFF => 12-3=9 addr_bits
|
181 |
|
|
// Section '.RED_SEC', segment 'data' - From PA FFF0010000 but should contain only an unused word
|
182 |
|
|
defparam mem_RED_SEC.addr_bits = 9;
|
183 |
|
|
defparam mem_RED_SEC.memfilename = "mem_RED_SEC.image";
|
184 |
|
|
defparam mem_RED_SEC.memdefaultcontent = 64'h0100000001000000;
|
185 |
|
|
|
186 |
|
|
// Decode the address and select the proper memory bank
|
187 |
|
|
|
188 |
|
|
assign wb_cycle_RED_EXT_SEC = ( (wb_addr[39:16]==24'h000004) ? wb_cycle : 0 );
|
189 |
|
|
assign wb_strobe_RED_EXT_SEC = ( (wb_addr[39:16]==24'h000004) ? wb_strobe : 0 );
|
190 |
|
|
|
191 |
|
|
assign wb_cycle_HTRAPS = ( (wb_addr[39:16]==24'h000008) ? wb_cycle : 0 );
|
192 |
|
|
assign wb_strobe_HTRAPS = ( (wb_addr[39:16]==24'h000008) ? wb_strobe : 0 );
|
193 |
|
|
|
194 |
|
|
assign wb_cycle_TRAPS = ( (wb_addr[39:16]==24'h100012) ? wb_cycle : 0 );
|
195 |
|
|
assign wb_strobe_TRAPS = ( (wb_addr[39:16]==24'h100012) ? wb_strobe : 0 );
|
196 |
|
|
|
197 |
|
|
assign wb_cycle_HPRIV_RESET = ( (wb_addr[39:12]==28'h1000144) ? wb_cycle : 0 );
|
198 |
|
|
assign wb_strobe_HPRIV_RESET = ( (wb_addr[39:12]==28'h1000144) ? wb_strobe : 0 );
|
199 |
|
|
|
200 |
|
|
assign wb_cycle_KERNEL_text = ( (wb_addr[39:12]==28'h1101834) ? wb_cycle : 0 );
|
201 |
|
|
assign wb_strobe_KERNEL_text = ( (wb_addr[39:12]==28'h1101834) ? wb_strobe : 0 );
|
202 |
|
|
|
203 |
|
|
assign wb_cycle_KERNEL_data = ( (wb_addr[39:12]==28'h1101C34) ? wb_cycle : 0 );
|
204 |
|
|
assign wb_strobe_KERNEL_data = ( (wb_addr[39:12]==28'h1101C34) ? wb_strobe : 0 );
|
205 |
|
|
|
206 |
|
|
assign wb_cycle_MAIN = ( (wb_addr[39:16]==24'h113000) ? wb_cycle : 0 );
|
207 |
|
|
assign wb_strobe_MAIN = ( (wb_addr[39:16]==24'h113000) ? wb_strobe : 0 );
|
208 |
|
|
|
209 |
|
|
assign wb_cycle_RED_SEC = ( (wb_addr[39:12]==28'hFFF0000) ? wb_cycle : 0 );
|
210 |
|
|
assign wb_strobe_RED_SEC = ( (wb_addr[39:12]==28'hFFF0000) ? wb_strobe : 0 );
|
211 |
|
|
|
212 |
|
|
assign wb_ack = wb_ack_RED_EXT_SEC | wb_ack_HTRAPS | wb_ack_TRAPS | wb_ack_HPRIV_RESET |
|
213 |
|
|
wb_ack_KERNEL_text | wb_ack_KERNEL_data | wb_ack_MAIN | wb_ack_RED_SEC;
|
214 |
|
|
|
215 |
|
|
mem_harness mem_RED_EXT_SEC (
|
216 |
|
|
|
217 |
|
|
// System inputs
|
218 |
|
|
.sys_clock_i(sys_clock),
|
219 |
|
|
.sys_reset_i(sys_reset),
|
220 |
|
|
|
221 |
|
|
// Wishbone Slave inputs
|
222 |
|
|
.wbs_addr_i(wb_addr),
|
223 |
|
|
.wbs_data_i(wb_dataout),
|
224 |
|
|
.wbs_cycle_i(wb_cycle_RED_EXT_SEC),
|
225 |
|
|
.wbs_strobe_i(wb_strobe_RED_EXT_SEC),
|
226 |
|
|
.wbs_sel_i(wb_sel),
|
227 |
|
|
.wbs_we_i(wb_we),
|
228 |
|
|
|
229 |
|
|
// Wishbone Slave outputs
|
230 |
|
|
.wbs_data_o(wb_datain),
|
231 |
|
|
.wbs_ack_o(wb_ack_RED_EXT_SEC)
|
232 |
|
|
|
233 |
|
|
);
|
234 |
|
|
|
235 |
|
|
mem_harness mem_HTRAPS (
|
236 |
|
|
|
237 |
|
|
// System inputs
|
238 |
|
|
.sys_clock_i(sys_clock),
|
239 |
|
|
.sys_reset_i(sys_reset),
|
240 |
|
|
|
241 |
|
|
// Wishbone Slave inputs
|
242 |
|
|
.wbs_addr_i(wb_addr),
|
243 |
|
|
.wbs_data_i(wb_dataout),
|
244 |
|
|
.wbs_cycle_i(wb_cycle_HTRAPS),
|
245 |
|
|
.wbs_strobe_i(wb_strobe_HTRAPS),
|
246 |
|
|
.wbs_sel_i(wb_sel),
|
247 |
|
|
.wbs_we_i(wb_we),
|
248 |
|
|
|
249 |
|
|
// Wishbone Slave outputs
|
250 |
|
|
.wbs_data_o(wb_datain),
|
251 |
|
|
.wbs_ack_o(wb_ack_HTRAPS)
|
252 |
|
|
|
253 |
|
|
);
|
254 |
|
|
|
255 |
|
|
mem_harness mem_TRAPS (
|
256 |
|
|
|
257 |
|
|
// System inputs
|
258 |
|
|
.sys_clock_i(sys_clock),
|
259 |
|
|
.sys_reset_i(sys_reset),
|
260 |
|
|
|
261 |
|
|
// Wishbone Slave inputs
|
262 |
|
|
.wbs_addr_i(wb_addr),
|
263 |
|
|
.wbs_data_i(wb_dataout),
|
264 |
|
|
.wbs_cycle_i(wb_cycle_TRAPS),
|
265 |
|
|
.wbs_strobe_i(wb_strobe_TRAPS),
|
266 |
|
|
.wbs_sel_i(wb_sel),
|
267 |
|
|
.wbs_we_i(wb_we),
|
268 |
|
|
|
269 |
|
|
// Wishbone Slave outputs
|
270 |
|
|
.wbs_data_o(wb_datain),
|
271 |
|
|
.wbs_ack_o(wb_ack_TRAPS)
|
272 |
|
|
|
273 |
|
|
);
|
274 |
|
|
|
275 |
|
|
mem_harness mem_HPRIV_RESET (
|
276 |
|
|
|
277 |
|
|
// System inputs
|
278 |
|
|
.sys_clock_i(sys_clock),
|
279 |
|
|
.sys_reset_i(sys_reset),
|
280 |
|
|
|
281 |
|
|
// Wishbone Slave inputs
|
282 |
|
|
.wbs_addr_i(wb_addr),
|
283 |
|
|
.wbs_data_i(wb_dataout),
|
284 |
|
|
.wbs_cycle_i(wb_cycle_HPRIV_RESET),
|
285 |
|
|
.wbs_strobe_i(wb_strobe_HPRIV_RESET),
|
286 |
|
|
.wbs_sel_i(wb_sel),
|
287 |
|
|
.wbs_we_i(wb_we),
|
288 |
|
|
|
289 |
|
|
// Wishbone Slave outputs
|
290 |
|
|
.wbs_data_o(wb_datain),
|
291 |
|
|
.wbs_ack_o(wb_ack_HPRIV_RESET)
|
292 |
|
|
|
293 |
|
|
);
|
294 |
|
|
|
295 |
|
|
mem_harness mem_KERNEL_text (
|
296 |
|
|
|
297 |
|
|
// System inputs
|
298 |
|
|
.sys_clock_i(sys_clock),
|
299 |
|
|
.sys_reset_i(sys_reset),
|
300 |
|
|
|
301 |
|
|
// Wishbone Slave inputs
|
302 |
|
|
.wbs_addr_i(wb_addr),
|
303 |
|
|
.wbs_data_i(wb_dataout),
|
304 |
|
|
.wbs_cycle_i(wb_cycle_KERNEL_text),
|
305 |
|
|
.wbs_strobe_i(wb_strobe_KERNEL_text),
|
306 |
|
|
.wbs_sel_i(wb_sel),
|
307 |
|
|
.wbs_we_i(wb_we),
|
308 |
|
|
|
309 |
|
|
// Wishbone Slave outputs
|
310 |
|
|
.wbs_data_o(wb_datain),
|
311 |
|
|
.wbs_ack_o(wb_ack_KERNEL_text)
|
312 |
|
|
|
313 |
|
|
);
|
314 |
|
|
|
315 |
|
|
mem_harness mem_KERNEL_data (
|
316 |
|
|
|
317 |
|
|
// System inputs
|
318 |
|
|
.sys_clock_i(sys_clock),
|
319 |
|
|
.sys_reset_i(sys_reset),
|
320 |
|
|
|
321 |
|
|
// Wishbone Slave inputs
|
322 |
|
|
.wbs_addr_i(wb_addr),
|
323 |
|
|
.wbs_data_i(wb_dataout),
|
324 |
|
|
.wbs_cycle_i(wb_cycle_KERNEL_data),
|
325 |
|
|
.wbs_strobe_i(wb_strobe_KERNEL_data),
|
326 |
|
|
.wbs_sel_i(wb_sel),
|
327 |
|
|
.wbs_we_i(wb_we),
|
328 |
|
|
|
329 |
|
|
// Wishbone Slave outputs
|
330 |
|
|
.wbs_data_o(wb_datain),
|
331 |
|
|
.wbs_ack_o(wb_ack_KERNEL_data)
|
332 |
|
|
|
333 |
|
|
);
|
334 |
|
|
|
335 |
|
|
mem_harness mem_MAIN (
|
336 |
|
|
|
337 |
|
|
// System inputs
|
338 |
|
|
.sys_clock_i(sys_clock),
|
339 |
|
|
.sys_reset_i(sys_reset),
|
340 |
|
|
|
341 |
|
|
// Wishbone Slave inputs
|
342 |
|
|
.wbs_addr_i(wb_addr),
|
343 |
|
|
.wbs_data_i(wb_dataout),
|
344 |
|
|
.wbs_cycle_i(wb_cycle_MAIN),
|
345 |
|
|
.wbs_strobe_i(wb_strobe_MAIN),
|
346 |
|
|
.wbs_sel_i(wb_sel),
|
347 |
|
|
.wbs_we_i(wb_we),
|
348 |
|
|
|
349 |
|
|
// Wishbone Slave outputs
|
350 |
|
|
.wbs_data_o(wb_datain),
|
351 |
|
|
.wbs_ack_o(wb_ack_MAIN)
|
352 |
|
|
|
353 |
|
|
);
|
354 |
|
|
|
355 |
|
|
mem_harness mem_RED_SEC (
|
356 |
|
|
|
357 |
|
|
// System inputs
|
358 |
|
|
.sys_clock_i(sys_clock),
|
359 |
|
|
.sys_reset_i(sys_reset),
|
360 |
|
|
|
361 |
|
|
// Wishbone Slave inputs
|
362 |
|
|
.wbs_addr_i(wb_addr),
|
363 |
|
|
.wbs_data_i(wb_dataout),
|
364 |
|
|
.wbs_cycle_i(wb_cycle_RED_SEC),
|
365 |
|
|
.wbs_strobe_i(wb_strobe_RED_SEC),
|
366 |
|
|
.wbs_sel_i(wb_sel),
|
367 |
|
|
.wbs_we_i(wb_we),
|
368 |
|
|
|
369 |
|
|
// Wishbone Slave outputs
|
370 |
|
|
.wbs_data_o(wb_datain),
|
371 |
|
|
.wbs_ack_o(wb_ack_RED_SEC)
|
372 |
|
|
|
373 |
|
|
);
|
374 |
|
|
|
375 |
|
|
endmodule
|