OpenCores
URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [hdl/] [filelist.dc] - Blame information for rev 112

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 111 albert.wat 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/sparc_libs/u1_lib.v
2 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/sparc_libs/m1_lib.v
3 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluor32.v
4 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
5 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
6 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_tcl.v
7 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cluster_header.v
8 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/test_stub_bist.v
9 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_tlbdp.v
10 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_mbist.v
11 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu.v
12 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_intctl.v
13 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_incr64.v
14 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_tlb.v
15 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_mmu_ctl.v
16 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_dec.v
17 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
18 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
19 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_irf.v
20 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_misctl.v
21 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/mul64.v
22 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_fdp.v
23 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_intdp.v
24 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_scm.v
25 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_top.v
26 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_tdp.v
27 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_incr46.v
28 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qctl1.v
29 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
30 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/swrvr_clib.v
31 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
32 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
33 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_asi_decode.v
34 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_errdp.v
35 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cpx_spc_buf.v
36 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_dcd.v
37 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_pcx_qmon.v
38 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
39 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_cntl.v
40 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_dcl.v
41 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_frf.v
42 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf32x80.v
43 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/synchronizer_asr.v
44 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
45 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_swpla.v
46 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_shft.v
47 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/swrvr_dlib.v
48 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_ctl.v
49 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
50 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_excpctl.v
51 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
52 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
53 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rndrob.v
54 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu.v
55 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
56 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
57 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par34.v
58 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alulogic.v
59 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf16x32.v
60 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl.v
61 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qctl2.v
62 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_pib.v
63 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_tagdp.v
64 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
65 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_mmu_dp.v
66 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_dec64.v
67 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecc.v
68 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dctldp.v
69 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_reg.v
70 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_icd.v
71 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qdp2.v
72 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_vis.v
73 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf16x160.v
74 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_byp.v
75 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
76 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
77 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par16.v
78 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf32x152b.v
79 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
80 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par32.v
81 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
82 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
83 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/test_stub_scan.v
84 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_dp.v
85 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dctl.v
86 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_fcl.v
87 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_invctl.v
88 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qdp1.v
89 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_rrobin_picker.v
90 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_lru4.v
91 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
92 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
93 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_sscan.v
94 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu.v
95 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
96 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
97 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
98 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
99 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_idct.v
100 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_swl.v
101 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cmp_sram_redhdr.v
102 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_dp.v
103 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_rwctl.v
104 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cpx_spc_rpt.v
105 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu.v
106 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_penc64.v
107 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
108 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_prencoder16.v
109 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_rwdp.v
110 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_hyperv.v
111 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_irf_register.v
112 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div.v
113 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
114 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
115 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
116 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml.v
117 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
118 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
119 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu.v
120 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_errctl.v
121 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
122 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclccr.v
123 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_addern_32.v
124 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
125 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_imd.v
126 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_ctl.v
127 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
128 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluspr.v
129 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc.v
130 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_ctldp.v
131 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alu.v
132 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dcdp.v
133 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/rst_ctrl.v
134 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/int_ctrl.v
135 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/spc2wbm.v
136 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/s1_top.v
137 81 fafa1971 
 
138 74 fafa1971 
# The Tcl script under $S1_ROOT/tools/src/build_dc.cmd is attached at the end of the filelist for DC;
139 
# if you modify this file *REMEMBER* to run 'update_filelist' or you'll run the old version!!!
140 3 fafa1971 
 
141 91 fafa1971 
# Variables setting
142 82 fafa1971 
 
143 91 fafa1971 
set sub_modules {sparc_ifu lsu sparc_exu sparc_ffu sparc_mul_top spu tlu s1_top}
144 
set sub_clocks  {rclk clk sys_clock_i}
145 
set sub_resets  {grst_l arst_l sys_reset_i}
146 3 fafa1971 
 
147 91 fafa1971 
foreach active_design $sub_modules {
148 3 fafa1971 
 
149 91 fafa1971 
  # Technology-independent elaboration and linking
150 
  elaborate      $active_design
151 
  current_design $active_design
152 
  link
153 
  uniquify -dont_skip_empty_designs
154 74 fafa1971 
 
155 91 fafa1971 
  # Set constraints and mapping on target library
156 
  create_clock -period 5.0 -waveform [list 0 2.5] [get_ports $sub_clocks]
157 
  set_input_delay  1.8 -clock [get_clocks $sub_clocks] -max [all_inputs]
158 
  set_output_delay 1.2 -clock [get_clocks $sub_clocks] -max [all_outputs]
159 
  set_dont_touch_network [concat $sub_clocks $sub_resets]
160 
  set_drive    0         [concat $sub_clocks $sub_resets]
161 
  set_max_area 0
162 
  set_wire_load_mode enclosed
163 
  set_fix_multiple_port_nets -buffer_constants -all
164 
  compile
165 74 fafa1971 
 
166 91 fafa1971 
  # Export the mapped design
167 
  remove_unconnected_ports [find -hierarchy cell {"*"}]
168 
  set_dont_touch current_design
169 
  write -format ddc -hierarchy -output $active_design.ddc
170 
  write -format verilog -hierarchy -output $active_design.sv
171 74 fafa1971 
 
172 91 fafa1971 
  # Report area and timing
173 
  report_area -hierarchy > report_${active_design}_area.rpt
174 
  report_timing > report_${active_design}_timing.rpt
175 
  report_constraint -all_violators > report_${active_design}_constraint.rpt
176 74 fafa1971 
 
177 91 fafa1971 
}
178 3 fafa1971 
 
179 
quit
180 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.