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[/] [s1_core/] [trunk/] [hdl/] [filelist.dc] - Blame information for rev 3

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Line No. Rev Author Line
1 3 fafa1971 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/macrocell/sparc_libs/u1_lib.v
2 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/macrocell/sparc_libs/m1_lib.v
3 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40b.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcd.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcm.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_efa.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_frf.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_icd.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_idct.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_irf.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_32k.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_bot.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_top.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x128d.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x160.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x32.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x108.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x152b.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x80.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_scm.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_tlb.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x65.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x81.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_48x.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_64x.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_128x.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_48x.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_64x.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_96x.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_scanlasr_2x.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_sync.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_center_3inv.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_192x.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_224x.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_288x.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_192x.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_224x.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_256x.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_sctag_3inv.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_fdbk.v
44 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_hz.v
45 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_rstce_rtl.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_vrt_all.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa0.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa1.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb0.v
50 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb1.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb2.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb3.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc0.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc1.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc2.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc3.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc4.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc5.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc6.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc7.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rng.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_ctu.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_dup.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_sync.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cmp_sram_redhdr.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/dbl_buf.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_clib.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_dlib.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sync_pulse_synchronizer.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_bist.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr_dup.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_scan.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_in.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_out.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_2buf.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_jbi.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_spi.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_noflow.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/mul64.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alulogic.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluor32.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluspr.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclccr.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_reg.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rndrob.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_shft.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_ctl.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_dp.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_vis.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_dcl.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_dec.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_errctl.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_errdp.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_fcl.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_fdp.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_imd.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_incr46.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_invctl.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
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analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_lru4.v
136 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_mbist.v
137 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
138 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par16.v
139 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par32.v
140 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par34.v
141 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
142 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_sscan.v
143 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_swl.v
144 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_swpla.v
145 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
146 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
147 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
148 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu.v
149 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_asi_decode.v
150 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
151 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
152 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dcdp.v
153 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dctl.v
154 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dctldp.v
155 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_excpctl.v
156 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_pcx_qmon.v
157 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qctl1.v
158 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qctl2.v
159 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qdp1.v
160 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qdp2.v
161 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
162 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_ctl.v
163 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_ctldp.v
164 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_rwctl.v
165 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_rwdp.v
166 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_tagdp.v
167 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_tlbdp.v
168 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_cntl.v
169 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_dp.v
170 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_top.v
171 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
172 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cpx_spc_buf.v
173 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cpx_spc_rpt.v
174 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc.v
175 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spc_pcx_buf.v
176 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu.v
177 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_ctl.v
178 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_lsurpt.v
179 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_lsurpt1.v
180 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maaddr.v
181 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maaeqb.v
182 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mactl.v
183 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_madp.v
184 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maexp.v
185 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mald.v
186 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mamul.v
187 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mared.v
188 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mast.v
189 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_wen.v
190 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_dec64.v
191 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_intctl.v
192 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_intdp.v
193 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_penc64.v
194 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
195 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu.v
196 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_addern_32.v
197 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_hyperv.v
198 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_incr64.v
199 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_misctl.v
200 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_mmu_ctl.v
201 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_mmu_dp.v
202 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_pib.v
203 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_prencoder16.v
204 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_rrobin_picker.v
205 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_tcl.v
206 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_tdp.v
207 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/s1_top/rst_ctrl.v
208 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/s1_top/int_ctrl.v
209 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/s1_top/spc2wbm.v
210 
analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/s1_top/s1_top.v
211 
 
212 
/* If you modify this file remember to run update_filelist so that filelist.dc gets updated!!! */
213 
 
214 
elaborate s1_top
215 
link
216 
uniquify
217 
/* check_design */
218 
 
219 
create_clock -period 2.0 -name sys_clock_i find(port, "sys_clock_i")
220 
set_input_delay  1 -max -clock sys_clock_i all_inputs() - find(port, "sys_clock_i")
221 
set_output_delay 1 -max -clock sys_clock_i all_outputs()
222 
 
223 
compile -map_effort high
224 
 
225 
write -format db -hierarchy -output s1_top.db
226 
write -format verilog -hierarchy -output s1_top.v
227 
 
228 
report_area > report_area.txt
229 
report_timing > report_timing.txt
230 
report_constraint -all_violators > report_constraint.txt
231 
 
232 
quit
233 
 

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