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[/] [s1_core/] [trunk/] [hdl/] [filelist.dc] - Blame information for rev 91

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Line No. Rev Author Line
1 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/behav/sparc_libs/u1_lib.v
2 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/behav/sparc_libs/m1_lib.v
3 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
4 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
5 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
6 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mared.v
7 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
8 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
9 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
10 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
11 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
12 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
13 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
14 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
15 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
16 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
17 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
18 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
19 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
20 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_madp.v
21 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
22 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
23 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
24 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
25 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
26 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
27 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
28 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
29 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
30 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
31 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
32 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
33 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
34 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_maexp.v
35 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
36 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
37 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
38 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
39 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
40 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
41 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt.v
42 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_pib.v
43 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
44 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mald.v
45 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_maaddr.v
46 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_maaeqb.v
47 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
48 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt1.v
49 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
50 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
51 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
52 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
53 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
54 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
55 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
56 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
57 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
58 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
59 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
60 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_wen.v
61 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
62 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
63 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
64 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
65 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
66 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
67 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
68 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
69 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu.v
70 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
71 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
72 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
73 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
74 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
75 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
76 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
77 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mast.v
78 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
79 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
80 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_ctl.v
81 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
82 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
83 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
84 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
85 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
86 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
87 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
88 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
89 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
90 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
91 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
92 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
93 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
94 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
95 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
96 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
97 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
98 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
99 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
100 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
101 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mamul.v
102 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
103 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
104 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
105 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
106 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
107 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
108 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
109 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
110 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
111 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
112 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
113 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
114 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
115 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
116 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
117 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
118 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu.v
119 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
120 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
121 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
122 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
123 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
124 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
125 91 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
126 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
127 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu.v
128 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu.v
129 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
130 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
131 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
132 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
133 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
134 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/mul64.v
135 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
136 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc.v
137 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
138 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
139 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cluster_header.v
140 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
141 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
142 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
143 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
144 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
145 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mactl.v
146 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
147 81 fafa1971 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/rst_ctrl.v
148 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/int_ctrl.v
149 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/spc2wbm.v
150 
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/s1_top.v
151 
 
152 74 fafa1971 
# The Tcl script under $S1_ROOT/tools/src/build_dc.cmd is attached at the end of the filelist for DC;
153 
# if you modify this file *REMEMBER* to run 'update_filelist' or you'll run the old version!!!
154 3 fafa1971 
 
155 91 fafa1971 
# Variables setting
156 82 fafa1971 
 
157 91 fafa1971 
set sub_modules {sparc_ifu lsu sparc_exu sparc_ffu sparc_mul_top spu tlu s1_top}
158 
set sub_clocks  {rclk clk sys_clock_i}
159 
set sub_resets  {grst_l arst_l sys_reset_i}
160 3 fafa1971 
 
161 91 fafa1971 
foreach active_design $sub_modules {
162 3 fafa1971 
 
163 91 fafa1971 
  # Technology-independent elaboration and linking
164 
  elaborate      $active_design
165 
  current_design $active_design
166 
  link
167 
  uniquify -dont_skip_empty_designs
168 74 fafa1971 
 
169 91 fafa1971 
  # Set constraints and mapping on target library
170 
  create_clock -period 5.0 -waveform [list 0 2.5] [get_ports $sub_clocks]
171 
  set_input_delay  1.8 -clock [get_clocks $sub_clocks] -max [all_inputs]
172 
  set_output_delay 1.2 -clock [get_clocks $sub_clocks] -max [all_outputs]
173 
  set_dont_touch_network [concat $sub_clocks $sub_resets]
174 
  set_drive    0         [concat $sub_clocks $sub_resets]
175 
  set_max_area 0
176 
  set_wire_load_mode enclosed
177 
  set_fix_multiple_port_nets -buffer_constants -all
178 
  compile
179 74 fafa1971 
 
180 91 fafa1971 
  # Export the mapped design
181 
  remove_unconnected_ports [find -hierarchy cell {"*"}]
182 
  set_dont_touch current_design
183 
  write -format ddc -hierarchy -output $active_design.ddc
184 
  write -format verilog -hierarchy -output $active_design.sv
185 74 fafa1971 
 
186 91 fafa1971 
  # Report area and timing
187 
  report_area -hierarchy > report_${active_design}_area.rpt
188 
  report_timing > report_${active_design}_timing.rpt
189 
  report_constraint -all_violators > report_${active_design}_constraint.rpt
190 74 fafa1971 
 
191 91 fafa1971 
}
192 3 fafa1971 
 
193 
quit
194 
 

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