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[/] [s1_core/] [trunk/] [hdl/] [filelist.xst] - Blame information for rev 96

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Line No. Rev Author Line
1 96 fafa1971
verilog work /home/ffazzino/s1_core/hdl/behav/sparc_libs/m1_lib.v
2
verilog work /home/ffazzino/s1_core/hdl/behav/sparc_libs/u1_lib.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
10
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
11
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
19
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
20
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
35
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu.v
36
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
40
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/mul64.v
42
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
46
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
47
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
48
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
58
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
59
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
60
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
62
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
63
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
64
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
68
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
69
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
70
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
71
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
72
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
74
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
75
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
77
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
80
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
81
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
82
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
85
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu.v
87
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
88
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
89
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
90
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
91
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/cluster_header.v
96
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc.v
98
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
99
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
100
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
101
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
102
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
103
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
104
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
105
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
106
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
107
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
108
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
109
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
110
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
111
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
112
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
113
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu.v
114
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_pib.v
115
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
116
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
117
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
118
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
119
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
120
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
121
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
122
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
123
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
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verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
125
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
126
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
127
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
128
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
129
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
130
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
131
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
132
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
133
verilog work /home/ffazzino/s1_core/hdl/rtl/s1_top/rst_ctrl.v
134
verilog work /home/ffazzino/s1_core/hdl/rtl/s1_top/int_ctrl.v
135
verilog work /home/ffazzino/s1_core/hdl/rtl/s1_top/spc2wbm.v
136
verilog work /home/ffazzino/s1_core/hdl/rtl/s1_top/s1_top.v

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