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albert.wat |
/*
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* Simply RISC PCX FIFO
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*
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* (C) Copyleft 2007 Simply RISC LLP
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* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
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*
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* LICENSE:
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* This is a Free Hardware Design; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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* The above named program is distributed in the hope that it will
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* be useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* DESCRIPTION:
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* Replica of the 'pcx_fifo' module used by Dmitry for his advanced
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* bridge, the original one was from an Altera SCFIFO Megafunction.
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*/
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`timescale 1ns/100ps
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`define PCX_FIFO_DATA_WIDTH 130
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module pcx_fifo(
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// System
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input aclr, // Async Clear (resets the FIFO to empty)
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input clock, // Clock
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// FIFO
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input rdreq, // Read Request (when not empty)
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input wrreq, // Write Request (when not full)
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input [(`PCX_FIFO_DATA_WIDTH-1):0] data, // Data Input
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output empty, // FIFO is empty
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output full, // FIFO is full
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output reg [(`PCX_FIFO_DATA_WIDTH-1):0] q // Data Output (oldest data when Read Request)
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);
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// Local Params TODO CHECKME
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localparam fifo_depth = 32; // TODO Dmitry says this should be enough, put an assertion to detect overflow
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localparam pointer_width = 6; // 5 bits to address 32 elements + 1 to detect wrapping
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// Read/Write Pointers
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logic [(pointer_width-1):0] rd_ptr;
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logic [(pointer_width-1):0] wr_ptr;
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// Memory Array
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logic [(`PCX_FIFO_DATA_WIDTH-1):0] mem[fifo_depth];
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`ifdef SIMPLY_RISC_DEBUG
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// For debugging
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logic printed_once = 0;
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`endif
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// One-process style for reset/read/write
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always @(posedge clock) begin
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// Reset
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if (aclr) begin
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`ifdef SIMPLY_RISC_DEBUG
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if (!printed_once) begin
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$display("PCX FIFO Asynchronous Clear");
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printed_once = 1;
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end
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`endif
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rd_ptr = {pointer_width{1'b0}};
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wr_ptr = {pointer_width{1'b0}};
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end else begin
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// Read
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if (rdreq) begin
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`ifdef SIMPLY_RISC_DEBUG
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if (empty) $fatal(1, "*** ERROR *** Attempt to read PCX FIFO whilst empty");
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$display("PCX FIFO Read Request: rd_ptr=%0d, data=0x%032X", rd_ptr, mem[rd_ptr]);
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`endif
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q <= mem[rd_ptr];
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rd_ptr <= rd_ptr + 1;
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end
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// Write
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if (wrreq) begin
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`ifdef SIMPLY_RISC_DEBUG
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if (full) $fatal(1, "*** ERROR *** Attempt to write PCX FIFO whilst full");
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$display("PCX FIFO Write Request: wr_ptr=%0d, data=0x%032X", wr_ptr, data);
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`endif
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mem[wr_ptr] <= data;
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wr_ptr <= wr_ptr + 1;
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end
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end
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end // always @ (posedge clock)
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// FIFO status flags
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assign empty = (rd_ptr == wr_ptr);
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assign full = ((rd_ptr[pointer_width-2:0] == wr_ptr[pointer_width-2:0]) && (rd_ptr[pointer_width-1] != wr_ptr[pointer_width-1]));
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endmodule // pcx_fifo
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