OpenCores
URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [hdl/] [rtl/] [s1_top/] [rst_ctrl.v] - Blame information for rev 4

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 fafa1971 
/*
2 
 * Reset Controller
3 
 *
4 
 * (C) Copyleft 2007 Simply RISC LLP
5 
 * AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
6 
 *
7 
 * LICENSE:
8 
 * This is a Free Hardware Design; you can redistribute it and/or
9 
 * modify it under the terms of the GNU General Public License
10 
 * version 2 as published by the Free Software Foundation.
11 
 * The above named program is distributed in the hope that it will
12 
 * be useful, but WITHOUT ANY WARRANTY; without even the implied
13 
 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 
 * See the GNU General Public License for more details.
15 
 *
16 
 * DESCRIPTION:
17 
 * This block implements the Reset Controller used by the S1 Core
18 
 * to wake up the SPARC Core of the OpenSPARC T1; its behavior was
19 
 * reverse-engineered from the OpenSPARC waveforms.
20 
 */
21 
 
22 
`include "s1_defs.h"
23 
 
24 
module rst_ctrl (
25 
    sys_clock_i, sys_reset_i,
26 
    cluster_cken_o, gclk_o, cmp_grst_o, cmp_arst_o,
27 
    ctu_tst_pre_grst_o, adbginit_o, gdbginit_o,
28 
    sys_reset_final_o
29 
  );
30 
 
31 
  /*
32 
   * Inputs
33 
   */
34 
 
35 
  // System inputs
36 
  input sys_clock_i;                            // System Clock
37 
  input sys_reset_i;                            // System Reset
38 
 
39 
  /*
40 
   * Registered Outputs
41 
   */
42 
 
43 
  output gclk_o;
44 
 
45 
  /*
46 
   * Registered Outputs
47 
   */
48 
 
49 
  // SPARC Core inputs
50 
  output cluster_cken_o;
51 
  reg cluster_cken_o;
52 
  output cmp_grst_o;
53 
  reg cmp_grst_o;
54 
  output cmp_arst_o;
55 
  reg cmp_arst_o;
56 
  output ctu_tst_pre_grst_o;
57 
  reg ctu_tst_pre_grst_o;
58 
  output adbginit_o;
59 
  reg adbginit_o;
60 
  output gdbginit_o;
61 
  reg gdbginit_o;
62 
  output sys_reset_final_o;
63 
  reg sys_reset_final_o;
64 
 
65 
  /*
66 
   * Registers
67 
   */
68 
 
69 
  // Counter used as a timer to strobe the reset signals
70 
  reg[`TIMER_BITS-1:0] cycle_counter;
71 
 
72 
  /*
73 
   * Procedural blocks
74 
   */
75 
 
76 
  // This process handles the timer counter
77 
  always @(posedge sys_clock_i)
78 
  begin
79 
    if(sys_reset_i==1'b1)
80 
    begin
81 
      cycle_counter = 0;
82 
    end
83 
    else
84 
    begin
85 
      if(cycle_counter[`TIMER_BITS-1]==1'b0)
86 
      begin
87 
        cycle_counter = cycle_counter+1;
88 
      end
89 
    end
90 
  end
91 
 
92 
  // This other process assigns the proper values to the outputs
93 
  // (that are used as system inputs by the SPARC Core)
94 
  always @(posedge sys_clock_i)
95 
  begin
96 
    if(sys_reset_i==1)
97 
    begin
98 
      cluster_cken_o <= 0;
99 
      cmp_grst_o <= 0;
100 
      cmp_arst_o <= 0;
101 
      ctu_tst_pre_grst_o <= 0;
102 
      adbginit_o <= 0;
103 
      gdbginit_o <= 0;
104 
      sys_reset_final_o <= 1;
105 
    end
106 
    else
107 
    begin
108 
      if(cycle_counter<`RESET_CYCLES_1)
109 
      begin
110 
        cluster_cken_o <= 0;
111 
        cmp_grst_o <= 0;
112 
        cmp_arst_o <= 0;
113 
        ctu_tst_pre_grst_o <= 0;
114 
        adbginit_o <= 0;
115 
        gdbginit_o <= 0;
116 
        sys_reset_final_o <= 1;
117 
      end
118 
      else
119 
      if(cycle_counter<`RESET_CYCLES_2)
120 
      begin
121 
        cluster_cken_o <= 0;
122 
        cmp_grst_o <= 0;
123 
        cmp_arst_o <= 1;  // <--
124 
        ctu_tst_pre_grst_o <= 0;
125 
        adbginit_o <= 1;  // <--
126 
        gdbginit_o <= 0;
127 
        sys_reset_final_o <= 1;
128 
      end
129 
      else
130 
      if(cycle_counter<`RESET_CYCLES_3)
131 
      begin
132 
        cluster_cken_o <= 1;  // <--
133 
        cmp_grst_o <= 0;
134 
        cmp_arst_o <= 1;
135 
        ctu_tst_pre_grst_o <= 1;  // <--
136 
        adbginit_o <= 1;
137 
        gdbginit_o <= 0;
138 
        sys_reset_final_o <= 1;
139 
      end
140 
      else
141 
      if(cycle_counter<`RESET_CYCLES_4)
142 
      begin
143 
        cluster_cken_o <= 1;
144 
        cmp_grst_o <= 1;  // <--
145 
        cmp_arst_o <= 1;
146 
        ctu_tst_pre_grst_o <= 1;
147 
        adbginit_o <= 1;
148 
        gdbginit_o <= 1;  // <--
149 
        sys_reset_final_o <= 1;
150 
      end
151 
      else
152 
      begin
153 
        cluster_cken_o <= 1;
154 
        cmp_grst_o <= 1;
155 
        cmp_arst_o <= 1;
156 
        ctu_tst_pre_grst_o <= 1;
157 
        adbginit_o <= 1;
158 
        gdbginit_o <= 1;
159 
        sys_reset_final_o <= 0;  // <--
160 
      end
161 
    end
162 
  end
163 
 
164 
  assign gclk_o = (cycle_counter>`GCLK_CYCLES) & sys_clock_i;
165 
 
166 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.