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/*
 * Simply RISC S1 Definitions
 *
 * (C) Copyleft 2007 Simply RISC LLP
 * AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
 *
 * LICENSE:
 * This is a Free Hardware Design; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 * The above named program is distributed in the hope that it will
 * be useful, but WITHOUT ANY WARRANTY; without even the implied
 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * DESCRIPTION:
 * Simple constant definitions used by the S1 Core design.
 */
 
`include "t1_defs.h"
`timescale 1ns/100ps
 
`define FPGA_SYN
`define FPGA_SYN_1THREAD
`define FPGA_SYN_NO_SPU
 
// Size of the buses
`define WB_ADDR_WIDTH 64
`define WB_DATA_WIDTH 64
 
// States of the FSM of the bridge
`define STATE_WAKEUP          4'b0000
`define STATE_IDLE            4'b0001
`define STATE_REQUEST_LATCHED 4'b0010
`define STATE_PACKET_LATCHED  4'b0011
`define STATE_REQUEST_GRANTED 4'b0100
`define STATE_ACCESS2_BEGIN   4'b0101
`define STATE_ACCESS2_END     4'b0110
`define STATE_ACCESS3_BEGIN   4'b0111
`define STATE_ACCESS3_END     4'b1000
`define STATE_ACCESS4_BEGIN   4'b1001
`define STATE_ACCESS4_END     4'b1010
`define STATE_PACKET_READY    4'b1011
 
// Constants used by the timer of the Reset Controller
`define TIMER_BITS 16
`define RESET_CYCLES_1   100
`define RESET_CYCLES_2  1000
`define RESET_CYCLES_3  2000
`define RESET_CYCLES_4  3000
`define GCLK_CYCLES      900
 

Line No.	Rev	Author	Line
1	4	fafa1971	`/*`
2			`* Simply RISC S1 Definitions`
3			`*`
4			`* (C) Copyleft 2007 Simply RISC LLP`
5			`* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>`
6			`*`
7			`* LICENSE:`
8			`* This is a Free Hardware Design; you can redistribute it and/or`
9			`* modify it under the terms of the GNU General Public License`
10			`* version 2 as published by the Free Software Foundation.`
11			`* The above named program is distributed in the hope that it will`
12			`* be useful, but WITHOUT ANY WARRANTY; without even the implied`
13			`* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.`
14			`* See the GNU General Public License for more details.`
15			`*`
16			`* DESCRIPTION:`
17			`* Simple constant definitions used by the S1 Core design.`
18			`*/`
19
20			`include "t1_defs.h"
21			`timescale 1ns/100ps
22
23	44	fafa1971	`define FPGA_SYN
24			`define FPGA_SYN_1THREAD
25			`define FPGA_SYN_NO_SPU
26
27	4	fafa1971	`// Size of the buses`
28			`define WB_ADDR_WIDTH 64
29			`define WB_DATA_WIDTH 64
30
31			`// States of the FSM of the bridge`
32			`define STATE_WAKEUP 4'b0000
33			`define STATE_IDLE 4'b0001
34			`define STATE_REQUEST_LATCHED 4'b0010
35			`define STATE_PACKET_LATCHED 4'b0011
36			`define STATE_REQUEST_GRANTED 4'b0100
37			`define STATE_ACCESS2_BEGIN 4'b0101
38			`define STATE_ACCESS2_END 4'b0110
39			`define STATE_ACCESS3_BEGIN 4'b0111
40			`define STATE_ACCESS3_END 4'b1000
41			`define STATE_ACCESS4_BEGIN 4'b1001
42			`define STATE_ACCESS4_END 4'b1010
43			`define STATE_PACKET_READY 4'b1011
44
45			`// Constants used by the timer of the Reset Controller`
46			`define TIMER_BITS 16
47			`define RESET_CYCLES_1 100
48			`define RESET_CYCLES_2 1000
49			`define RESET_CYCLES_3 2000
50			`define RESET_CYCLES_4 3000
51			`define GCLK_CYCLES 900
52

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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [s1_top/] [s1_defs.h] - Blame information for rev 105