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/*
 * Bridge from SPARC Core to Wishbone Master
 *
 * (C) 2007 Simply RISC LLP
 * AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
 *
 * LICENSE:
 * This is a Free Hardware Design; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 * The above named program is distributed in the hope that it will
 * be useful, but WITHOUT ANY WARRANTY; without even the implied
 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * DESCRIPTION:
 * This block implements a bridge from one SPARC Core of the
 * OpenSPARC T1 to a master interface that makes use of the
 * Wishbone interconnect protocol.
 * For informations about Sun Microsystems' OpenSPARC T1
 * refer to the web site http://www.opensparc.net
 * For informations about OpenCores' Wishbone interconnect
 * please refer to the web site http://www.opencores.org
 */
 
`include "s1_defs.h"
 
module spc2wbm (
    sys_clock_i, sys_reset_i, sys_interrupt_source_i,
    spc_req_i, spc_atom_i, spc_packetout_i,
    spc_grant_o, spc_ready_o, spc_packetin_o, spc_stallreq_o,
    wbm_ack_i, wbm_data_i,
    wbm_cycle_o, wbm_strobe_o, wbm_we_o, wbm_addr_o, wbm_data_o, wbm_sel_o
  );
 
  /*
   * Inputs
   */
 
  // System inputs
  input sys_clock_i;                            // System Clock
  input sys_reset_i;                            // System Reset
  input[5:0] sys_interrupt_source_i;            // Encoded Interrupt Source
 
  // SPARC-side inputs connected to the PCX (Processor-to-Cache Xbar) outputs of the SPARC Core
  input[4:0] spc_req_i;                         // Request
  input spc_atom_i;                             // Atomic Request
  input[(`PCX_WIDTH-1):0] spc_packetout_i;      // Outgoing Packet
 
  // Wishbone Master interface inputs
  input wbm_ack_i;                              // Ack
  input[(`WB_DATA_WIDTH-1):0] wbm_data_i;       // Data In
 
  /*
   * Registered Outputs
   */
 
  // SPARC-side outputs connected to the CPX (Cache-to-Processor Xbar) inputs of the SPARC Core
  output[4:0] spc_grant_o;                      // Grant
  reg[4:0] spc_grant_o;                         // Grant
  output spc_ready_o;                           // Ready
  reg spc_ready_o;                              // Ready
  output[`CPX_WIDTH-1:0] spc_packetin_o;        // Incoming Packet
  reg[`CPX_WIDTH-1:0] spc_packetin_o;           // Incoming Packet
  output spc_stallreq_o;                        // Stall Request
  reg spc_stallreq_o;                           // Stall Request
 
  // Wishbone Master interface outputs
  output wbm_cycle_o;                           // Cycle Start
  reg wbm_cycle_o;                              // Cycle Start
  output wbm_strobe_o;                          // Strobe Request
  reg wbm_strobe_o;                             // Strobe Request
  output wbm_we_o;                              // Write Enable
  reg wbm_we_o;                                 // Write Enable
  output[`WB_ADDR_WIDTH-1:0] wbm_addr_o;        // Address Bus
  reg[`WB_ADDR_WIDTH-1:0] wbm_addr_o;           // Address Bus
  output[`WB_DATA_WIDTH-1:0] wbm_data_o;        // Data Out
  reg[`WB_DATA_WIDTH-1:0] wbm_data_o;           // Data Out
  output[`WB_DATA_WIDTH/8-1:0] wbm_sel_o;       // Select Output
  reg[`WB_DATA_WIDTH/8-1:0] wbm_sel_o;          // Select Output
 
  /*
   * Registers
   */
 
  // Registers to latch requests from SPARC Core to Wishbone Master
  reg[3:0] state;
  reg[4:0] spc2wbm_region;                                             // Target region number (one-hot encoded)
  reg spc2wbm_atom;
  reg[(`PCX_WIDTH-1):0] spc2wbm_packet;                                // Latched Packet
 
  // Wishbone Master to SPARC Core info used to encode the return packet
  reg wbm2spc_valid;                                                   // Valid
  reg[(`CPX_RQ_HI-`CPX_RQ_LO):0] wbm2spc_type;                         // Request type
  reg[(`CPX_ERR_HI-`CPX_ERR_LO):0] wbm2spc_error;                      // Error
  reg wbm2spc_nc;                                                      // Non-Cacheable
  reg[(`CPX_TH_HI-`CPX_TH_LO):0] wbm2spc_thread;                       // Thread
  reg wbm2spc_way_valid;                                               // L2 Way Valid
  reg[(`CPX_WY_HI-`CPX_WY_LO):0] wbm2spc_way;                          // Replaced L2 Way
  reg[(`CPX_DA_HI-`CPX_DA_LO):0] wbm2spc_data;                         // Load Data
  reg[6:0] wbm2spc_interrupt_source;                                   // Encoded Interrupt Source
  reg wbm2spc_interrupt_new;                                           // New Interrupt Pending
 
 
  /*
   * Wires
   */
 
  // Decoded SPARC Core to Wishbone Master info
  wire spc2wbm_req;                                                     // Request
  wire spc2wbm_valid;                                                   // Valid
  wire[(`PCX_RQ_HI-`PCX_RQ_LO):0] spc2wbm_type;                         // Request type
  wire spc2wbm_nc;                                                      // Non-Cacheable
  wire[(`PCX_CP_HI-`PCX_CP_LO):0] spc2wbm_cpu_id;                       // CPU ID
  wire[(`PCX_TH_HI-`PCX_TH_LO):0] spc2wbm_thread;                       // Thread
  wire spc2wbm_invalidate;                                              // Invalidate all
  wire[(`PCX_WY_HI-`PCX_WY_LO):0] spc2wbm_way;                          // Replaced L1 Way
  wire[(`PCX_SZ_HI-`PCX_SZ_LO):0] spc2wbm_size;                         // Load/Store size
  wire[(`PCX_AD_HI-`PCX_AD_LO):0] spc2wbm_addr;                         // Address
  wire[(`PCX_DA_HI-`PCX_DA_LO):0] spc2wbm_data;                         // Store Data
 
  // Return packets assembled with various fields
  wire[`CPX_WIDTH-1:0] wbm2spc_packet;                                  // Incoming Packet
 
  /*
   * Encode/decode incoming info
   *
   * Legenda: available constants for some of the PCX/CPX fields.
   *
   * spc2wbm_size (3 bits) is one of:
   * - PCX_SZ_1B
   * - PCX_SZ_2B
   * - PCX_SZ_4B
   * - PCX_SZ_8B
   * - PCX_SZ_16B (Read accesses only)
   *
   * spc2wbm_type (5 bits) is one of:
   * { LOAD_RQ, IMISS_RQ, STORE_RQ, CAS1_RQ, CAS2_RQ, SWAP_RQ, STRLOAD_RQ, STRST_RQ, STQ_RQ,
   *   INT_RQ, FWD_RQ, FWD_RPY, RSVD_RQ }
   *
   * wbm2spc_type (4 bits) is one of:
   * { LOAD_RET, INV_RET, ST_ACK, AT_ACK, INT_RET, TEST_RET, FP_RET, IFILL_RET, EVICT_REQ,
   *   ERR_RET, STRLOAD_RET, STRST_ACK, FWD_RQ_RET, FWD_RPY_RET, RSVD_RET }
   *
   */
 
  // Decode info arriving from the SPC side
  assign spc2wbm_req = ( spc_req_i[4] | spc_req_i[3] | spc_req_i[2] | spc_req_i[1] | spc_req_i[0] );
  assign spc2wbm_valid = spc2wbm_packet[`PCX_VLD];
  assign spc2wbm_type = spc2wbm_packet[`PCX_RQ_HI:`PCX_RQ_LO];
  assign spc2wbm_nc = spc2wbm_packet[`PCX_NC];
  assign spc2wbm_cpu_id = spc2wbm_packet[`PCX_CP_HI:`PCX_CP_LO];
  assign spc2wbm_thread = spc2wbm_packet[`PCX_TH_HI:`PCX_TH_LO];
  assign spc2wbm_invalidate = spc2wbm_packet[`PCX_INVALL];
  assign spc2wbm_way = spc2wbm_packet[`PCX_WY_HI:`PCX_WY_LO];
  assign spc2wbm_size = spc2wbm_packet[`PCX_SZ_HI:`PCX_SZ_LO];
  assign spc2wbm_addr = spc2wbm_packet[`PCX_AD_HI:`PCX_AD_LO];
  assign spc2wbm_data = spc2wbm_packet[`PCX_DA_HI:`PCX_DA_LO];
 
  // Encode info going to the SPC side assembling return packets
  assign wbm2spc_packet = { wbm2spc_valid, wbm2spc_type, wbm2spc_error, wbm2spc_nc,
    wbm2spc_thread, wbm2spc_way_valid, wbm2spc_way, 3'b100, wbm2spc_data };
 
  /*
   * State Machine
   */
 
  always @(posedge sys_clock_i) begin
 
    // Initialization
    if(sys_reset_i==1) begin
 
      // Clear outputs going to SPARC Core inputs
      spc_grant_o = 5'b00000;
      spc_ready_o = 0;
      spc_packetin_o = 0;
      spc_stallreq_o = 0;
 
      // Clear Wishbone Master interface outputs
      wbm_cycle_o = 0;
      wbm_strobe_o = 0;
      wbm_we_o = 0;
      wbm_addr_o = 64'b0;
      wbm_data_o = 64'b0;
      wbm_sel_o = 8'b0;
 
      // Prepare wakeup packet for SPARC Core, the resulting output is
      // spc_packetin_o = `CPX_WIDTH'h1700000000000000000000000000000010001;
      wbm2spc_valid = 1;
      wbm2spc_type = `INT_RET;
      wbm2spc_error = 0;
      wbm2spc_nc = 0;
      wbm2spc_thread = 0;
      wbm2spc_way_valid = 0;
      wbm2spc_way = 0;
      wbm2spc_data = 64'h10001;
 
      // Clear state machine
      state = `STATE_WAKEUP;
 
    end else begin
 
      // FSM State 0: STATE_WAKEUP
      // Send to the SPARC Core the wakeup packet
      if(state==`STATE_WAKEUP) begin
 
        // Send wakeup packet
        spc_ready_o = 1;
        spc_packetin_o = wbm2spc_packet;
 
// synopsys translate_off
        // Display comment
        $display("INFO: SPC2WBM: SPARC Core to Wishbone Master bridge starting...");
        $display("INFO: SPC2WBM: Wakeup packet sent to SPARC Core");
// synopsys translate_on
 
        // Unconditional state change
        state = `STATE_IDLE;
 
      // FSM State 1: STATE_IDLE
      // Wait for a request from the SPARC Core
      // If available send an interrupt packet to the Core
      end else if(state==`STATE_IDLE) begin
 
        // Check if there's an incoming request
        if(spc2wbm_req==1) begin
 
          // Clear previously modified outputs
          spc_ready_o = 0;
          spc_packetin_o = 0;
 
          // Stall other requests from the SPARC Core
          spc_stallreq_o = 1;
 
          // Latch target region and atomicity
          spc2wbm_region = spc_req_i;
          spc2wbm_atom = spc_atom_i;
 
          // Jump to next state
          state = `STATE_REQUEST_LATCHED;
 
        // See if the interrupt vector has changed
        end else if(sys_interrupt_source_i!=wbm2spc_interrupt_source) begin
 
          // Set the flag for next cycle
          wbm2spc_interrupt_new = 1;
 
          // Prepare the interrupt packet for the SPARC Core
          wbm2spc_valid = 1;
          wbm2spc_type = `INT_RET;
          wbm2spc_error = 0;
          wbm2spc_nc = 0;
          wbm2spc_thread = 0;
          wbm2spc_way_valid = 0;
          wbm2spc_way = 0;
 
          // Stall other requests from the SPARC Core
          spc_stallreq_o = 1;
 
        // Next cycle see if there's an int to be forwarded to the Core
        end else if(wbm2spc_interrupt_source!=6'b000000 && wbm2spc_interrupt_new) begin
 
          // Clean the flag
          wbm2spc_interrupt_new = 0;
 
          // Send the interrupt packet to the Core
          spc_ready_o = 1;
          spc_packetin_o = wbm2spc_packet;
 
          // Stall other requests from the SPARC Core
          spc_stallreq_o = 1;
 
          // Stay in this state
          state = `STATE_IDLE;
 
        // Nothing to do, stay idle
        end else begin
 
          // Clear previously modified outputs
          spc_ready_o = 0;
          spc_packetin_o = 0;
          spc_stallreq_o = 0;
 
          // Stay in this state
          state = `STATE_IDLE;
 
        end
 
      // FSM State 2: STATE_REQUEST_LATCHED
      // We've just latched the request
      // Now we latch the packet
      // Start granting the request
      end else if(state==`STATE_REQUEST_LATCHED) begin
 
        // Latch the incoming packet
        spc2wbm_packet = spc_packetout_i;
 
        // Grant the request to the SPARC Core
        spc_grant_o = spc2wbm_region;
 
// synopsys translate_off
        // Print details of SPARC Core request
        $display("INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE ***");
        if(spc2wbm_region[0]==1) $display("INFO: SPC2WBM: Request to RAM Bank 0");
        else if(spc2wbm_region[1]==1) $display("INFO: SPC2WBM: Request to RAM Bank 1");
        else if(spc2wbm_region[2]==1) $display("INFO: SPC2WBM: Request to RAM Bank 2");
        else if(spc2wbm_region[3]==1) $display("INFO: SPC2WBM: Request to RAM Bank 3");
        else if(spc2wbm_region[4]==1) $display("INFO: SPC2WBM: Request targeted to I/O Block");
        else $display("INFO: SPC2WBM: Request to target region unknown");
        if(spc2wbm_atom==1) $display("INFO: SPC2WBM: Request is ATOMIC");
        else $display("INFO: SPC2WBM: Request is not atomic");
// synopsys translate_on
 
        // Unconditional state change
        state = `STATE_PACKET_LATCHED;
 
      // FSM State 3: STATE_PACKET_LATCHED
      // The packet has already been latched
      // Decode this packet to build the request for the Wishbone bus
      // The grant of the request to the SPARC Core has been completed
      end else if(state==`STATE_PACKET_LATCHED) begin
 
        // Clear previously modified outputs
        spc_grant_o = 5'b0;
 
        // Issue a request on the Wishbone bus
        wbm_cycle_o = 1;
        wbm_strobe_o = 1;
        wbm_addr_o = { spc2wbm_region, 19'b0, spc2wbm_addr[`PCX_AD_HI-`PCX_AD_LO:3], 3'b000 };
        wbm_data_o = spc2wbm_data;
 
        // Handle write enable and byte select
        if(spc2wbm_type==`IMISS_RQ) begin
 
          // For instruction miss always read memory
          wbm_we_o = 0;
          if(spc2wbm_region==5'b10000)
            // For accesses to SSI ROM only 32 bits are required
            wbm_sel_o = (4'b1111<<(spc2wbm_addr[2]<<2));
          else
            // For accesses to RAM 256 bits are expected (2 ret packets)
            wbm_sel_o = 8'b11111111;
 
        end else if(spc2wbm_type==`LOAD_RQ) begin
 
          // For data load use the provided data
          wbm_we_o = 0;
          case(spc2wbm_size)
            `PCX_SZ_1B: wbm_sel_o = (1'b1<<spc2wbm_addr[2:0]);
            `PCX_SZ_2B: wbm_sel_o = (2'b11<<(spc2wbm_addr[2:1]<<1));
            `PCX_SZ_4B: wbm_sel_o = (4'b1111<<(spc2wbm_addr[2]<<2));
            `PCX_SZ_8B: wbm_sel_o = 8'b11111111;
            `PCX_SZ_16B: wbm_sel_o = 8'b11111111;  // Requires a 2nd access
            default: wbm_sel_o = 8'b00000000;
          endcase
 
        end else if(spc2wbm_type==`STORE_RQ) begin
 
          // For data store use the provided data
          wbm_we_o = 1;
          case(spc2wbm_size)
            `PCX_SZ_1B: wbm_sel_o = (1'b1<<spc2wbm_addr[2:0]);
            `PCX_SZ_2B: wbm_sel_o = (2'b11<<(spc2wbm_addr[2:1]<<1));
            `PCX_SZ_4B: wbm_sel_o = (4'b1111<<(spc2wbm_addr[2]<<2));
            `PCX_SZ_8B: wbm_sel_o = 8'b11111111;
            `PCX_SZ_16B: wbm_sel_o = 8'b11111111;  // Requires a 2nd access
            default: wbm_sel_o = 8'b00000000;
          endcase
 
        end else begin
 
          wbm_we_o = 1;
          wbm_sel_o = 8'b00000000;
 
        end
 
// synopsys translate_off
        // Print details of request packet
        $display("INFO: SPC2WBM: Valid bit is %X", spc2wbm_valid);
        case(spc2wbm_type)
          `LOAD_RQ: $display("INFO: SPC2WBM: Request of Type LOAD_RQ");
          `IMISS_RQ: $display("INFO: SPC2WBM: Request of Type IMISS_RQ");
          `STORE_RQ: $display("INFO: SPC2WBM: Request of Type STORE_RQ");
          `CAS1_RQ: $display("INFO: SPC2WBM: Request of Type CAS1_RQ");
          `CAS2_RQ: $display("INFO: SPC2WBM: Request of Type CAS2_RQ");
          `SWAP_RQ: $display("INFO: SPC2WBM: Request of Type SWAP_RQ");
          `STRLOAD_RQ: $display("INFO: SPC2WBM: Request of Type STRLOAD_RQ");
          `STRST_RQ: $display("INFO: SPC2WBM: Request of Type STRST_RQ");
          `STQ_RQ: $display("INFO: SPC2WBM: Request of Type STQ_RQ");
          `INT_RQ: $display("INFO: SPC2WBM: Request of Type INT_RQ");
          `FWD_RQ: $display("INFO: SPC2WBM: Request of Type FWD_RQ");
          `FWD_RPY: $display("INFO: SPC2WBM: Request of Type FWD_RPY");
          `RSVD_RQ: $display("INFO: SPC2WBM: Request of Type RSVD_RQ");
          default: $display("INFO: SPC2WBM: Request of Type Unknown");
        endcase
        $display("INFO: SPC2WBM: Non-Cacheable is %X", spc2wbm_nc);
        $display("INFO: SPC2WBM: CPU-ID is %X", spc2wbm_cpu_id);
        $display("INFO: SPC2WBM: Thread is %X", spc2wbm_thread);
        $display("INFO: SPC2WBM: Invalidate All is %X", spc2wbm_invalidate);
        $display("INFO: SPC2WBM: Replaced L1 Way is %X", spc2wbm_way);
        case(spc2wbm_size)
          `PCX_SZ_1B: $display("INFO: SPC2WBM: Request size is 1 Byte");
          `PCX_SZ_2B: $display("INFO: SPC2WBM: Request size is 2 Bytes");
          `PCX_SZ_4B: $display("INFO: SPC2WBM: Request size is 4 Bytes");
          `PCX_SZ_8B: $display("INFO: SPC2WBM: Request size is 8 Bytes");
          `PCX_SZ_16B: $display("INFO: SPC2WBM: Request size is 16 Bytes");
          default: $display("INFO: SPC2WBM: Request size is Unknown");
        endcase
        $display("INFO: SPC2WBM: Address is %X", spc2wbm_addr);
        $display("INFO: SPC2WBM: Data is %X", spc2wbm_data);
        $display("INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master");
// synopsys translate_on
 
        // Unconditional state change
        state = `STATE_REQUEST_GRANTED;
 
      // FSM State 4: STATE_REQUEST_GRANTED
      // Wishbone access completed, latch the incoming data
      end else if(state==`STATE_REQUEST_GRANTED) begin
 
        // Wait until Wishbone access completes
        if(wbm_ack_i==1) begin
 
          // Clear previously modified outputs
          if(spc2wbm_atom==0) wbm_cycle_o = 0;
          wbm_strobe_o = 0;
          wbm_we_o = 0;
          wbm_addr_o = 64'b0;
          wbm_data_o = 64'b0;
          wbm_sel_o = 8'b0;
 
          // Latch the data and set up the return packet for the SPARC Core
          wbm2spc_valid = 1;
          case(spc2wbm_type)
            `IMISS_RQ: begin
              wbm2spc_type = `IFILL_RET; // I-Cache Miss
            end
            `LOAD_RQ: begin
              wbm2spc_type = `LOAD_RET;  // Load
            end
            `STORE_RQ: begin
              wbm2spc_type = `ST_ACK;    // Store
            end
          endcase
          wbm2spc_error = 0;
          wbm2spc_nc = spc2wbm_nc;
          wbm2spc_thread = spc2wbm_thread;
          wbm2spc_way_valid = 0;
          wbm2spc_way = 0;
          if(spc2wbm_addr[3]==0) wbm2spc_data = { wbm_data_i, 64'b0 };
          else wbm2spc_data = { 64'b0, wbm_data_i };
 
          // See if other 64-bit Wishbone accesses are required
          if(
              // Instruction miss directed to RAM expects 256 bits
              ( (spc2wbm_type==`IMISS_RQ)&&(spc2wbm_region!=5'b10000) ) ||
              // Data access of 128 bits
              ( (spc2wbm_type==`LOAD_RQ)&&(spc2wbm_size==`PCX_SZ_16B) )
            )
            state = `STATE_ACCESS2_BEGIN;
          else
            state = `STATE_PACKET_READY;
 
        end else state = `STATE_REQUEST_GRANTED;
 
      // FSM State 5: STATE_ACCESS2_BEGIN
      // If needed start a second read access to the Wishbone bus
      end else if(state==`STATE_ACCESS2_BEGIN) begin
 
        // Issue a second request on the Wishbone bus
        wbm_cycle_o = 1;
        wbm_strobe_o = 1;
        wbm_we_o = 0;
        wbm_addr_o = { spc2wbm_region, 19'b0, spc2wbm_addr[`PCX_AD_HI-`PCX_AD_LO:4], 4'b1000 };  // 2nd doubleword inside the same quadword
        wbm_data_o = 64'b0;
        wbm_sel_o = 8'b11111111;
 
        // Unconditional state change
        state = `STATE_ACCESS2_END;
 
      // FSM State 6: STATE_ACCESS2_END
      // Latch the second data returning from Wishbone when ready
      end else if(state==`STATE_ACCESS2_END) begin
 
        // Wait until Wishbone access completes
        if(wbm_ack_i==1) begin
 
          // Clear previously modified outputs
          if(spc2wbm_atom==0) wbm_cycle_o = 0;
          wbm_strobe_o = 0;
          wbm_we_o = 0;
          wbm_addr_o = 64'b0;
          wbm_data_o = 64'b0;
          wbm_sel_o = 8'b0;
 
          // Latch the data and set up the return packet for the SPARC Core
          wbm2spc_data[63:0] = wbm_data_i;
 
          // See if two return packets are required or just one
          if(spc2wbm_type==`IMISS_RQ && spc2wbm_region==5'b10000)
            state = `STATE_PACKET_READY;
          else
            state = `STATE_ACCESS3_BEGIN;
 
        end else state = `STATE_ACCESS2_END;
 
      // FSM State 7: STATE_ACCESS3_BEGIN
      // If needed start a third read access to the Wishbone bus
      // In the meanwhile we can return the first 128-bit packet
      end else if(state==`STATE_ACCESS3_BEGIN) begin
 
        // Return the packet to the SPARC Core
        spc_ready_o = 1;
        spc_packetin_o = wbm2spc_packet;
 
        // Issue a third request on the Wishbone bus
        wbm_cycle_o = 1;
        wbm_strobe_o = 1;
        wbm_we_o = 0;
        wbm_addr_o = { spc2wbm_region, 19'b0, spc2wbm_addr[`PCX_AD_HI-`PCX_AD_LO:5], 5'b10000 };  // 3nd doubleword inside the same 256-bit data
        wbm_data_o = 64'b0;
        wbm_sel_o = 8'b11111111;
 
// synopsys translate_off
        // Print details of return packet
        $display("INFO: WBM2SPC: Return packet has valid bit %X", wbm2spc_valid);
        case(wbm2spc_type)
          `IFILL_RET: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
          `LOAD_RET: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
          `ST_ACK: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
          default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
        endcase
        $display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
        $display("INFO: WBM2SPC: Non-Cacheable is %X", wbm2spc_nc);
        $display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
        $display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
        $display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
        $display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
        $display("INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core");
// synopsys translate_on
 
        // Unconditional state change
        state = `STATE_ACCESS3_END;
 
      // FSM State 8: STATE_ACCESS3_END
      // Latch the second data returning from Wishbone when ready
      end else if(state==`STATE_ACCESS3_END) begin
 
        // Clear previously modified outputs
        spc_ready_o = 0;
 
        // Wait until Wishbone access completes
        if(wbm_ack_i==1) begin
 
          // Clear previously modified outputs
          if(spc2wbm_atom==0) wbm_cycle_o = 0;
          wbm_strobe_o = 0;
          wbm_we_o = 0;
          wbm_addr_o = 64'b0;
          wbm_data_o = 64'b0;
          wbm_sel_o = 8'b0;
 
          // Latch the data and set up the return packet for the SPARC Core
          wbm2spc_data = { wbm_data_i, 64'b0 };
 
          // Jump to next state
          state = `STATE_ACCESS4_BEGIN;
 
        end else state = `STATE_ACCESS3_END;
 
      // FSM State 9: STATE_ACCESS4_BEGIN
      // If needed start a second read access to the Wishbone bus
      end else if(state==`STATE_ACCESS4_BEGIN) begin
 
        // Issue a fourth request on the Wishbone bus
        wbm_cycle_o = 1;
        wbm_strobe_o = 1;
        wbm_we_o = 0;
        wbm_addr_o = { spc2wbm_region, 19'b0, spc2wbm_addr[`PCX_AD_HI-`PCX_AD_LO:5], 5'b11000 };  // 4th doubleword inside the same 256-bit data
        wbm_data_o = 64'b0;
        wbm_sel_o = 8'b11111111;
 
        // Unconditional state change
        state = `STATE_ACCESS4_END;
 
      // FSM State 10: STATE_ACCESS4_END
      // Latch the second data returning from Wishbone when ready
      end else if(state==`STATE_ACCESS4_END) begin
 
        // Wait until Wishbone access completes
        if(wbm_ack_i==1) begin
 
          // Clear previously modified outputs
          if(spc2wbm_atom==0) wbm_cycle_o = 0;
          wbm_strobe_o = 0;
          wbm_we_o = 0;
          wbm_addr_o = 64'b0;
          wbm_data_o = 64'b0;
          wbm_sel_o = 8'b0;
 
          // Latch the data and set up the return packet for the SPARC Core
          wbm2spc_data[63:0] = wbm_data_i;
 
          // Jump to next state
          state = `STATE_PACKET_READY;
 
        end else state = `STATE_ACCESS4_END;
 
      // FSM State 11: STATE_PACKET_READY
      // We can start returning the packet to the SPARC Core
      end else if(state==`STATE_PACKET_READY) begin
 
        // Return the packet to the SPARC Core
        spc_ready_o = 1;
        spc_packetin_o = wbm2spc_packet;
 
        // Unconditional state change
        state = `STATE_IDLE;
 
// synopsys translate_off
        // Print details of return packet
        $display("INFO: WBM2SPC: Valid bit is %X", wbm2spc_valid);
        case(wbm2spc_type)
          `IFILL_RET: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
          `LOAD_RET: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
          `ST_ACK: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
          default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
        endcase
        $display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
        $display("INFO: WBM2SPC: Non-Cacheable bit is %X", wbm2spc_nc);
        $display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
        $display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
        $display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
        $display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
        $display("INFO: WBM2SPC: Return Packet forwarded from Wishbone Master to SPARC Core");
// synopsys translate_on
 
      end
    end
  end
 
endmodule
 

Line No.	Rev	Author	Line
1	4	fafa1971	`/*`
2			`* Bridge from SPARC Core to Wishbone Master`
3			`*`
4			`* (C) 2007 Simply RISC LLP`
5			`* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>`
6			`*`
7			`* LICENSE:`
8			`* This is a Free Hardware Design; you can redistribute it and/or`
9			`* modify it under the terms of the GNU General Public License`
10			`* version 2 as published by the Free Software Foundation.`
11			`* The above named program is distributed in the hope that it will`
12			`* be useful, but WITHOUT ANY WARRANTY; without even the implied`
13			`* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.`
14			`* See the GNU General Public License for more details.`
15			`*`
16			`* DESCRIPTION:`
17			`* This block implements a bridge from one SPARC Core of the`
18			`* OpenSPARC T1 to a master interface that makes use of the`
19			`* Wishbone interconnect protocol.`
20			`* For informations about Sun Microsystems' OpenSPARC T1`
21			`* refer to the web site http://www.opensparc.net`
22			`* For informations about OpenCores' Wishbone interconnect`
23			`* please refer to the web site http://www.opencores.org`
24			`*/`
25
26			`include "s1_defs.h"
27
28			`module spc2wbm (`
29			`sys_clock_i, sys_reset_i, sys_interrupt_source_i,`
30			`spc_req_i, spc_atom_i, spc_packetout_i,`
31			`spc_grant_o, spc_ready_o, spc_packetin_o, spc_stallreq_o,`
32			`wbm_ack_i, wbm_data_i,`
33			`wbm_cycle_o, wbm_strobe_o, wbm_we_o, wbm_addr_o, wbm_data_o, wbm_sel_o`
34			`);`
35
36			`/*`
37			`* Inputs`
38			`*/`
39
40			`// System inputs`
41			`input sys_clock_i; // System Clock`
42			`input sys_reset_i; // System Reset`
43	11	fafa1971	`input[5:0] sys_interrupt_source_i; // Encoded Interrupt Source`
44	4	fafa1971
45			`// SPARC-side inputs connected to the PCX (Processor-to-Cache Xbar) outputs of the SPARC Core`
46			`input[4:0] spc_req_i; // Request`
47			`input spc_atom_i; // Atomic Request`
48			input[(`PCX_WIDTH-1):0] spc_packetout_i; // Outgoing Packet
49
50			`// Wishbone Master interface inputs`
51			`input wbm_ack_i; // Ack`
52			input[(`WB_DATA_WIDTH-1):0] wbm_data_i; // Data In
53
54			`/*`
55			`* Registered Outputs`
56			`*/`
57
58			`// SPARC-side outputs connected to the CPX (Cache-to-Processor Xbar) inputs of the SPARC Core`
59			`output[4:0] spc_grant_o; // Grant`
60			`reg[4:0] spc_grant_o; // Grant`
61			`output spc_ready_o; // Ready`
62			`reg spc_ready_o; // Ready`
63			output[`CPX_WIDTH-1:0] spc_packetin_o; // Incoming Packet
64			reg[`CPX_WIDTH-1:0] spc_packetin_o; // Incoming Packet
65			`output spc_stallreq_o; // Stall Request`
66			`reg spc_stallreq_o; // Stall Request`
67
68			`// Wishbone Master interface outputs`
69			`output wbm_cycle_o; // Cycle Start`
70			`reg wbm_cycle_o; // Cycle Start`
71			`output wbm_strobe_o; // Strobe Request`
72			`reg wbm_strobe_o; // Strobe Request`
73			`output wbm_we_o; // Write Enable`
74			`reg wbm_we_o; // Write Enable`
75			output[`WB_ADDR_WIDTH-1:0] wbm_addr_o; // Address Bus
76			reg[`WB_ADDR_WIDTH-1:0] wbm_addr_o; // Address Bus
77			output[`WB_DATA_WIDTH-1:0] wbm_data_o; // Data Out
78			reg[`WB_DATA_WIDTH-1:0] wbm_data_o; // Data Out
79			output[`WB_DATA_WIDTH/8-1:0] wbm_sel_o; // Select Output
80			reg[`WB_DATA_WIDTH/8-1:0] wbm_sel_o; // Select Output
81
82			`/*`
83			`* Registers`
84			`*/`
85
86			`// Registers to latch requests from SPARC Core to Wishbone Master`
87			`reg[3:0] state;`
88			`reg[4:0] spc2wbm_region; // Target region number (one-hot encoded)`
89			`reg spc2wbm_atom;`
90			reg[(`PCX_WIDTH-1):0] spc2wbm_packet; // Latched Packet
91
92			`// Wishbone Master to SPARC Core info used to encode the return packet`
93			`reg wbm2spc_valid; // Valid`
94			reg[(`CPX_RQ_HI-`CPX_RQ_LO):0] wbm2spc_type; // Request type
95			reg[(`CPX_ERR_HI-`CPX_ERR_LO):0] wbm2spc_error; // Error
96	11	fafa1971	`reg wbm2spc_nc; // Non-Cacheable`
97	4	fafa1971	reg[(`CPX_TH_HI-`CPX_TH_LO):0] wbm2spc_thread; // Thread
98	11	fafa1971	`reg wbm2spc_way_valid; // L2 Way Valid`
99			reg[(`CPX_WY_HI-`CPX_WY_LO):0] wbm2spc_way; // Replaced L2 Way
100	4	fafa1971	reg[(`CPX_DA_HI-`CPX_DA_LO):0] wbm2spc_data; // Load Data
101	11	fafa1971	`reg[6:0] wbm2spc_interrupt_source; // Encoded Interrupt Source`
102			`reg wbm2spc_interrupt_new; // New Interrupt Pending`
103
104
105	4	fafa1971	`/*`
106			`* Wires`
107			`*/`
108
109			`// Decoded SPARC Core to Wishbone Master info`
110			`wire spc2wbm_req; // Request`
111			`wire spc2wbm_valid; // Valid`
112			wire[(`PCX_RQ_HI-`PCX_RQ_LO):0] spc2wbm_type; // Request type
113	11	fafa1971	`wire spc2wbm_nc; // Non-Cacheable`
114	4	fafa1971	wire[(`PCX_CP_HI-`PCX_CP_LO):0] spc2wbm_cpu_id; // CPU ID
115			wire[(`PCX_TH_HI-`PCX_TH_LO):0] spc2wbm_thread; // Thread
116	11	fafa1971	`wire spc2wbm_invalidate; // Invalidate all`
117			wire[(`PCX_WY_HI-`PCX_WY_LO):0] spc2wbm_way; // Replaced L1 Way
118	4	fafa1971	wire[(`PCX_SZ_HI-`PCX_SZ_LO):0] spc2wbm_size; // Load/Store size
119			wire[(`PCX_AD_HI-`PCX_AD_LO):0] spc2wbm_addr; // Address
120			wire[(`PCX_DA_HI-`PCX_DA_LO):0] spc2wbm_data; // Store Data
121
122			`// Return packets assembled with various fields`
123	11	fafa1971	wire[`CPX_WIDTH-1:0] wbm2spc_packet; // Incoming Packet
124	4	fafa1971
125			`/*`
126			`* Encode/decode incoming info`
127			`*`
128			`* Legenda: available constants for some of the PCX/CPX fields.`
129			`*`
130			`* spc2wbm_size (3 bits) is one of:`
131			`* - PCX_SZ_1B`
132			`* - PCX_SZ_2B`
133			`* - PCX_SZ_4B`
134			`* - PCX_SZ_8B`
135			`* - PCX_SZ_16B (Read accesses only)`
136			`*`
137			`* spc2wbm_type (5 bits) is one of:`
138			`* { LOAD_RQ, IMISS_RQ, STORE_RQ, CAS1_RQ, CAS2_RQ, SWAP_RQ, STRLOAD_RQ, STRST_RQ, STQ_RQ,`
139			`* INT_RQ, FWD_RQ, FWD_RPY, RSVD_RQ }`
140			`*`
141			`* wbm2spc_type (4 bits) is one of:`
142			`* { LOAD_RET, INV_RET, ST_ACK, AT_ACK, INT_RET, TEST_RET, FP_RET, IFILL_RET, EVICT_REQ,`
143			`* ERR_RET, STRLOAD_RET, STRST_ACK, FWD_RQ_RET, FWD_RPY_RET, RSVD_RET }`
144			`*`
145			`*/`
146
147			`// Decode info arriving from the SPC side`
148			`assign spc2wbm_req = ( spc_req_i[4] \| spc_req_i[3] \| spc_req_i[2] \| spc_req_i[1] \| spc_req_i[0] );`
149			assign spc2wbm_valid = spc2wbm_packet[`PCX_VLD];
150			assign spc2wbm_type = spc2wbm_packet[`PCX_RQ_HI:`PCX_RQ_LO];
151	11	fafa1971	assign spc2wbm_nc = spc2wbm_packet[`PCX_NC];
152	4	fafa1971	assign spc2wbm_cpu_id = spc2wbm_packet[`PCX_CP_HI:`PCX_CP_LO];
153			assign spc2wbm_thread = spc2wbm_packet[`PCX_TH_HI:`PCX_TH_LO];
154	11	fafa1971	assign spc2wbm_invalidate = spc2wbm_packet[`PCX_INVALL];
155			assign spc2wbm_way = spc2wbm_packet[`PCX_WY_HI:`PCX_WY_LO];
156	4	fafa1971	assign spc2wbm_size = spc2wbm_packet[`PCX_SZ_HI:`PCX_SZ_LO];
157			assign spc2wbm_addr = spc2wbm_packet[`PCX_AD_HI:`PCX_AD_LO];
158			assign spc2wbm_data = spc2wbm_packet[`PCX_DA_HI:`PCX_DA_LO];
159
160			`// Encode info going to the SPC side assembling return packets`
161	11	fafa1971	`assign wbm2spc_packet = { wbm2spc_valid, wbm2spc_type, wbm2spc_error, wbm2spc_nc,`
162			`wbm2spc_thread, wbm2spc_way_valid, wbm2spc_way, 3'b100, wbm2spc_data };`
163	4	fafa1971
164			`/*`
165			`* State Machine`
166			`*/`
167
168			`always @(posedge sys_clock_i) begin`
169
170			`// Initialization`
171			`if(sys_reset_i==1) begin`
172
173			`// Clear outputs going to SPARC Core inputs`
174			`spc_grant_o = 5'b00000;`
175			`spc_ready_o = 0;`
176			`spc_packetin_o = 0;`
177			`spc_stallreq_o = 0;`
178
179			`// Clear Wishbone Master interface outputs`
180			`wbm_cycle_o = 0;`
181			`wbm_strobe_o = 0;`
182			`wbm_we_o = 0;`
183			`wbm_addr_o = 64'b0;`
184			`wbm_data_o = 64'b0;`
185			`wbm_sel_o = 8'b0;`
186
187			`// Prepare wakeup packet for SPARC Core, the resulting output is`
188			// spc_packetin_o = `CPX_WIDTH'h1700000000000000000000000000000010001;
189			`wbm2spc_valid = 1;`
190			wbm2spc_type = `INT_RET;
191			`wbm2spc_error = 0;`
192	11	fafa1971	`wbm2spc_nc = 0;`
193	4	fafa1971	`wbm2spc_thread = 0;`
194	11	fafa1971	`wbm2spc_way_valid = 0;`
195			`wbm2spc_way = 0;`
196			`wbm2spc_data = 64'h10001;`
197	4	fafa1971
198			`// Clear state machine`
199			state = `STATE_WAKEUP;
200
201			`end else begin`
202
203			`// FSM State 0: STATE_WAKEUP`
204			`// Send to the SPARC Core the wakeup packet`
205			if(state==`STATE_WAKEUP) begin
206
207			`// Send wakeup packet`
208			`spc_ready_o = 1;`
209	11	fafa1971	`spc_packetin_o = wbm2spc_packet;`
210	4	fafa1971
211			`// synopsys translate_off`
212			`// Display comment`
213			`$display("INFO: SPC2WBM: SPARC Core to Wishbone Master bridge starting...");`
214			`$display("INFO: SPC2WBM: Wakeup packet sent to SPARC Core");`
215			`// synopsys translate_on`
216
217			`// Unconditional state change`
218			state = `STATE_IDLE;
219
220			`// FSM State 1: STATE_IDLE`
221			`// Wait for a request from the SPARC Core`
222			`// If available send an interrupt packet to the Core`
223			end else if(state==`STATE_IDLE) begin
224
225			`// Check if there's an incoming request`
226			`if(spc2wbm_req==1) begin`
227
228			`// Clear previously modified outputs`
229			`spc_ready_o = 0;`
230			`spc_packetin_o = 0;`
231
232			`// Stall other requests from the SPARC Core`
233			`spc_stallreq_o = 1;`
234
235			`// Latch target region and atomicity`
236			`spc2wbm_region = spc_req_i;`
237			`spc2wbm_atom = spc_atom_i;`
238
239			`// Jump to next state`
240			state = `STATE_REQUEST_LATCHED;
241
242			`// See if the interrupt vector has changed`
243			`end else if(sys_interrupt_source_i!=wbm2spc_interrupt_source) begin`
244
245			`// Set the flag for next cycle`
246	11	fafa1971	`wbm2spc_interrupt_new = 1;`
247	4	fafa1971
248			`// Prepare the interrupt packet for the SPARC Core`
249			`wbm2spc_valid = 1;`
250			wbm2spc_type = `INT_RET;
251			`wbm2spc_error = 0;`
252	11	fafa1971	`wbm2spc_nc = 0;`
253	4	fafa1971	`wbm2spc_thread = 0;`
254	11	fafa1971	`wbm2spc_way_valid = 0;`
255			`wbm2spc_way = 0;`
256	4	fafa1971
257			`// Stall other requests from the SPARC Core`
258			`spc_stallreq_o = 1;`
259
260			`// Next cycle see if there's an int to be forwarded to the Core`
261	11	fafa1971	`end else if(wbm2spc_interrupt_source!=6'b000000 && wbm2spc_interrupt_new) begin`
262	4	fafa1971
263			`// Clean the flag`
264	11	fafa1971	`wbm2spc_interrupt_new = 0;`
265	4	fafa1971
266			`// Send the interrupt packet to the Core`
267			`spc_ready_o = 1;`
268	11	fafa1971	`spc_packetin_o = wbm2spc_packet;`
269	4	fafa1971
270			`// Stall other requests from the SPARC Core`
271			`spc_stallreq_o = 1;`
272
273			`// Stay in this state`
274			state = `STATE_IDLE;
275
276			`// Nothing to do, stay idle`
277			`end else begin`
278
279			`// Clear previously modified outputs`
280			`spc_ready_o = 0;`
281			`spc_packetin_o = 0;`
282			`spc_stallreq_o = 0;`
283
284			`// Stay in this state`
285			state = `STATE_IDLE;
286
287			`end`
288
289			`// FSM State 2: STATE_REQUEST_LATCHED`
290			`// We've just latched the request`
291			`// Now we latch the packet`
292			`// Start granting the request`
293			end else if(state==`STATE_REQUEST_LATCHED) begin
294
295			`// Latch the incoming packet`
296			`spc2wbm_packet = spc_packetout_i;`
297
298			`// Grant the request to the SPARC Core`
299			`spc_grant_o = spc2wbm_region;`
300
301			`// synopsys translate_off`
302			`// Print details of SPARC Core request`
303			`$display("INFO: SPC2WBM: * NEW REQUEST FROM SPARC CORE *");`
304			`if(spc2wbm_region[0]==1) $display("INFO: SPC2WBM: Request to RAM Bank 0");`
305			`else if(spc2wbm_region[1]==1) $display("INFO: SPC2WBM: Request to RAM Bank 1");`
306			`else if(spc2wbm_region[2]==1) $display("INFO: SPC2WBM: Request to RAM Bank 2");`
307			`else if(spc2wbm_region[3]==1) $display("INFO: SPC2WBM: Request to RAM Bank 3");`
308			`else if(spc2wbm_region[4]==1) $display("INFO: SPC2WBM: Request targeted to I/O Block");`
309			`else $display("INFO: SPC2WBM: Request to target region unknown");`
310			`if(spc2wbm_atom==1) $display("INFO: SPC2WBM: Request is ATOMIC");`
311			`else $display("INFO: SPC2WBM: Request is not atomic");`
312			`// synopsys translate_on`
313
314			`// Unconditional state change`
315			state = `STATE_PACKET_LATCHED;
316
317			`// FSM State 3: STATE_PACKET_LATCHED`
318			`// The packet has already been latched`
319			`// Decode this packet to build the request for the Wishbone bus`
320			`// The grant of the request to the SPARC Core has been completed`
321			end else if(state==`STATE_PACKET_LATCHED) begin
322
323			`// Clear previously modified outputs`
324			`spc_grant_o = 5'b0;`
325
326			`// Issue a request on the Wishbone bus`
327			`wbm_cycle_o = 1;`
328			`wbm_strobe_o = 1;`
329			wbm_addr_o = { spc2wbm_region, 19'b0, spc2wbm_addr[`PCX_AD_HI-`PCX_AD_LO:3], 3'b000 };
330			`wbm_data_o = spc2wbm_data;`
331
332			`// Handle write enable and byte select`
333			if(spc2wbm_type==`IMISS_RQ) begin
334
335			`// For instruction miss always read memory`
336			`wbm_we_o = 0;`
337			`if(spc2wbm_region==5'b10000)`
338			`// For accesses to SSI ROM only 32 bits are required`
339			`wbm_sel_o = (4'b1111<<(spc2wbm_addr[2]<<2));`
340			`else`
341			`// For accesses to RAM 256 bits are expected (2 ret packets)`
342			`wbm_sel_o = 8'b11111111;`
343
344	11	fafa1971	end else if(spc2wbm_type==`LOAD_RQ) begin
345
346			`// For data load use the provided data`
347			`wbm_we_o = 0;`
348			`case(spc2wbm_size)`
349			`PCX_SZ_1B: wbm_sel_o = (1'b1<<spc2wbm_addr[2:0]);
350			`PCX_SZ_2B: wbm_sel_o = (2'b11<<(spc2wbm_addr[2:1]<<1));
351			`PCX_SZ_4B: wbm_sel_o = (4'b1111<<(spc2wbm_addr[2]<<2));
352			`PCX_SZ_8B: wbm_sel_o = 8'b11111111;
353			`PCX_SZ_16B: wbm_sel_o = 8'b11111111; // Requires a 2nd access
354			`default: wbm_sel_o = 8'b00000000;`
355			`endcase`
356	4	fafa1971
357	11	fafa1971	end else if(spc2wbm_type==`STORE_RQ) begin
358
359			`// For data store use the provided data`
360			`wbm_we_o = 1;`
361	4	fafa1971	`case(spc2wbm_size)`
362			`PCX_SZ_1B: wbm_sel_o = (1'b1<<spc2wbm_addr[2:0]);
363			`PCX_SZ_2B: wbm_sel_o = (2'b11<<(spc2wbm_addr[2:1]<<1));
364			`PCX_SZ_4B: wbm_sel_o = (4'b1111<<(spc2wbm_addr[2]<<2));
365			`PCX_SZ_8B: wbm_sel_o = 8'b11111111;
366			`PCX_SZ_16B: wbm_sel_o = 8'b11111111; // Requires a 2nd access
367			`default: wbm_sel_o = 8'b00000000;`
368			`endcase`
369
370	11	fafa1971	`end else begin`
371
372			`wbm_we_o = 1;`
373			`wbm_sel_o = 8'b00000000;`
374
375	4	fafa1971	`end`
376
377			`// synopsys translate_off`
378			`// Print details of request packet`
379	11	fafa1971	`$display("INFO: SPC2WBM: Valid bit is %X", spc2wbm_valid);`
380	4	fafa1971	`case(spc2wbm_type)`
381			`LOAD_RQ: $display("INFO: SPC2WBM: Request of Type LOAD_RQ");
382			`IMISS_RQ: $display("INFO: SPC2WBM: Request of Type IMISS_RQ");
383			`STORE_RQ: $display("INFO: SPC2WBM: Request of Type STORE_RQ");
384			`CAS1_RQ: $display("INFO: SPC2WBM: Request of Type CAS1_RQ");
385			`CAS2_RQ: $display("INFO: SPC2WBM: Request of Type CAS2_RQ");
386			`SWAP_RQ: $display("INFO: SPC2WBM: Request of Type SWAP_RQ");
387			`STRLOAD_RQ: $display("INFO: SPC2WBM: Request of Type STRLOAD_RQ");
388			`STRST_RQ: $display("INFO: SPC2WBM: Request of Type STRST_RQ");
389			`STQ_RQ: $display("INFO: SPC2WBM: Request of Type STQ_RQ");
390			`INT_RQ: $display("INFO: SPC2WBM: Request of Type INT_RQ");
391			`FWD_RQ: $display("INFO: SPC2WBM: Request of Type FWD_RQ");
392			`FWD_RPY: $display("INFO: SPC2WBM: Request of Type FWD_RPY");
393			`RSVD_RQ: $display("INFO: SPC2WBM: Request of Type RSVD_RQ");
394			`default: $display("INFO: SPC2WBM: Request of Type Unknown");`
395	11	fafa1971	`endcase`
396			`$display("INFO: SPC2WBM: Non-Cacheable is %X", spc2wbm_nc);`
397			`$display("INFO: SPC2WBM: CPU-ID is %X", spc2wbm_cpu_id);`
398	4	fafa1971	`$display("INFO: SPC2WBM: Thread is %X", spc2wbm_thread);`
399	11	fafa1971	`$display("INFO: SPC2WBM: Invalidate All is %X", spc2wbm_invalidate);`
400			`$display("INFO: SPC2WBM: Replaced L1 Way is %X", spc2wbm_way);`
401	4	fafa1971	`case(spc2wbm_size)`
402			`PCX_SZ_1B: $display("INFO: SPC2WBM: Request size is 1 Byte");
403			`PCX_SZ_2B: $display("INFO: SPC2WBM: Request size is 2 Bytes");
404			`PCX_SZ_4B: $display("INFO: SPC2WBM: Request size is 4 Bytes");
405			`PCX_SZ_8B: $display("INFO: SPC2WBM: Request size is 8 Bytes");
406			`PCX_SZ_16B: $display("INFO: SPC2WBM: Request size is 16 Bytes");
407			`default: $display("INFO: SPC2WBM: Request size is Unknown");`
408			`endcase`
409			`$display("INFO: SPC2WBM: Address is %X", spc2wbm_addr);`
410			`$display("INFO: SPC2WBM: Data is %X", spc2wbm_data);`
411			`$display("INFO: SPC2WBM: Request forwarded from SPARC Core to Wishbone Master");`
412			`// synopsys translate_on`
413
414			`// Unconditional state change`
415			state = `STATE_REQUEST_GRANTED;
416
417			`// FSM State 4: STATE_REQUEST_GRANTED`
418			`// Wishbone access completed, latch the incoming data`
419			end else if(state==`STATE_REQUEST_GRANTED) begin
420
421			`// Wait until Wishbone access completes`
422			`if(wbm_ack_i==1) begin`
423
424			`// Clear previously modified outputs`
425			`if(spc2wbm_atom==0) wbm_cycle_o = 0;`
426			`wbm_strobe_o = 0;`
427			`wbm_we_o = 0;`
428			`wbm_addr_o = 64'b0;`
429			`wbm_data_o = 64'b0;`
430			`wbm_sel_o = 8'b0;`
431
432			`// Latch the data and set up the return packet for the SPARC Core`
433			`wbm2spc_valid = 1;`
434			`case(spc2wbm_type)`
435			`IMISS_RQ: begin
436			wbm2spc_type = `IFILL_RET; // I-Cache Miss
437			`end`
438			`LOAD_RQ: begin
439	11	fafa1971	wbm2spc_type = `LOAD_RET; // Load
440	4	fafa1971	`end`
441			`STORE_RQ: begin
442			wbm2spc_type = `ST_ACK; // Store
443			`end`
444			`endcase`
445			`wbm2spc_error = 0;`
446	11	fafa1971	`wbm2spc_nc = spc2wbm_nc;`
447	4	fafa1971	`wbm2spc_thread = spc2wbm_thread;`
448	11	fafa1971	`wbm2spc_way_valid = 0;`
449			`wbm2spc_way = 0;`
450			`if(spc2wbm_addr[3]==0) wbm2spc_data = { wbm_data_i, 64'b0 };`
451			`else wbm2spc_data = { 64'b0, wbm_data_i };`
452	4	fafa1971
453			`// See if other 64-bit Wishbone accesses are required`
454			`if(`
455			`// Instruction miss directed to RAM expects 256 bits`
456			( (spc2wbm_type==`IMISS_RQ)&&(spc2wbm_region!=5'b10000) ) \|\|
457			`// Data access of 128 bits`
458			( (spc2wbm_type==`LOAD_RQ)&&(spc2wbm_size==`PCX_SZ_16B) )
459			`)`
460			state = `STATE_ACCESS2_BEGIN;
461			`else`
462			state = `STATE_PACKET_READY;
463
464			end else state = `STATE_REQUEST_GRANTED;
465
466			`// FSM State 5: STATE_ACCESS2_BEGIN`
467			`// If needed start a second read access to the Wishbone bus`
468			end else if(state==`STATE_ACCESS2_BEGIN) begin
469
470			`// Issue a second request on the Wishbone bus`
471			`wbm_cycle_o = 1;`
472			`wbm_strobe_o = 1;`
473			`wbm_we_o = 0;`
474			wbm_addr_o = { spc2wbm_region, 19'b0, spc2wbm_addr[`PCX_AD_HI-`PCX_AD_LO:4], 4'b1000 }; // 2nd doubleword inside the same quadword
475			`wbm_data_o = 64'b0;`
476			`wbm_sel_o = 8'b11111111;`
477
478			`// Unconditional state change`
479			state = `STATE_ACCESS2_END;
480
481			`// FSM State 6: STATE_ACCESS2_END`
482			`// Latch the second data returning from Wishbone when ready`
483			end else if(state==`STATE_ACCESS2_END) begin
484
485			`// Wait until Wishbone access completes`
486			`if(wbm_ack_i==1) begin`
487
488			`// Clear previously modified outputs`
489			`if(spc2wbm_atom==0) wbm_cycle_o = 0;`
490			`wbm_strobe_o = 0;`
491			`wbm_we_o = 0;`
492			`wbm_addr_o = 64'b0;`
493			`wbm_data_o = 64'b0;`
494			`wbm_sel_o = 8'b0;`
495
496			`// Latch the data and set up the return packet for the SPARC Core`
497			`wbm2spc_data[63:0] = wbm_data_i;`
498
499			`// See if two return packets are required or just one`
500			if(spc2wbm_type==`IMISS_RQ && spc2wbm_region==5'b10000)

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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [s1_top/] [spc2wbm.v] - Blame information for rev 11