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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [s1_top/] [spc2wbm.v] - Blame information for rev 73

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1 4 fafa1971
/*
2
 * Bridge from SPARC Core to Wishbone Master
3
 *
4
 * (C) 2007 Simply RISC LLP
5
 * AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
6
 *
7
 * LICENSE:
8
 * This is a Free Hardware Design; you can redistribute it and/or
9
 * modify it under the terms of the GNU General Public License
10
 * version 2 as published by the Free Software Foundation.
11
 * The above named program is distributed in the hope that it will
12
 * be useful, but WITHOUT ANY WARRANTY; without even the implied
13
 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14
 * See the GNU General Public License for more details.
15
 *
16
 * DESCRIPTION:
17
 * This block implements a bridge from one SPARC Core of the
18
 * OpenSPARC T1 to a master interface that makes use of the
19
 * Wishbone interconnect protocol.
20
 * For informations about Sun Microsystems' OpenSPARC T1
21
 * refer to the web site http://www.opensparc.net
22
 * For informations about OpenCores' Wishbone interconnect
23
 * please refer to the web site http://www.opencores.org
24
 */
25
 
26
`include "s1_defs.h"
27
 
28
module spc2wbm (
29
    sys_clock_i, sys_reset_i, sys_interrupt_source_i,
30
    spc_req_i, spc_atom_i, spc_packetout_i,
31
    spc_grant_o, spc_ready_o, spc_packetin_o, spc_stallreq_o,
32
    wbm_ack_i, wbm_data_i,
33
    wbm_cycle_o, wbm_strobe_o, wbm_we_o, wbm_addr_o, wbm_data_o, wbm_sel_o
34
  );
35
 
36
  /*
37
   * Inputs
38
   */
39
 
40
  // System inputs
41
  input sys_clock_i;                            // System Clock
42
  input sys_reset_i;                            // System Reset
43 11 fafa1971
  input[5:0] sys_interrupt_source_i;            // Encoded Interrupt Source
44 4 fafa1971
 
45
  // SPARC-side inputs connected to the PCX (Processor-to-Cache Xbar) outputs of the SPARC Core
46
  input[4:0] spc_req_i;                         // Request
47
  input spc_atom_i;                             // Atomic Request
48
  input[(`PCX_WIDTH-1):0] spc_packetout_i;      // Outgoing Packet
49
 
50
  // Wishbone Master interface inputs
51
  input wbm_ack_i;                              // Ack
52
  input[(`WB_DATA_WIDTH-1):0] wbm_data_i;       // Data In
53
 
54
  /*
55
   * Registered Outputs
56
   */
57
 
58
  // SPARC-side outputs connected to the CPX (Cache-to-Processor Xbar) inputs of the SPARC Core
59
  output[4:0] spc_grant_o;                      // Grant
60
  reg[4:0] spc_grant_o;                         // Grant
61
  output spc_ready_o;                           // Ready
62
  reg spc_ready_o;                              // Ready
63
  output[`CPX_WIDTH-1:0] spc_packetin_o;        // Incoming Packet
64
  reg[`CPX_WIDTH-1:0] spc_packetin_o;           // Incoming Packet
65
  output spc_stallreq_o;                        // Stall Request
66
  reg spc_stallreq_o;                           // Stall Request
67
 
68
  // Wishbone Master interface outputs
69
  output wbm_cycle_o;                           // Cycle Start
70
  reg wbm_cycle_o;                              // Cycle Start
71
  output wbm_strobe_o;                          // Strobe Request
72
  reg wbm_strobe_o;                             // Strobe Request
73
  output wbm_we_o;                              // Write Enable
74
  reg wbm_we_o;                                 // Write Enable
75
  output[`WB_ADDR_WIDTH-1:0] wbm_addr_o;        // Address Bus
76
  reg[`WB_ADDR_WIDTH-1:0] wbm_addr_o;           // Address Bus
77
  output[`WB_DATA_WIDTH-1:0] wbm_data_o;        // Data Out
78
  reg[`WB_DATA_WIDTH-1:0] wbm_data_o;           // Data Out
79
  output[`WB_DATA_WIDTH/8-1:0] wbm_sel_o;       // Select Output
80
  reg[`WB_DATA_WIDTH/8-1:0] wbm_sel_o;          // Select Output
81
 
82
  /*
83
   * Registers
84
   */
85
 
86
  // Registers to latch requests from SPARC Core to Wishbone Master
87
  reg[3:0] state;
88
  reg[4:0] spc2wbm_region;                                             // Target region number (one-hot encoded)
89 12 fafa1971
  reg spc2wbm_atomic;                                                  // Request is Atomic
90 4 fafa1971
  reg[(`PCX_WIDTH-1):0] spc2wbm_packet;                                // Latched Packet
91
 
92
  // Wishbone Master to SPARC Core info used to encode the return packet
93
  reg wbm2spc_valid;                                                   // Valid
94
  reg[(`CPX_RQ_HI-`CPX_RQ_LO):0] wbm2spc_type;                         // Request type
95 12 fafa1971
  reg wbm2spc_miss;                                                    // L2 Miss
96
  reg[(`CPX_ERR_HI-`CPX_ERR_LO-1):0] wbm2spc_error;                    // Error
97 11 fafa1971
  reg wbm2spc_nc;                                                      // Non-Cacheable
98 4 fafa1971
  reg[(`CPX_TH_HI-`CPX_TH_LO):0] wbm2spc_thread;                       // Thread
99 11 fafa1971
  reg wbm2spc_way_valid;                                               // L2 Way Valid
100
  reg[(`CPX_WY_HI-`CPX_WY_LO):0] wbm2spc_way;                          // Replaced L2 Way
101 12 fafa1971
  reg wbm2spc_boot_fetch;                                              // Fetch for Boot
102
  reg wbm2spc_atomic;                                                  // Atomic LD/ST or 2nd IFill packet
103
  reg wbm2spc_pfl;                                                     // PFL
104 4 fafa1971
  reg[(`CPX_DA_HI-`CPX_DA_LO):0] wbm2spc_data;                         // Load Data
105 11 fafa1971
  reg[6:0] wbm2spc_interrupt_source;                                   // Encoded Interrupt Source
106
  reg wbm2spc_interrupt_new;                                           // New Interrupt Pending
107
 
108 4 fafa1971
  /*
109
   * Wires
110
   */
111
 
112
  // Decoded SPARC Core to Wishbone Master info
113
  wire spc2wbm_req;                                                     // Request
114
  wire spc2wbm_valid;                                                   // Valid
115
  wire[(`PCX_RQ_HI-`PCX_RQ_LO):0] spc2wbm_type;                         // Request type
116 11 fafa1971
  wire spc2wbm_nc;                                                      // Non-Cacheable
117 4 fafa1971
  wire[(`PCX_CP_HI-`PCX_CP_LO):0] spc2wbm_cpu_id;                       // CPU ID
118
  wire[(`PCX_TH_HI-`PCX_TH_LO):0] spc2wbm_thread;                       // Thread
119 11 fafa1971
  wire spc2wbm_invalidate;                                              // Invalidate all
120
  wire[(`PCX_WY_HI-`PCX_WY_LO):0] spc2wbm_way;                          // Replaced L1 Way
121 4 fafa1971
  wire[(`PCX_SZ_HI-`PCX_SZ_LO):0] spc2wbm_size;                         // Load/Store size
122
  wire[(`PCX_AD_HI-`PCX_AD_LO):0] spc2wbm_addr;                         // Address
123
  wire[(`PCX_DA_HI-`PCX_DA_LO):0] spc2wbm_data;                         // Store Data
124
 
125
  // Return packets assembled with various fields
126 11 fafa1971
  wire[`CPX_WIDTH-1:0] wbm2spc_packet;                                  // Incoming Packet
127 4 fafa1971
 
128
  /*
129
   * Encode/decode incoming info
130
   *
131
   * Legenda: available constants for some of the PCX/CPX fields.
132
   *
133
   * spc2wbm_size (3 bits) is one of:
134
   * - PCX_SZ_1B
135
   * - PCX_SZ_2B
136
   * - PCX_SZ_4B
137
   * - PCX_SZ_8B
138
   * - PCX_SZ_16B (Read accesses only)
139
   *
140
   * spc2wbm_type (5 bits) is one of:
141
   * { LOAD_RQ, IMISS_RQ, STORE_RQ, CAS1_RQ, CAS2_RQ, SWAP_RQ, STRLOAD_RQ, STRST_RQ, STQ_RQ,
142
   *   INT_RQ, FWD_RQ, FWD_RPY, RSVD_RQ }
143
   *
144
   * wbm2spc_type (4 bits) is one of:
145
   * { LOAD_RET, INV_RET, ST_ACK, AT_ACK, INT_RET, TEST_RET, FP_RET, IFILL_RET, EVICT_REQ,
146
   *   ERR_RET, STRLOAD_RET, STRST_ACK, FWD_RQ_RET, FWD_RPY_RET, RSVD_RET }
147
   *
148
   */
149
 
150
  // Decode info arriving from the SPC side
151
  assign spc2wbm_req = ( spc_req_i[4] | spc_req_i[3] | spc_req_i[2] | spc_req_i[1] | spc_req_i[0] );
152
  assign spc2wbm_valid = spc2wbm_packet[`PCX_VLD];
153
  assign spc2wbm_type = spc2wbm_packet[`PCX_RQ_HI:`PCX_RQ_LO];
154 11 fafa1971
  assign spc2wbm_nc = spc2wbm_packet[`PCX_NC];
155 4 fafa1971
  assign spc2wbm_cpu_id = spc2wbm_packet[`PCX_CP_HI:`PCX_CP_LO];
156
  assign spc2wbm_thread = spc2wbm_packet[`PCX_TH_HI:`PCX_TH_LO];
157 11 fafa1971
  assign spc2wbm_invalidate = spc2wbm_packet[`PCX_INVALL];
158
  assign spc2wbm_way = spc2wbm_packet[`PCX_WY_HI:`PCX_WY_LO];
159 4 fafa1971
  assign spc2wbm_size = spc2wbm_packet[`PCX_SZ_HI:`PCX_SZ_LO];
160
  assign spc2wbm_addr = spc2wbm_packet[`PCX_AD_HI:`PCX_AD_LO];
161
  assign spc2wbm_data = spc2wbm_packet[`PCX_DA_HI:`PCX_DA_LO];
162
 
163
  // Encode info going to the SPC side assembling return packets
164 12 fafa1971
  assign wbm2spc_packet = { wbm2spc_valid, wbm2spc_type, wbm2spc_miss, wbm2spc_error, wbm2spc_nc, wbm2spc_thread,
165
    wbm2spc_way_valid, wbm2spc_way, wbm2spc_boot_fetch, wbm2spc_atomic, wbm2spc_pfl, wbm2spc_data };
166 4 fafa1971
 
167
  /*
168
   * State Machine
169
   */
170
 
171
  always @(posedge sys_clock_i) begin
172
 
173
    // Initialization
174
    if(sys_reset_i==1) begin
175
 
176
      // Clear outputs going to SPARC Core inputs
177 51 fafa1971
      spc_grant_o <= 5'b00000;
178
      spc_ready_o <= 0;
179
      spc_packetin_o <= 0;
180
      spc_stallreq_o <= 0;
181 4 fafa1971
 
182
      // Clear Wishbone Master interface outputs
183 51 fafa1971
      wbm_cycle_o <= 0;
184
      wbm_strobe_o <= 0;
185
      wbm_we_o <= 0;
186
      wbm_addr_o <= 64'b0;
187
      wbm_data_o <= 64'b0;
188
      wbm_sel_o <= 8'b0;
189 4 fafa1971
 
190
      // Prepare wakeup packet for SPARC Core, the resulting output is
191 51 fafa1971
      // spc_packetin_o <= `CPX_WIDTH'h1700000000000000000000000000000010001;
192
      wbm2spc_valid <= 1;
193
      wbm2spc_type <= `INT_RET;
194
      wbm2spc_miss <= 0;
195
      wbm2spc_error <= 0;
196
      wbm2spc_nc <= 0;
197
      wbm2spc_thread <= 0;
198
      wbm2spc_way_valid <= 0;
199
      wbm2spc_way <= 0;
200
      wbm2spc_boot_fetch <= 0;
201
      wbm2spc_atomic <= 0;
202
      wbm2spc_pfl <= 0;
203
      wbm2spc_data <= 64'h10001;
204
      wbm2spc_interrupt_source <= 7'h0;
205
      wbm2spc_interrupt_new <= 1'b0;
206
 
207 4 fafa1971
      // Clear state machine
208 51 fafa1971
      state <= `STATE_WAKEUP;
209 4 fafa1971
 
210
    end else begin
211
 
212
      // FSM State 0: STATE_WAKEUP
213
      // Send to the SPARC Core the wakeup packet
214
      if(state==`STATE_WAKEUP) begin
215
 
216
        // Send wakeup packet
217 51 fafa1971
        spc_ready_o <= 1;
218
        spc_packetin_o <= wbm2spc_packet;
219 4 fafa1971
 
220
// synopsys translate_off
221
        // Display comment
222 51 fafa1971
`ifdef DEBUG
223 4 fafa1971
        $display("INFO: SPC2WBM: SPARC Core to Wishbone Master bridge starting...");
224
        $display("INFO: SPC2WBM: Wakeup packet sent to SPARC Core");
225 51 fafa1971
`endif
226 4 fafa1971
// synopsys translate_on
227
 
228
        // Unconditional state change
229 51 fafa1971
        state <= `STATE_IDLE;
230 4 fafa1971
 
231
      // FSM State 1: STATE_IDLE
232
      // Wait for a request from the SPARC Core
233
      // If available send an interrupt packet to the Core
234
      end else if(state==`STATE_IDLE) begin
235
 
236
        // Check if there's an incoming request
237
        if(spc2wbm_req==1) begin
238
 
239
          // Clear previously modified outputs
240 51 fafa1971
          spc_ready_o <= 0;
241
          spc_packetin_o <= 0;
242 4 fafa1971
 
243
          // Stall other requests from the SPARC Core
244 51 fafa1971
          spc_stallreq_o <= 1;
245 4 fafa1971
 
246
          // Latch target region and atomicity
247 51 fafa1971
          spc2wbm_region <= spc_req_i;
248
          spc2wbm_atomic <= spc_atom_i;
249 4 fafa1971
 
250
          // Jump to next state
251 51 fafa1971
          state <= `STATE_REQUEST_LATCHED;
252 4 fafa1971
 
253
        // See if the interrupt vector has changed
254
        end else if(sys_interrupt_source_i!=wbm2spc_interrupt_source) begin
255
 
256
          // Set the flag for next cycle
257 51 fafa1971
          wbm2spc_interrupt_new <= 1;
258 4 fafa1971
 
259
          // Prepare the interrupt packet for the SPARC Core
260 51 fafa1971
          wbm2spc_valid <= 1;
261
          wbm2spc_type <= `INT_RET;
262
          wbm2spc_miss <= 0;
263
          wbm2spc_error <= 0;
264
          wbm2spc_nc <= 0;
265
          wbm2spc_thread <= 0;
266
          wbm2spc_way_valid <= 0;
267
          wbm2spc_way <= 0;
268
          wbm2spc_boot_fetch <= 0;
269
          wbm2spc_atomic <= 0;
270
          wbm2spc_pfl <= 0;
271 4 fafa1971
 
272
          // Stall other requests from the SPARC Core
273 51 fafa1971
          spc_stallreq_o <= 1;
274 4 fafa1971
 
275
        // Next cycle see if there's an int to be forwarded to the Core
276 11 fafa1971
        end else if(wbm2spc_interrupt_source!=6'b000000 && wbm2spc_interrupt_new) begin
277 4 fafa1971
 
278
          // Clean the flag
279 51 fafa1971
          wbm2spc_interrupt_new <= 0;
280 4 fafa1971
 
281
          // Send the interrupt packet to the Core
282 51 fafa1971
          spc_ready_o <= 1;
283
          spc_packetin_o <= wbm2spc_packet;
284 4 fafa1971
 
285
          // Stall other requests from the SPARC Core
286 51 fafa1971
          spc_stallreq_o <= 1;
287 4 fafa1971
 
288
          // Stay in this state
289 51 fafa1971
          state <= `STATE_IDLE;
290 4 fafa1971
 
291
        // Nothing to do, stay idle
292
        end else begin
293
 
294
          // Clear previously modified outputs
295 51 fafa1971
          spc_ready_o <= 0;
296
          spc_packetin_o <= 0;
297
          spc_stallreq_o <= 0;
298 4 fafa1971
 
299
          // Stay in this state
300 51 fafa1971
          state <= `STATE_IDLE;
301 4 fafa1971
 
302
        end
303
 
304
      // FSM State 2: STATE_REQUEST_LATCHED
305
      // We've just latched the request
306
      // Now we latch the packet
307
      // Start granting the request
308
      end else if(state==`STATE_REQUEST_LATCHED) begin
309
 
310
        // Latch the incoming packet
311 51 fafa1971
        spc2wbm_packet <= spc_packetout_i;
312 4 fafa1971
 
313
        // Grant the request to the SPARC Core
314 51 fafa1971
        spc_grant_o <= spc2wbm_region;
315 4 fafa1971
 
316
// synopsys translate_off
317
        // Print details of SPARC Core request
318 51 fafa1971
`ifdef DEBUG
319 4 fafa1971
        $display("INFO: SPC2WBM: *** NEW REQUEST FROM SPARC CORE ***");
320
        if(spc2wbm_region[0]==1) $display("INFO: SPC2WBM: Request to RAM Bank 0");
321
        else if(spc2wbm_region[1]==1) $display("INFO: SPC2WBM: Request to RAM Bank 1");
322
        else if(spc2wbm_region[2]==1) $display("INFO: SPC2WBM: Request to RAM Bank 2");
323
        else if(spc2wbm_region[3]==1) $display("INFO: SPC2WBM: Request to RAM Bank 3");
324
        else if(spc2wbm_region[4]==1) $display("INFO: SPC2WBM: Request targeted to I/O Block");
325
        else $display("INFO: SPC2WBM: Request to target region unknown");
326 12 fafa1971
        if(spc2wbm_atomic==1) $display("INFO: SPC2WBM: Request is ATOMIC");
327 4 fafa1971
        else $display("INFO: SPC2WBM: Request is not atomic");
328 51 fafa1971
`endif
329 4 fafa1971
// synopsys translate_on
330
 
331
        // Unconditional state change
332 51 fafa1971
        state <= `STATE_PACKET_LATCHED;
333 4 fafa1971
 
334
      // FSM State 3: STATE_PACKET_LATCHED
335
      // The packet has already been latched
336
      // Decode this packet to build the request for the Wishbone bus
337
      // The grant of the request to the SPARC Core has been completed
338
      end else if(state==`STATE_PACKET_LATCHED) begin
339
 
340
        // Clear previously modified outputs
341 51 fafa1971
        spc_grant_o <= 5'b0;
342 4 fafa1971
 
343
        // Issue a request on the Wishbone bus
344 51 fafa1971
        wbm_cycle_o <= 1;
345
        wbm_strobe_o <= 1;
346
        wbm_addr_o <= { spc2wbm_region, 19'b0, spc2wbm_addr[`PCX_AD_HI-`PCX_AD_LO:3], 3'b000 };
347
        wbm_data_o <= spc2wbm_data;
348 4 fafa1971
 
349
        // Handle write enable and byte select
350
        if(spc2wbm_type==`IMISS_RQ) begin
351
 
352
          // For instruction miss always read memory
353 51 fafa1971
          wbm_we_o <= 0;
354 4 fafa1971
          if(spc2wbm_region==5'b10000)
355
            // For accesses to SSI ROM only 32 bits are required
356 51 fafa1971
            wbm_sel_o <= (4'b1111<<(spc2wbm_addr[2]<<2));
357 4 fafa1971
          else
358
            // For accesses to RAM 256 bits are expected (2 ret packets)
359 51 fafa1971
            wbm_sel_o <= 8'b11111111;
360 4 fafa1971
 
361 11 fafa1971
        end else if(spc2wbm_type==`LOAD_RQ) begin
362
 
363
          // For data load use the provided data
364 51 fafa1971
          wbm_we_o <= 0;
365 11 fafa1971
          case(spc2wbm_size)
366 51 fafa1971
            `PCX_SZ_1B: wbm_sel_o <= (1'b1<<spc2wbm_addr[2:0]);
367
            `PCX_SZ_2B: wbm_sel_o <= (2'b11<<(spc2wbm_addr[2:1]<<1));
368
            `PCX_SZ_4B: wbm_sel_o <= (4'b1111<<(spc2wbm_addr[2]<<2));
369
            `PCX_SZ_8B: wbm_sel_o <= 8'b11111111;
370
            `PCX_SZ_16B: wbm_sel_o <= 8'b11111111;  // Requires a 2nd access
371
            default: wbm_sel_o <= 8'b00000000;
372 11 fafa1971
          endcase
373 4 fafa1971
 
374 11 fafa1971
        end else if(spc2wbm_type==`STORE_RQ) begin
375
 
376
          // For data store use the provided data
377 51 fafa1971
          wbm_we_o <= 1;
378 4 fafa1971
          case(spc2wbm_size)
379 51 fafa1971
            `PCX_SZ_1B: wbm_sel_o <= (1'b1<<spc2wbm_addr[2:0]);
380
            `PCX_SZ_2B: wbm_sel_o <= (2'b11<<(spc2wbm_addr[2:1]<<1));
381
            `PCX_SZ_4B: wbm_sel_o <= (4'b1111<<(spc2wbm_addr[2]<<2));
382
            `PCX_SZ_8B: wbm_sel_o <= 8'b11111111;
383
            `PCX_SZ_16B: wbm_sel_o <= 8'b11111111;  // Requires a 2nd access
384
            default: wbm_sel_o <= 8'b00000000;
385 4 fafa1971
          endcase
386
 
387 11 fafa1971
        end else begin
388
 
389 51 fafa1971
          wbm_we_o <= 1;
390
          wbm_sel_o <= 8'b00000000;
391 11 fafa1971
 
392 4 fafa1971
        end
393
 
394
// synopsys translate_off
395
        // Print details of request packet
396 51 fafa1971
`ifdef DEBUG
397 11 fafa1971
        $display("INFO: SPC2WBM: Valid bit is %X", spc2wbm_valid);
398 4 fafa1971
        case(spc2wbm_type)
399
          `LOAD_RQ: $display("INFO: SPC2WBM: Request of Type LOAD_RQ");
400
          `IMISS_RQ: $display("INFO: SPC2WBM: Request of Type IMISS_RQ");
401
          `STORE_RQ: $display("INFO: SPC2WBM: Request of Type STORE_RQ");
402
          `CAS1_RQ: $display("INFO: SPC2WBM: Request of Type CAS1_RQ");
403
          `CAS2_RQ: $display("INFO: SPC2WBM: Request of Type CAS2_RQ");
404
          `SWAP_RQ: $display("INFO: SPC2WBM: Request of Type SWAP_RQ");
405
          `STRLOAD_RQ: $display("INFO: SPC2WBM: Request of Type STRLOAD_RQ");
406
          `STRST_RQ: $display("INFO: SPC2WBM: Request of Type STRST_RQ");
407
          `STQ_RQ: $display("INFO: SPC2WBM: Request of Type STQ_RQ");
408
          `INT_RQ: $display("INFO: SPC2WBM: Request of Type INT_RQ");
409
          `FWD_RQ: $display("INFO: SPC2WBM: Request of Type FWD_RQ");
410
          `FWD_RPY: $display("INFO: SPC2WBM: Request of Type FWD_RPY");
411
          `RSVD_RQ: $display("INFO: SPC2WBM: Request of Type RSVD_RQ");
412
          default: $display("INFO: SPC2WBM: Request of Type Unknown");
413 11 fafa1971
        endcase
414 12 fafa1971
        $display("INFO: SPC2WBM: Non-Cacheable bit is %X", spc2wbm_nc);
415 11 fafa1971
        $display("INFO: SPC2WBM: CPU-ID is %X", spc2wbm_cpu_id);
416 4 fafa1971
        $display("INFO: SPC2WBM: Thread is %X", spc2wbm_thread);
417 11 fafa1971
        $display("INFO: SPC2WBM: Invalidate All is %X", spc2wbm_invalidate);
418
        $display("INFO: SPC2WBM: Replaced L1 Way is %X", spc2wbm_way);
419 4 fafa1971
        case(spc2wbm_size)
420
          `PCX_SZ_1B: $display("INFO: SPC2WBM: Request size is 1 Byte");
421
          `PCX_SZ_2B: $display("INFO: SPC2WBM: Request size is 2 Bytes");
422
          `PCX_SZ_4B: $display("INFO: SPC2WBM: Request size is 4 Bytes");
423
          `PCX_SZ_8B: $display("INFO: SPC2WBM: Request size is 8 Bytes");
424
          `PCX_SZ_16B: $display("INFO: SPC2WBM: Request size is 16 Bytes");
425
          default: $display("INFO: SPC2WBM: Request size is Unknown");
426
        endcase
427
        $display("INFO: SPC2WBM: Address is %X", spc2wbm_addr);
428
        $display("INFO: SPC2WBM: Data is %X", spc2wbm_data);
429 51 fafa1971
`endif
430 4 fafa1971
// synopsys translate_on
431
 
432
        // Unconditional state change
433 51 fafa1971
        state <= `STATE_REQUEST_GRANTED;
434 4 fafa1971
 
435
      // FSM State 4: STATE_REQUEST_GRANTED
436
      // Wishbone access completed, latch the incoming data
437
      end else if(state==`STATE_REQUEST_GRANTED) begin
438
 
439
        // Wait until Wishbone access completes
440
        if(wbm_ack_i==1) begin
441
 
442
          // Clear previously modified outputs
443 51 fafa1971
          if(spc2wbm_atomic==0) wbm_cycle_o <= 0;
444
          wbm_strobe_o <= 0;
445
          wbm_we_o <= 0;
446
          wbm_addr_o <= 64'b0;
447
          wbm_data_o <= 64'b0;
448
          wbm_sel_o <= 8'b0;
449 4 fafa1971
 
450
          // Latch the data and set up the return packet for the SPARC Core
451 51 fafa1971
          wbm2spc_valid <= 1;
452 4 fafa1971
          case(spc2wbm_type)
453
            `IMISS_RQ: begin
454 51 fafa1971
              wbm2spc_type <= `IFILL_RET; // I-Cache Miss
455
              wbm2spc_atomic <= 0;
456 4 fafa1971
            end
457
            `LOAD_RQ: begin
458 51 fafa1971
              wbm2spc_type <= `LOAD_RET;  // Load
459
              wbm2spc_atomic <= spc2wbm_atomic;
460 4 fafa1971
            end
461
            `STORE_RQ: begin
462 51 fafa1971
              wbm2spc_type <= `ST_ACK;    // Store
463
              wbm2spc_atomic <= spc2wbm_atomic;
464 4 fafa1971
            end
465
          endcase
466 51 fafa1971
          wbm2spc_miss <= 0;
467
          wbm2spc_error <= 0;
468
          wbm2spc_nc <= spc2wbm_nc;
469
          wbm2spc_thread <= spc2wbm_thread;
470
          wbm2spc_way_valid <= 0;
471
          wbm2spc_way <= 0;
472
          if(spc2wbm_region==5'b10000) wbm2spc_boot_fetch <= 1;
473
          else wbm2spc_boot_fetch <= 0;
474
          wbm2spc_pfl <= 0;
475
          if(spc2wbm_addr[3]==0) wbm2spc_data <= { wbm_data_i, 64'b0 };
476
          else wbm2spc_data <= { 64'b0, wbm_data_i };
477 4 fafa1971
 
478
          // See if other 64-bit Wishbone accesses are required
479
          if(
480
              // Instruction miss directed to RAM expects 256 bits
481
              ( (spc2wbm_type==`IMISS_RQ)&&(spc2wbm_region!=5'b10000) ) ||
482
              // Data access of 128 bits
483
              ( (spc2wbm_type==`LOAD_RQ)&&(spc2wbm_size==`PCX_SZ_16B) )
484
            )
485 51 fafa1971
            state <= `STATE_ACCESS2_BEGIN;
486 4 fafa1971
          else
487 51 fafa1971
            state <= `STATE_PACKET_READY;
488 4 fafa1971
 
489 51 fafa1971
        end else state <= `STATE_REQUEST_GRANTED;
490 4 fafa1971
 
491
      // FSM State 5: STATE_ACCESS2_BEGIN
492
      // If needed start a second read access to the Wishbone bus
493
      end else if(state==`STATE_ACCESS2_BEGIN) begin
494
 
495
        // Issue a second request on the Wishbone bus
496 51 fafa1971
        wbm_cycle_o <= 1;
497
        wbm_strobe_o <= 1;
498
        wbm_we_o <= 0;
499
        wbm_addr_o <= { spc2wbm_region, 19'b0, spc2wbm_addr[`PCX_AD_HI-`PCX_AD_LO:4], 4'b1000 };  // 2nd doubleword inside the same quadword
500
        wbm_data_o <= 64'b0;
501
        wbm_sel_o <= 8'b11111111;
502 4 fafa1971
 
503
        // Unconditional state change
504 51 fafa1971
        state <= `STATE_ACCESS2_END;
505 4 fafa1971
 
506
      // FSM State 6: STATE_ACCESS2_END
507
      // Latch the second data returning from Wishbone when ready
508
      end else if(state==`STATE_ACCESS2_END) begin
509
 
510
        // Wait until Wishbone access completes
511
        if(wbm_ack_i==1) begin
512
 
513
          // Clear previously modified outputs
514 51 fafa1971
          if(spc2wbm_atomic==0) wbm_cycle_o <= 0;
515
          wbm_strobe_o <= 0;
516
          wbm_we_o <= 0;
517
          wbm_addr_o <= 64'b0;
518
          wbm_data_o <= 64'b0;
519
          wbm_sel_o <= 8'b0;
520 4 fafa1971
 
521
          // Latch the data and set up the return packet for the SPARC Core
522 51 fafa1971
          wbm2spc_data[63:0] <= wbm_data_i;
523 4 fafa1971
 
524
          // See if two return packets are required or just one
525
          if(spc2wbm_type==`IMISS_RQ && spc2wbm_region==5'b10000)
526 51 fafa1971
            state <= `STATE_PACKET_READY;
527 4 fafa1971
          else
528 51 fafa1971
            state <= `STATE_ACCESS3_BEGIN;
529 4 fafa1971
 
530 51 fafa1971
        end else state <= `STATE_ACCESS2_END;
531 4 fafa1971
 
532
      // FSM State 7: STATE_ACCESS3_BEGIN
533
      // If needed start a third read access to the Wishbone bus
534
      // In the meanwhile we can return the first 128-bit packet
535
      end else if(state==`STATE_ACCESS3_BEGIN) begin
536
 
537
        // Return the packet to the SPARC Core
538 51 fafa1971
        spc_ready_o <= 1;
539
        spc_packetin_o <= wbm2spc_packet;
540 4 fafa1971
 
541
        // Issue a third request on the Wishbone bus
542 51 fafa1971
        wbm_cycle_o <= 1;
543
        wbm_strobe_o <= 1;
544
        wbm_we_o <= 0;
545
        wbm_addr_o <= { spc2wbm_region, 19'b0, spc2wbm_addr[`PCX_AD_HI-`PCX_AD_LO:5], 5'b10000 };  // 3nd doubleword inside the same 256-bit data
546
        wbm_data_o <= 64'b0;
547
        wbm_sel_o <= 8'b11111111;
548 4 fafa1971
 
549
// synopsys translate_off
550
        // Print details of return packet
551 51 fafa1971
`ifdef DEBUG
552 12 fafa1971
        $display("INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE ***");
553
        $display("INFO: WBM2SPC: Valid bit is %X", wbm2spc_valid);
554 4 fafa1971
        case(wbm2spc_type)
555
          `IFILL_RET: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
556
          `LOAD_RET: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
557
          `ST_ACK: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
558
          default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
559
        endcase
560 12 fafa1971
        $display("INFO: WBM2SPC: L2 Miss is %X", wbm2spc_miss);
561 11 fafa1971
        $display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
562 12 fafa1971
        $display("INFO: WBM2SPC: Non-Cacheable bit is %X", wbm2spc_nc);
563 4 fafa1971
        $display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
564 11 fafa1971
        $display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
565
        $display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
566 12 fafa1971
        $display("INFO: WBM2SPC: Fetch for Boot is %X", wbm2spc_boot_fetch);
567
        $display("INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is %X", wbm2spc_atomic);
568
        $display("INFO: WBM2SPC: PFL is %X", wbm2spc_pfl);
569 4 fafa1971
        $display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
570 51 fafa1971
`endif
571 4 fafa1971
// synopsys translate_on
572
 
573
        // Unconditional state change
574 51 fafa1971
        state <= `STATE_ACCESS3_END;
575 4 fafa1971
 
576
      // FSM State 8: STATE_ACCESS3_END
577
      // Latch the second data returning from Wishbone when ready
578
      end else if(state==`STATE_ACCESS3_END) begin
579
 
580
        // Clear previously modified outputs
581 51 fafa1971
        spc_ready_o <= 0;
582 4 fafa1971
 
583
        // Wait until Wishbone access completes
584
        if(wbm_ack_i==1) begin
585
 
586
          // Clear previously modified outputs
587 51 fafa1971
          if(spc2wbm_atomic==0) wbm_cycle_o <= 0;
588
          wbm_strobe_o <= 0;
589
          wbm_we_o <= 0;
590
          wbm_addr_o <= 64'b0;
591
          wbm_data_o <= 64'b0;
592
          wbm_sel_o <= 8'b0;
593 4 fafa1971
 
594
          // Latch the data and set up the return packet for the SPARC Core
595 51 fafa1971
          wbm2spc_data <= { wbm_data_i, 64'b0 };
596 4 fafa1971
 
597
          // Jump to next state
598 51 fafa1971
          state <= `STATE_ACCESS4_BEGIN;
599 4 fafa1971
 
600 51 fafa1971
        end else state <= `STATE_ACCESS3_END;
601 4 fafa1971
 
602
      // FSM State 9: STATE_ACCESS4_BEGIN
603
      // If needed start a second read access to the Wishbone bus
604
      end else if(state==`STATE_ACCESS4_BEGIN) begin
605
 
606
        // Issue a fourth request on the Wishbone bus
607 51 fafa1971
        wbm_cycle_o <= 1;
608
        wbm_strobe_o <= 1;
609
        wbm_we_o <= 0;
610
        wbm_addr_o <= { spc2wbm_region, 19'b0, spc2wbm_addr[`PCX_AD_HI-`PCX_AD_LO:5], 5'b11000 };  // 4th doubleword inside the same 256-bit data
611
        wbm_data_o <= 64'b0;
612
        wbm_sel_o <= 8'b11111111;
613 4 fafa1971
 
614
        // Unconditional state change
615 51 fafa1971
        state <= `STATE_ACCESS4_END;
616 4 fafa1971
 
617
      // FSM State 10: STATE_ACCESS4_END
618
      // Latch the second data returning from Wishbone when ready
619
      end else if(state==`STATE_ACCESS4_END) begin
620
 
621
        // Wait until Wishbone access completes
622
        if(wbm_ack_i==1) begin
623
 
624
          // Clear previously modified outputs
625 51 fafa1971
          if(spc2wbm_atomic==0) wbm_cycle_o <= 0;
626
          wbm_strobe_o <= 0;
627
          wbm_we_o <= 0;
628
          wbm_addr_o <= 64'b0;
629
          wbm_data_o <= 64'b0;
630
          wbm_sel_o <= 8'b0;
631 4 fafa1971
 
632
          // Latch the data and set up the return packet for the SPARC Core
633 51 fafa1971
          wbm2spc_atomic <= 1;
634
          wbm2spc_data[63:0] <= wbm_data_i;
635 4 fafa1971
 
636
          // Jump to next state
637 51 fafa1971
          state <= `STATE_PACKET_READY;
638 4 fafa1971
 
639 51 fafa1971
        end else state <= `STATE_ACCESS4_END;
640 4 fafa1971
 
641
      // FSM State 11: STATE_PACKET_READY
642
      // We can start returning the packet to the SPARC Core
643
      end else if(state==`STATE_PACKET_READY) begin
644
 
645
        // Return the packet to the SPARC Core
646 51 fafa1971
        spc_ready_o <= 1;
647
        spc_packetin_o <= wbm2spc_packet;
648 4 fafa1971
 
649
        // Unconditional state change
650 51 fafa1971
        state <= `STATE_IDLE;
651 4 fafa1971
 
652
// synopsys translate_off
653
        // Print details of return packet
654 51 fafa1971
`ifdef DEBUG
655 12 fafa1971
        $display("INFO: WBM2SPC: *** RETURN PACKET TO SPARC CORE ***");
656 11 fafa1971
        $display("INFO: WBM2SPC: Valid bit is %X", wbm2spc_valid);
657 4 fafa1971
        case(wbm2spc_type)
658
          `IFILL_RET: $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
659
          `LOAD_RET: $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
660
          `ST_ACK: $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
661
          default: $display("INFO: WBM2SPC: Return Packet of Type Unknown");
662
        endcase
663 12 fafa1971
        $display("INFO: WBM2SPC: L2 Miss is %X", wbm2spc_miss);
664 11 fafa1971
        $display("INFO: WBM2SPC: Error is %X", wbm2spc_error);
665
        $display("INFO: WBM2SPC: Non-Cacheable bit is %X", wbm2spc_nc);
666 4 fafa1971
        $display("INFO: WBM2SPC: Thread is %X", wbm2spc_thread);
667 11 fafa1971
        $display("INFO: WBM2SPC: Way Valid is %X", wbm2spc_way_valid);
668
        $display("INFO: WBM2SPC: Replaced L2 Way is %X", wbm2spc_way);
669 12 fafa1971
        $display("INFO: WBM2SPC: Fetch for Boot is %X", wbm2spc_boot_fetch);
670
        $display("INFO: WBM2SPC: Atomic LD/ST or 2nd IFill Packet is %X", wbm2spc_atomic);
671
        $display("INFO: WBM2SPC: PFL is %X", wbm2spc_pfl);
672 4 fafa1971
        $display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
673 51 fafa1971
`endif
674 4 fafa1971
// synopsys translate_on
675
 
676
      end
677
    end
678
  end
679
 
680
endmodule
681
 

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