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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [s1_top/] [t1_defs.h] - Blame information for rev 105

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1 4 fafa1971
/*
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* ========== Copyright Header Begin ==========================================
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*
4
* OpenSPARC T1 Processor File: iop.h
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* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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*
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* The above named program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* The above named program is distributed in the hope that it will be
13
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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* General Public License for more details.
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*
17
* You should have received a copy of the GNU General Public
18
* License along with this work; if not, write to the Free Software
19
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20
*
21
* ========== Copyright Header End ============================================
22
*/
23
//-*- verilog -*-
24
////////////////////////////////////////////////////////////////////////
25
/*
26
//
27
//  Description:        Global header file that contain definitions that
28
//                      are common/shared at the IOP chip level
29
*/
30
////////////////////////////////////////////////////////////////////////
31
 
32
 
33
// Address Map Defines
34
// ===================
35
`define ADDR_MAP_HI      39
36
`define ADDR_MAP_LO      32
37
`define IO_ADDR_BIT      39
38
 
39
// CMP space
40
`define DRAM_DATA_LO     8'h00
41
`define DRAM_DATA_HI     8'h7f
42
 
43
// IOP space
44
`define JBUS1            8'h80
45
`define RESERVED_5       8'h81 //`define HASH_TBL_NRAM_CSR 8'h81
46
`define RESERVED_1       8'h82
47
`define RESERVED_6_LO    8'h83 //`define ENET_MAC_CSR     8'h83
48
                               //`define ENET_ING_CSR     8'h84
49
                               //`define ENET_EGR_CMD_CSR 8'h85
50
`define RESERVED_6_HI    8'h86 //`define ENET_EGR_DP_CSR  8'h86
51
`define RESERVED_2_LO    8'h87
52
`define RESERVED_2_HI    8'h92
53
`define RESERVED_7       8'h93 //`define BSC_CSR          8'h93
54
`define RESERVED_3       8'h94
55
`define RESERVED_8       8'h95 //`define RAND_GEN_CSR     8'h95
56
`define CLOCK_UNIT_CSR   8'h96
57
`define DRAM_CSR         8'h97
58
`define IOB_MAN_CSR      8'h98
59
`define TAP_CSR          8'h99
60
`define RESERVED_4_L0    8'h9a
61
`define RESERVED_4_HI    8'h9d
62
`define CPU_ASI          8'h9e
63
`define IOB_INT_CSR      8'h9f
64
 
65
// L2 space
66
`define L2C_CSR_LO       8'ha0
67
`define L2C_CSR_HI       8'hbf
68
 
69
// More IOP space
70
`define JBUS2_LO         8'hc0
71
`define JBUS2_HI         8'hfe
72
`define SPI_CSR          8'hff
73
 
74
 
75
//Cache Crossbar Width and Field Defines
76
//======================================
77
`define PCX_WIDTH       124  //PCX payload packet width
78
`define CPX_WIDTH       145  //CPX payload packet width
79
 
80
`define PCX_VLD         123  //PCX packet valid
81
`define PCX_RQ_HI       122  //PCX request type field
82
`define PCX_RQ_LO       118
83
`define PCX_NC          117  //PCX non-cacheable bit
84
`define PCX_R           117  //PCX read/!write bit
85
`define PCX_CP_HI       116  //PCX cpu_id field
86
`define PCX_CP_LO       114
87
`define PCX_TH_HI       113  //PCX Thread field
88
`define PCX_TH_LO       112
89
`define PCX_BF_HI       111  //PCX buffer id field
90
`define PCX_INVALL      111
91
`define PCX_BF_LO       109
92
`define PCX_WY_HI       108  //PCX replaced L1 way field
93
`define PCX_WY_LO       107
94
`define PCX_P_HI        108  //PCX packet ID, 1st STQ - 10, 2nd - 01
95
`define PCX_P_LO        107
96
`define PCX_SZ_HI       106  //PCX load/store size field
97
`define PCX_SZ_LO       104
98
`define PCX_ERR_HI      106  //PCX error field
99
`define PCX_ERR_LO      104
100
`define PCX_AD_HI       103  //PCX address field
101
`define PCX_AD_LO        64
102
`define PCX_DA_HI        63  //PCX Store data
103
`define PCX_DA_LO         0
104
 
105
`define PCX_SZ_1B    3'b000  // encoding for 1B access
106
`define PCX_SZ_2B    3'b001  // encoding for 2B access
107
`define PCX_SZ_4B    3'b010  // encoding for 4B access
108
`define PCX_SZ_8B    3'b011  // encoding for 8B access
109
`define PCX_SZ_16B   3'b111  // encoding for 16B access
110
 
111
`define CPX_VLD         144  //CPX payload packet valid
112
 
113
`define CPX_RQ_HI       143  //CPX Request type
114
`define CPX_RQ_LO       140
115
`define CPX_ERR_HI      139  //CPX error field
116
`define CPX_ERR_LO      137
117
`define CPX_NC          136  //CPX non-cacheable
118
`define CPX_R           136  //CPX read/!write bit
119
`define CPX_TH_HI       135  //CPX thread ID field 
120
`define CPX_TH_LO       134
121
 
122
//bits 133:128 are shared by different fields
123
//for different packet types.
124
 
125
`define CPX_IN_HI       133  //CPX Interrupt source 
126
`define CPX_IN_LO       128
127
 
128
`define CPX_WYVLD       133  //CPX replaced way valid
129
`define CPX_WY_HI       132  //CPX replaced I$/D$ way
130
`define CPX_WY_LO       131
131
`define CPX_BF_HI       130  //CPX buffer ID field - 3 bits
132
`define CPX_BF_LO       128
133
 
134
`define CPX_SI_HI       132  //L1 set ID - PA[10:6]- 5 bits
135
`define CPX_SI_LO       128  //used for invalidates
136
 
137
`define CPX_P_HI        131  //CPX packet ID, 1st STQ - 10, 2nd - 01 
138
`define CPX_P_LO        130
139
 
140
`define CPX_ASI         130  //CPX forward request to ASI
141
`define CPX_IF4B        130
142
`define CPX_IINV        124
143
`define CPX_DINV        123
144
`define CPX_INVPA5      122
145
`define CPX_INVPA4      121
146
`define CPX_CPUID_HI    120
147
`define CPX_CPUID_LO    118
148
`define CPX_INV_PA_HI   116
149
`define CPX_INV_PA_LO   112
150
`define CPX_INV_IDX_HI   117
151
`define CPX_INV_IDX_LO   112
152
 
153
`define CPX_DA_HI       127  //CPX data payload
154
`define CPX_DA_LO         0
155
 
156
`define LOAD_RQ         5'b00000
157
`define IMISS_RQ        5'b10000
158
`define STORE_RQ        5'b00001
159
`define CAS1_RQ         5'b00010
160
`define CAS2_RQ         5'b00011
161
`define SWAP_RQ         5'b00110
162
`define STRLOAD_RQ      5'b00100
163
`define STRST_RQ        5'b00101
164
`define STQ_RQ          5'b00111
165
`define INT_RQ          5'b01001
166
`define FWD_RQ          5'b01101
167
`define FWD_RPY         5'b01110
168
`define RSVD_RQ         5'b11111
169
 
170
`define LOAD_RET        4'b0000
171
`define INV_RET         4'b0011
172
`define ST_ACK          4'b0100
173
`define AT_ACK          4'b0011
174
`define INT_RET         4'b0111
175
`define TEST_RET        4'b0101
176
`define FP_RET          4'b1000
177
`define IFILL_RET       4'b0001
178
`define EVICT_REQ       4'b0011
179
`define ERR_RET         4'b1100
180
`define STRLOAD_RET     4'b0010
181
`define STRST_ACK       4'b0110
182
`define FWD_RQ_RET      4'b1010
183
`define FWD_RPY_RET     4'b1011
184
`define RSVD_RET        4'b1111
185
 
186
//End cache crossbar defines
187
 
188
 
189
// Number of COS supported by EECU 
190
`define EECU_COS_NUM      2
191
 
192
 
193
// 
194
// BSC bus sizes
195
// =============
196
//
197
 
198
// General
199
`define BSC_ADDRESS      40
200
`define MAX_XFER_LEN     7'b0
201
`define XFER_LEN_WIDTH   6
202
 
203
// CTags
204
`define BSC_CTAG_SZ      12
205
`define EICU_CTAG_PRE    5'b11101
206
`define EICU_CTAG_REM    7
207
`define EIPU_CTAG_PRE    3'b011
208
`define EIPU_CTAG_REM    9
209
`define EECU_CTAG_PRE    8'b11010000
210
`define EECU_CTAG_REM    4
211
`define EEPU_CTAG_PRE    6'b010000
212
`define EEPU_CTAG_REM    6
213
`define L2C_CTAG_PRE     2'b00
214
`define L2C_CTAG_REM     10
215
`define JBI_CTAG_PRE     2'b10
216
`define JBI_CTAG_REM     10
217
// reinstated temporarily
218
`define PCI_CTAG_PRE     7'b1101100
219
`define PCI_CTAG_REM     5
220
 
221
 
222
// CoS
223
`define EICU_COS         1'b0
224
`define EIPU_COS         1'b1
225
`define EECU_COS         1'b0
226
`define EEPU_COS         1'b1
227
`define PCI_COS          1'b0
228
 
229
// L2$ Bank
230
`define BSC_L2_BNK_HI    8
231
`define BSC_L2_BNK_LO    6
232
 
233
// L2$ Req
234
`define BSC_L2_REQ_SZ   62
235
`define BSC_L2_REQ      `BSC_L2_REQ_SZ  // used by rams in L2 code
236
`define BSC_L2_BUS      64
237
`define BSC_L2_CTAG_HI  61
238
`define BSC_L2_CTAG_LO  50
239
`define BSC_L2_ADD_HI   49
240
`define BSC_L2_ADD_LO   10
241
`define BSC_L2_LEN_HI    9
242
`define BSC_L2_LEN_LO    3
243
`define BSC_L2_ALLOC     2
244
`define BSC_L2_COS       1
245
`define BSC_L2_READ      0
246
 
247
// L2$ Ack
248
`define L2_BSC_ACK_SZ   16
249
`define L2_BSC_BUS      64
250
`define L2_BSC_CBA_HI   14    // CBA - Critical Byte Address
251
`define L2_BSC_CBA_LO   13
252
`define L2_BSC_READ     12
253
`define L2_BSC_CTAG_HI  11
254
`define L2_BSC_CTAG_LO   0
255
 
256
// Enet Egress Command Unit
257
`define EECU_REQ_BUS    44
258
`define EECU_REQ_SZ     44
259
`define EECU_R_QID_HI   43
260
`define EECU_R_QID_LO   40
261
`define EECU_R_ADD_HI   39
262
`define EECU_R_ADD_LO    0
263
 
264
`define EECU_ACK_BUS    64
265
`define EECU_ACK_SZ      5
266
`define EECU_A_NACK      4
267
`define EECU_A_QID_HI    3
268
`define EECU_A_QID_LO    0
269
 
270
 
271
// Enet Egress Packet Unit
272
`define EEPU_REQ_BUS    55
273
`define EEPU_REQ_SZ     55
274
`define EEPU_R_TLEN_HI  54
275
`define EEPU_R_TLEN_LO  48
276
`define EEPU_R_SOF      47
277
`define EEPU_R_EOF      46
278
`define EEPU_R_PORT_HI  45
279
`define EEPU_R_PORT_LO  44
280
`define EEPU_R_QID_HI   43
281
`define EEPU_R_QID_LO   40
282
`define EEPU_R_ADD_HI   39
283
`define EEPU_R_ADD_LO    0
284
 
285
// This is cleaved in between Egress Datapath Ack's
286
`define EEPU_ACK_BUS     6
287
`define EEPU_ACK_SZ      6
288
`define EEPU_A_EOF       5
289
`define EEPU_A_NACK      4
290
`define EEPU_A_QID_HI    3
291
`define EEPU_A_QID_LO    0
292
 
293
 
294
// Enet Egress Datapath
295
`define EEDP_ACK_BUS   128
296
`define EEDP_ACK_SZ     28
297
`define EEDP_A_NACK     27
298
`define EEDP_A_QID_HI   26
299
`define EEDP_A_QID_LO   21
300
`define EEDP_A_SOF      20
301
`define EEDP_A_EOF      19
302
`define EEDP_A_LEN_HI   18
303
`define EEDP_A_LEN_LO   12
304
`define EEDP_A_TAG_HI   11
305
`define EEDP_A_TAG_LO    0
306
`define EEDP_A_PORT_HI   5
307
`define EEDP_A_PORT_LO   4
308
`define EEDP_A_PORT_WIDTH 2
309
 
310
 
311
// In-Order / Ordered Queue: EEPU
312
// Tag is: TLEN, SOF, EOF, QID = 15
313
`define EEPU_TAG_ARY     (7+1+1+6)
314
`define EEPU_ENTRIES     16
315
`define EEPU_E_IDX        4
316
`define EEPU_PORTS        4
317
`define EEPU_P_IDX        2
318
 
319
// Nack + Tag Info + CTag
320
`define IOQ_TAG_ARY      (1+`EEPU_TAG_ARY+12)
321
`define EEPU_TAG_LOC     (`EEPU_P_IDX+`EEPU_E_IDX)
322
 
323
 
324
// ENET Ingress Queue Management Req
325
`define EICU_REQ_BUS     64
326
`define EICU_REQ_SZ      62
327
`define EICU_R_CTAG_HI   61
328
`define EICU_R_CTAG_LO   50
329
`define EICU_R_ADD_HI    49
330
`define EICU_R_ADD_LO    10
331
`define EICU_R_LEN_HI     9
332
`define EICU_R_LEN_LO     3
333
`define EICU_R_COS        1
334
`define EICU_R_READ       0
335
 
336
 
337
// ENET Ingress Queue Management Ack
338
`define EICU_ACK_BUS     64
339
`define EICU_ACK_SZ      14
340
`define EICU_A_NACK      13
341
`define EICU_A_READ      12
342
`define EICU_A_CTAG_HI   11
343
`define EICU_A_CTAG_LO    0
344
 
345
 
346
// Enet Ingress Packet Unit
347
`define EIPU_REQ_BUS    128
348
`define EIPU_REQ_SZ      59
349
`define EIPU_R_CTAG_HI   58
350
`define EIPU_R_CTAG_LO   50
351
`define EIPU_R_ADD_HI    49
352
`define EIPU_R_ADD_LO    10
353
`define EIPU_R_LEN_HI     9
354
`define EIPU_R_LEN_LO     3
355
`define EIPU_R_COS        1
356
`define EIPU_R_READ       0
357
 
358
 
359
// ENET Ingress Packet Unit Ack
360
`define EIPU_ACK_BUS      10
361
`define EIPU_ACK_SZ       10
362
`define EIPU_A_NACK       9
363
`define EIPU_A_CTAG_HI    8
364
`define EIPU_A_CTAG_LO    0
365
 
366
 
367
// In-Order / Ordered Queue: PCI
368
// Tag is: CTAG
369
`define PCI_TAG_ARY     12
370
`define PCI_ENTRIES     16
371
`define PCI_E_IDX        4
372
`define PCI_PORTS        2
373
 
374
// PCI-X Request
375
`define PCI_REQ_BUS      64
376
`define PCI_REQ_SZ       62
377
`define PCI_R_CTAG_HI    61
378
`define PCI_R_CTAG_LO    50
379
`define PCI_R_ADD_HI     49
380
`define PCI_R_ADD_LO     10
381
`define PCI_R_LEN_HI      9
382
`define PCI_R_LEN_LO      3
383
`define PCI_R_COS         1
384
`define PCI_R_READ        0
385
 
386
// PCI_X Acknowledge
387
`define PCI_ACK_BUS      64
388
`define PCI_ACK_SZ       14
389
`define PCI_A_NACK       13
390
`define PCI_A_READ       12
391
`define PCI_A_CTAG_HI    11
392
`define PCI_A_CTAG_LO     0
393
 
394
 
395
`define BSC_MAX_REQ_SZ   62
396
 
397
 
398
//
399
// BSC array sizes
400
//================
401
//
402
`define BSC_REQ_ARY_INDEX        6
403
`define BSC_REQ_ARY_DEPTH       64
404
`define BSC_REQ_ARY_WIDTH       62
405
`define BSC_REQ_NXT_WIDTH       12
406
`define BSC_ACK_ARY_INDEX        6
407
`define BSC_ACK_ARY_DEPTH       64
408
`define BSC_ACK_ARY_WIDTH       14
409
`define BSC_ACK_NXT_WIDTH       12
410
`define BSC_PAY_ARY_INDEX        6
411
`define BSC_PAY_ARY_DEPTH       64
412
`define BSC_PAY_ARY_WIDTH      256
413
 
414
// ECC syndrome bits per memory element
415
`define BSC_PAY_ECC             10
416
`define BSC_PAY_MEM_WIDTH       (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH)
417
 
418
 
419
//
420
// BSC Port Definitions
421
// ====================
422
//
423
// Bits 7 to 4 of curr_port_id
424
`define BSC_PORT_NULL       4'h0
425
`define BSC_PORT_SC         4'h1
426
`define BSC_PORT_EICU       4'h2
427
`define BSC_PORT_EIPU       4'h3
428
`define BSC_PORT_EECU       4'h4
429
`define BSC_PORT_EEPU       4'h8
430
`define BSC_PORT_PCI        4'h9
431
 
432
// Number of ports of each type
433
`define BSC_PORT_SC_CNT     8
434
 
435
// Bits needed to represent above
436
`define BSC_PORT_SC_IDX     3
437
 
438
// How wide the linked list pointers are
439
// 60b for no payload (2CoS)
440
// 80b for payload (2CoS)
441
 
442
//`define BSC_OBJ_PTR   80
443
//`define BSC_HD1_HI    69
444
//`define BSC_HD1_LO    60
445
//`define BSC_TL1_HI    59
446
//`define BSC_TL1_LO    50
447
//`define BSC_CT1_HI    49
448
//`define BSC_CT1_LO    40
449
//`define BSC_HD0_HI    29
450
//`define BSC_HD0_LO    20
451
//`define BSC_TL0_HI    19
452
//`define BSC_TL0_LO    10
453
//`define BSC_CT0_HI     9
454
//`define BSC_CT0_LO     0
455
 
456
`define BSC_OBJP_PTR  48
457
`define BSC_PYP1_HI   47
458
`define BSC_PYP1_LO   42
459
`define BSC_HDP1_HI   41
460
`define BSC_HDP1_LO   36
461
`define BSC_TLP1_HI   35
462
`define BSC_TLP1_LO   30
463
`define BSC_CTP1_HI   29
464
`define BSC_CTP1_LO   24
465
`define BSC_PYP0_HI   23
466
`define BSC_PYP0_LO   18
467
`define BSC_HDP0_HI   17
468
`define BSC_HDP0_LO   12
469
`define BSC_TLP0_HI   11
470
`define BSC_TLP0_LO    6
471
`define BSC_CTP0_HI    5
472
`define BSC_CTP0_LO    0
473
 
474
`define BSC_PTR_WIDTH     192
475
`define BSC_PTR_REQ_HI    191
476
`define BSC_PTR_REQ_LO    144
477
`define BSC_PTR_REQP_HI   143
478
`define BSC_PTR_REQP_LO    96
479
`define BSC_PTR_ACK_HI     95
480
`define BSC_PTR_ACK_LO     48
481
`define BSC_PTR_ACKP_HI    47
482
`define BSC_PTR_ACKP_LO     0
483
 
484
`define BSC_PORT_SC_PTR    96       // R, R+P
485
`define BSC_PORT_EECU_PTR  48       // A+P
486
`define BSC_PORT_EICU_PTR  96       // A, A+P
487
`define BSC_PORT_EIPU_PTR  48       // A
488
 
489
// I2C STATES in DRAMctl
490
`define I2C_CMD_NOP   4'b0000
491
`define I2C_CMD_START 4'b0001
492
`define I2C_CMD_STOP  4'b0010
493
`define I2C_CMD_WRITE 4'b0100
494
`define I2C_CMD_READ  4'b1000
495
 
496
 
497
//
498
// IOB defines
499
// ===========
500
//
501
`define IOB_ADDR_WIDTH       40
502
`define IOB_LOCAL_ADDR_WIDTH 32
503
 
504
`define IOB_CPU_INDEX         3
505
`define IOB_CPU_WIDTH         8
506
`define IOB_THR_INDEX         2
507
`define IOB_THR_WIDTH         4
508
`define IOB_CPUTHR_INDEX      5
509
`define IOB_CPUTHR_WIDTH     32
510
 
511
`define IOB_MONDO_DATA_INDEX  5
512
`define IOB_MONDO_DATA_DEPTH 32
513
`define IOB_MONDO_DATA_WIDTH 64
514
`define IOB_MONDO_SRC_WIDTH   5
515
`define IOB_MONDO_BUSY        5
516
 
517
`define IOB_INT_TAB_INDEX     2
518
`define IOB_INT_TAB_DEPTH     4
519
 
520
//`define IOB_INT_STAT_WIDTH   32
521
//`define IOB_INT_STAT_HI      31
522
//`define IOB_INT_STAT_LO       0
523
 
524
`define IOB_INT_VEC_WIDTH     6
525
`define IOB_INT_VEC_HI        5
526
`define IOB_INT_VEC_LO        0
527
 
528
`define IOB_INT_CPU_WIDTH     5
529
`define IOB_INT_CPU_HI       12
530
`define IOB_INT_CPU_LO        8
531
 
532
`define IOB_INT_MASK          2
533
`define IOB_INT_CLEAR         1
534
`define IOB_INT_PEND          0
535
 
536
`define IOB_DISP_TYPE_HI     17
537
`define IOB_DISP_TYPE_LO     16
538
`define IOB_DISP_THR_HI      12
539
`define IOB_DISP_THR_LO       8
540
`define IOB_DISP_VEC_HI       5
541
`define IOB_DISP_VEC_LO       0
542
 
543
`define IOB_JBI_RESET         1
544
`define IOB_ENET_RESET        0
545
 
546
`define IOB_RESET_STAT_WIDTH  3
547
`define IOB_RESET_STAT_HI     3
548
`define IOB_RESET_STAT_LO     1
549
 
550
`define IOB_SERNUM_WIDTH     64
551
 
552
`define IOB_FUSE_WIDTH       22
553
 
554
`define IOB_TMSTAT_THERM     63
555
 
556
`define IOB_POR_TT            6'b01  // power-on-reset trap type
557
 
558
`define IOB_CPU_BUF_INDEX     4
559
 
560
`define IOB_INT_BUF_INDEX     4
561
`define IOB_INT_BUF_WIDTH   153  // interrupt table read result buffer width
562
 
563
`define IOB_IO_BUF_INDEX      4
564
`define IOB_IO_BUF_WIDTH    153  // io-2-cpu return buffer width
565
 
566
`define IOB_L2_VIS_BUF_INDEX  5
567
`define IOB_L2_VIS_BUF_WIDTH 48  // l2 visibility buffer width
568
 
569
`define IOB_INT_AVEC_WIDTH    9  // availibility vector width
570
`define IOB_ACK_AVEC_WIDTH    9  // availibility vector width
571
 
572
// fixme - double check address mapping
573
// CREG in `IOB_INT_CSR space
574
`define IOB_DEV_ADDR_MASK    32'hffffffe7
575
`define IOB_CREG_INTSTAT     32'h00000000
576
`define IOB_CREG_MDATA0      32'h00000400
577
`define IOB_CREG_MDATA1      32'h00000500
578
`define IOB_CREG_MBUSY       32'h00000900
579
`define IOB_THR_ADDR_MASK    32'hffffff07
580
`define IOB_CREG_MDATA0_ALIAS 32'h00000600
581
`define IOB_CREG_MDATA1_ALIAS 32'h00000700
582
`define IOB_CREG_MBUSY_ALIAS  32'h00000b00
583
 
584
// CREG in `IOB_MAN_CSR space
585
`define IOB_CREG_INTMAN      32'h00000000
586
`define IOB_CREG_INTCTL      32'h00000400
587
`define IOB_CREG_INTVECDISP  32'h00000800
588
`define IOB_CREG_RESETSTAT   32'h00000810
589
`define IOB_CREG_SERNUM      32'h00000820
590
`define IOB_CREG_TMSTATCTRL  32'h00000828
591
`define IOB_CREG_COREAVAIL   32'h00000830
592
`define IOB_CREG_SSYSRESET   32'h00000838
593
`define IOB_CREG_FUSESTAT    32'h00000840
594
`define IOB_CREG_MARGIN      32'h00000850
595
`define IOB_CREG_JINTV       32'h00000a00
596
 
597
`define IOB_CREG_DBG_L2VIS_CTRL    32'h00001800
598
`define IOB_CREG_DBG_L2VIS_MASKA   32'h00001820
599
`define IOB_CREG_DBG_L2VIS_MASKB   32'h00001828
600
`define IOB_CREG_DBG_L2VIS_CMPA    32'h00001830
601
`define IOB_CREG_DBG_L2VIS_CMPB    32'h00001838
602
`define IOB_CREG_DBG_L2VIS_TRIG    32'h00001840
603
`define IOB_CREG_DBG_IOBVIS_CTRL   32'h00001000
604
`define IOB_CREG_DBG_ENET_CTRL     32'h00002000
605
`define IOB_CREG_DBG_ENET_IDLEVAL  32'h00002008
606
`define IOB_CREG_DBG_JBUS_CTRL     32'h00002100
607
`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140
608
`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160
609
`define IOB_CREG_DBG_JBUS_LO_CMP0  32'h00002148
610
`define IOB_CREG_DBG_JBUS_LO_CMP1  32'h00002168
611
`define IOB_CREG_DBG_JBUS_LO_CNT0  32'h00002150
612
`define IOB_CREG_DBG_JBUS_LO_CNT1  32'h00002170
613
`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180
614
`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0
615
`define IOB_CREG_DBG_JBUS_HI_CMP0  32'h00002188
616
`define IOB_CREG_DBG_JBUS_HI_CMP1  32'h000021a8
617
`define IOB_CREG_DBG_JBUS_HI_CNT0  32'h00002190
618
`define IOB_CREG_DBG_JBUS_HI_CNT1  32'h000021b0
619
 
620
`define IOB_CREG_TESTSTUB    32'h80000000
621
 
622
// Address map for TAP access of SPARC ASI
623
`define IOB_ASI_PC            4'b0000
624
`define IOB_ASI_BIST          4'b0001
625
`define IOB_ASI_MARGIN        4'b0010
626
`define IOB_ASI_DEFEATURE     4'b0011
627
`define IOB_ASI_L1DD          4'b0100
628
`define IOB_ASI_L1ID          4'b0101
629
`define IOB_ASI_L1DT          4'b0110
630
 
631
`define IOB_INT               2'b00
632
`define IOB_RESET             2'b01
633
`define IOB_IDLE              2'b10
634
`define IOB_RESUME            2'b11
635
 
636
//
637
// CIOP UCB Bus Width
638
// ==================
639
//
640
//`define IOB_EECU_WIDTH       16  // ethernet egress command
641
//`define EECU_IOB_WIDTH       16
642
 
643
//`define IOB_NRAM_WIDTH       16  // NRAM (RLDRAM previously)
644
//`define NRAM_IOB_WIDTH        4
645
 
646
`define IOB_JBI_WIDTH        64  // JBI
647
`define JBI_IOB_WIDTH        16
648
 
649
//`define IOB_ENET_ING_WIDTH   32  // ethernet ingress
650
//`define ENET_ING_IOB_WIDTH    8
651
 
652
//`define IOB_ENET_EGR_WIDTH    4  // ethernet egress
653
//`define ENET_EGR_IOB_WIDTH    4
654
 
655
//`define IOB_ENET_MAC_WIDTH    4  // ethernet MAC
656
//`define ENET_MAC_IOB_WIDTH    4
657
 
658
`define IOB_DRAM_WIDTH        4  // DRAM controller
659
`define DRAM_IOB_WIDTH        4
660
 
661
//`define IOB_BSC_WIDTH         4  // BSC
662
//`define BSC_IOB_WIDTH         4
663
 
664
`define IOB_SPI_WIDTH         4  // SPI (Boot ROM)
665
`define SPI_IOB_WIDTH         4
666
 
667
`define IOB_CLK_WIDTH         4  // clk unit
668
`define CLK_IOB_WIDTH         4
669
 
670
//`define IOB_CLSP_WIDTH        4  // clk spine unit
671
//`define CLSP_IOB_WIDTH        4
672
 
673
`define IOB_TAP_WIDTH         8  // TAP
674
`define TAP_IOB_WIDTH         8
675
 
676
 
677
//
678
// CIOP UCB Buf ID Type
679
// ====================
680
//
681
`define UCB_BID_CMP          2'b00
682
`define UCB_BID_TAP          2'b01
683
 
684
//
685
// Interrupt Device ID
686
// ===================
687
//
688
// Caution: DUMMY_DEV_ID has to be 9 bit wide
689
//          for fields to line up properly in the IOB.
690
`define DUMMY_DEV_ID         9'h00   // 0
691
`define UNCOR_ECC_DEV_ID     7'd1    // 1
692
 
693
//
694
// Soft Error related definitions
695
// ==============================
696
//
697
`define COR_ECC_CNT_WIDTH   16
698
 
699
 
700
//
701
// CMP clock
702
// =========
703
//
704
 
705
`define CMP_CLK_PERIOD   1333
706
 
707
 
708
//
709
// NRAM/IO Interface
710
// =================
711
//
712
 
713
`define DRAM_CLK_PERIOD  6000
714
 
715
`define NRAM_IO_DQ_WIDTH   32
716
`define IO_NRAM_DQ_WIDTH   32
717
 
718
`define NRAM_IO_ADDR_WIDTH 15
719
`define NRAM_IO_BA_WIDTH    2
720
 
721
 
722
//
723
// NRAM/ENET Interface
724
// ===================
725
//
726
 
727
`define NRAM_ENET_DATA_WIDTH 64
728
`define ENET_NRAM_ADDR_WIDTH 20
729
 
730
`define NRAM_DBG_DATA_WIDTH  40
731
 
732
 
733
//
734
// IO/FCRAM Interface
735
// ==================
736
//
737
 
738
`define FCRAM_DATA1_HI       63
739
`define FCRAM_DATA1_LO       32
740
`define FCRAM_DATA0_HI       31
741
`define FCRAM_DATA0_LO        0
742
 
743
//
744
// PCI Interface
745
// ==================
746
// Load/store size encodings
747
// -------------------------
748
// Size encoding
749
// 000 - byte
750
// 001 - half-word
751
// 010 - word
752
// 011 - double-word
753
// 100 - quad
754
`define LDST_SZ_BYTE        3'b000
755
`define LDST_SZ_HALF_WORD   3'b001
756
`define LDST_SZ_WORD        3'b010
757
`define LDST_SZ_DOUBLE_WORD 3'b011
758
`define LDST_SZ_QUAD        3'b100
759
 
760
//
761
// JBI<->SCTAG Interface
762
// =======================
763
// Outbound Header Format
764
`define JBI_BTU_OUT_ADDR_LO      0
765
`define JBI_BTU_OUT_ADDR_HI     42
766
`define JBI_BTU_OUT_RSV0_LO     43
767
`define JBI_BTU_OUT_RSV0_HI     43
768
`define JBI_BTU_OUT_TYPE_LO     44
769
`define JBI_BTU_OUT_TYPE_HI     48
770
`define JBI_BTU_OUT_RSV1_LO     49
771
`define JBI_BTU_OUT_RSV1_HI     51
772
`define JBI_BTU_OUT_REPLACE_LO  52
773
`define JBI_BTU_OUT_REPLACE_HI  56
774
`define JBI_BTU_OUT_RSV2_LO     57
775
`define JBI_BTU_OUT_RSV2_HI     59
776
`define JBI_BTU_OUT_BTU_ID_LO   60
777
`define JBI_BTU_OUT_BTU_ID_HI   71
778
`define JBI_BTU_OUT_DATA_RTN    72
779
`define JBI_BTU_OUT_RSV3_LO     73
780
`define JBI_BTU_OUT_RSV3_HI     75
781
`define JBI_BTU_OUT_CE          76
782
`define JBI_BTU_OUT_RSV4_LO     77
783
`define JBI_BTU_OUT_RSV4_HI     79
784
`define JBI_BTU_OUT_UE          80
785
`define JBI_BTU_OUT_RSV5_LO     81
786
`define JBI_BTU_OUT_RSV5_HI     83
787
`define JBI_BTU_OUT_DRAM        84
788
`define JBI_BTU_OUT_RSV6_LO     85
789
`define JBI_BTU_OUT_RSV6_HI    127
790
 
791
// Inbound Header Format
792
`define JBI_SCTAG_IN_ADDR_LO   0
793
`define JBI_SCTAG_IN_ADDR_HI  39
794
`define JBI_SCTAG_IN_SZ_LO    40
795
`define JBI_SCTAG_IN_SZ_HI    42
796
`define JBI_SCTAG_IN_RSV0     43
797
`define JBI_SCTAG_IN_TAG_LO   44
798
`define JBI_SCTAG_IN_TAG_HI   55
799
`define JBI_SCTAG_IN_REQ_LO   56
800
`define JBI_SCTAG_IN_REQ_HI   58
801
`define JBI_SCTAG_IN_POISON   59
802
`define JBI_SCTAG_IN_RSV1_LO  60
803
`define JBI_SCTAG_IN_RSV1_HI  63
804
 
805
`define JBI_SCTAG_REQ_WRI   3'b100
806
`define JBI_SCTAG_REQ_WR8   3'b010
807
`define JBI_SCTAG_REQ_RDD   3'b001
808
`define JBI_SCTAG_REQ_WRI_BIT 2
809
`define JBI_SCTAG_REQ_WR8_BIT 1
810
`define JBI_SCTAG_REQ_RDD_BIT 0
811
 
812
//
813
// JBI->IOB Mondo Header Format
814
// ============================
815
//
816
`define JBI_IOB_MONDO_RSV1_HI       15 // reserved 1
817
`define JBI_IOB_MONDO_RSV1_LO       13
818
`define JBI_IOB_MONDO_TRG_HI        12 // interrupt target
819
`define JBI_IOB_MONDO_TRG_LO         8
820
`define JBI_IOB_MONDO_RSV0_HI        7 // reserved 0
821
`define JBI_IOB_MONDO_RSV0_LO        5
822
`define JBI_IOB_MONDO_SRC_HI         4 // interrupt source
823
`define JBI_IOB_MONDO_SRC_LO         0
824
 
825
`define JBI_IOB_MONDO_RSV1_WIDTH     3
826
`define JBI_IOB_MONDO_TRG_WIDTH      5
827
`define JBI_IOB_MONDO_RSV0_WIDTH     3
828
`define JBI_IOB_MONDO_SRC_WIDTH      5
829
 
830
// JBI->IOB Mondo Bus Width/Cycle
831
// ==============================
832
// Cycle  1 Header[15:8]
833
// Cycle  2 Header[ 7:0]
834
// Cycle  3 J_AD[127:120]
835
// Cycle  4 J_AD[119:112]
836
// .....
837
// Cycle 18 J_AD[  7:  0]
838
`define JBI_IOB_MONDO_BUS_WIDTH      8
839
`define JBI_IOB_MONDO_BUS_CYCLE     18 // 2 header + 16 data

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