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// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T1 Processor File: bw_r_rf32x80.v
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================
`ifdef SIMPLY_RISC_TWEAKS
`define SIMPLY_RISC_SCANIN .si(0)
`else
`define SIMPLY_RISC_SCANIN .si()
`endif
////////////////////////////////////////////////////////////////////////
/*
//      Description:    Trap Stack Array
//                      - Dual-Ported.
//                      - Port1 - Write Port; Used by wrpr, trap insertion.
//                      Write occurs in W Stage. (M1:M2:W).
//                      - Port2 - Read Port; Used by rdpr, done/retry.
//                      Read occurs in E Stage.
//                      - Arranged as 6(trap-levels/thread) x 4 threads = 24 entries.
//                      Trap-level and thread id used to index array.
*/
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
 
//FPGA_SYN enables all FPGA related modifications
`ifdef FPGA_SYN
`define FPGA_SYN_32x80
`endif
 
`ifdef FPGA_SYN_32x80
module bw_r_rf32x80 (/*AUTOARG*/
   // Outputs
   dout, so,
   // Inputs
   rd_en, rd_adr, wr_en, nib_wr_en, wr_adr, din,
   si, se, sehold, rclk, rst_tri_en, reset_l);
 
parameter NUM_TPL = 6 ;                 // 6 supported trap levels.
parameter NUM_ENTRIES = 32 ;    // 8 entries per thread
 
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
input [4:0]   rd_adr;      // read adr. 
input         rd_en;      // read pointer
input         wr_en;      // write pointer vld
input [19:0]  nib_wr_en;  // enable write of a byte in tsa. 
input [4:0]   wr_adr;      // write adr.
input [79:0] din;              // wr data for tsa.
input             rclk;       // clock
input         reset_l;    // active low reset
input         rst_tri_en; // reset and scan  
input         sehold;     // scan hold 
input             si;             // scan in 
input             se;             // scan enable 
 
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
output  [79:0] dout ; // rd data for tsa.
output                  so ;   // scan out write 
 
wire [79:0]    dout;
wire clk;
wire wr_vld, wr_vld_d1;
 
reg     [79:0]           tsa_rdata;
reg [79:0]     local_dout;
// reg                  so; 
 
integer i,j;
 
wire    [79:0]   write_mask;
wire    [79:0]   write_mask_d1;
//
// added for atpg support
wire [4:0]   sehold_rd_adr;         // output of sehold mux - read adr. 
wire         sehold_rd_en;         // output of sehold mux - read pointer
wire         sehold_wr_en;         // output of sehold mux - write pointer vld
wire [19:0]  sehold_nib_wr_en; // output of sehold mux - enable write of a byte in tsa. 
wire  [4:0]   sehold_wr_adr;        // output of sehold mux - write adr.
wire [79:0]  sehold_din;    // wr data for tsa.
 
reg [4:0]   rd_adr_d1;      // flopped read adr. 
wire         rd_en_d1;     // flopped read pointer
wire         wr_en_d1;     // flopped write pointer vld
wire [19:0]  nib_wr_en_d1; // flopped enable write of a byte in tsa. 
reg [4:0]   wr_adr_d1;      // flopped write adr.
wire [79:0]  din_d1;        // flopped wr data for tsa.
// wire [5:0]   local_scan1;
// wire [25:0]  local_scan2;
// wire [78:0]  local_scan3;
 
//
// creating local clock
assign clk=rclk;
// 
//=========================================================================================
//      support for atpg pattern generation
//=========================================================================================
//
// read controls
dp_mux2es #(1) mux_sehold_rd_ctrl (
    .in0  ({rd_en}),
    .in1  ({rd_en_d1}),
    .sel  (sehold),
    .dout ({sehold_rd_en})
);
//
// modified to match circuit implementataion
dff_s #(1) dff_rd_ctrl_d1(
    .din ({sehold_rd_en}),
    .q   ({rd_en_d1}),
    .clk (clk),
    .se  (se),
    `SIMPLY_RISC_SCANIN,
    .so  ()
);
//
// write controls
// modified to match circuit implementataion
dp_mux2es #(21) mux_sehold_wr_ctrl (
        .in0    ({nib_wr_en[19:0], wr_en}),
        .in1    ({nib_wr_en_d1[19:0], wr_en_d1}),
        .sel    (sehold),
        .dout   ({sehold_nib_wr_en[19:0], sehold_wr_en})
);
 
// modified to match circuit implementataion
dff_s #(21) dff_wr_ctrl_d1(
    .din ({sehold_nib_wr_en[19:0], sehold_wr_en}),
    .q   ({nib_wr_en_d1[19:0], wr_en_d1}),
    .clk (clk),
    .se  (se),
    `SIMPLY_RISC_SCANIN,
    .so  ()
);
//
// write data
dp_mux2es #(80) mux_sehold_din (
        .in0    (din[79:0]),
        .in1    (din_d1[79:0]),
        .sel    (sehold),
        .dout   (sehold_din[79:0])
);
 
dff_s #(80) dff_din_d1(
    .din (sehold_din[79:0]),
    .q   (din_d1[79:0]),
    .clk (clk),
    .se  (se),
    `SIMPLY_RISC_SCANIN,
    .so  ()
);
 
//
// diable write to register file during reset or scan
// assign wr_vld = sehold_wr_en & ~rst_tri_en & reset_l; 
assign wr_vld = sehold_wr_en & ~rst_tri_en;
assign wr_vld_d1 = wr_en_d1 & ~rst_tri_en;
 
//    always @ (posedge clk)
//      begin
//         so <= 1'bx;
//      end
 
//=========================================================================================
//      generate wordlines
//=========================================================================================
 
// Word-Line Generation skipped. Implicit in read and write.
 
//=========================================================================================
//      write or read to/from memory
//=========================================================================================
// creating the write mask from the nibble enable controls
 
assign  write_mask[79:0] =
        {{4{sehold_nib_wr_en[19]}},
         {4{sehold_nib_wr_en[18]}},
     {4{sehold_nib_wr_en[17]}},
         {4{sehold_nib_wr_en[16]}},
         {4{sehold_nib_wr_en[15]}},
         {4{sehold_nib_wr_en[14]}},
         {4{sehold_nib_wr_en[13]}},
         {4{sehold_nib_wr_en[12]}},
         {4{sehold_nib_wr_en[11]}},
         {4{sehold_nib_wr_en[10]}},
         {4{sehold_nib_wr_en[9]}},
         {4{sehold_nib_wr_en[8]}},
         {4{sehold_nib_wr_en[7]}},
         {4{sehold_nib_wr_en[6]}},
         {4{sehold_nib_wr_en[5]}},
         {4{sehold_nib_wr_en[4]}},
         {4{sehold_nib_wr_en[3]}},
         {4{sehold_nib_wr_en[2]}},
         {4{sehold_nib_wr_en[1]}},
         {4{sehold_nib_wr_en[0]}}
        };
 
assign  write_mask_d1[79:0] =
        {{4{nib_wr_en_d1[19]}},
         {4{nib_wr_en_d1[18]}},
     {4{nib_wr_en_d1[17]}},
         {4{nib_wr_en_d1[16]}},
         {4{nib_wr_en_d1[15]}},
         {4{nib_wr_en_d1[14]}},
         {4{nib_wr_en_d1[13]}},
         {4{nib_wr_en_d1[12]}},
         {4{nib_wr_en_d1[11]}},
         {4{nib_wr_en_d1[10]}},
         {4{nib_wr_en_d1[9]}},
         {4{nib_wr_en_d1[8]}},
         {4{nib_wr_en_d1[7]}},
         {4{nib_wr_en_d1[6]}},
         {4{nib_wr_en_d1[5]}},
         {4{nib_wr_en_d1[4]}},
         {4{nib_wr_en_d1[3]}},
         {4{nib_wr_en_d1[2]}},
         {4{nib_wr_en_d1[1]}},
         {4{nib_wr_en_d1[0]}}
        };
 
reg     [79:0]   tsa_mem [NUM_ENTRIES-1:0] /* synthesis syn_ramstyle = block_ram  syn_ramstyle = no_rw_check */ ;
 
reg     [79:0]           temp_tlvl;
wire    [79:0]           temp_tlvl2;
 
 
 
always @(posedge clk) begin
  rd_adr_d1 <= sehold_rd_adr;
  wr_adr_d1 <= sehold_wr_adr;
end
 
assign sehold_wr_adr = sehold ? wr_adr_d1 : wr_adr;
assign sehold_rd_adr = sehold ? rd_adr_d1 : rd_adr;
 
assign temp_tlvl2 = tsa_mem[sehold_rd_adr[4:0]];
 
always @(posedge clk)
  if(~reset_l)
    local_dout[79:0] <= 80'b0;
  else
   if (sehold_rd_en)
     local_dout[79:0] <= temp_tlvl2;
 
always @ ( posedge clk) begin
        temp_tlvl[79:0] = tsa_mem[sehold_wr_adr];
        if (wr_vld & reset_l) begin
                tsa_mem[sehold_wr_adr] = (temp_tlvl[79:0] & ~write_mask[79:0]) | (sehold_din[79:0] &  write_mask[79:0]) ;
        end
end
 
 
assign dout[79:0] = local_dout;
 
 
 
endmodule
 
`else
 
module bw_r_rf32x80 (/*AUTOARG*/
   // Outputs
   dout, so,
   // Inputs
   rd_en, rd_adr, wr_en, nib_wr_en, wr_adr, din,
   si, se, sehold, rclk, rst_tri_en, reset_l);
 
parameter NUM_TPL = 6 ;                 // 6 supported trap levels.
parameter NUM_ENTRIES = 32 ;    // 8 entries per thread
 
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
input [4:0]   rd_adr;      // read adr. 
input         rd_en;      // read pointer
input         wr_en;      // write pointer vld
input [19:0]  nib_wr_en;  // enable write of a byte in tsa. 
input [4:0]   wr_adr;      // write adr.
input [79:0] din;              // wr data for tsa.
input             rclk;       // clock
input         reset_l;    // active low reset
input         rst_tri_en; // reset and scan  
input         sehold;     // scan hold 
input             si;             // scan in 
input             se;             // scan enable 
 
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
output  [79:0] dout ; // rd data for tsa.
output                  so ;   // scan out write 
 
wire [79:0]    dout;
wire clk;
wire wr_vld, wr_vld_d1;
 
reg     [79:0]           tsa_mem [NUM_ENTRIES-1:0];
reg     [79:0]           tsa_rdata;
reg [79:0]     local_dout;
reg     [79:0]           temp_tlvl;
// reg                  so; 
 
integer i,j;
 
wire    [79:0]   write_mask;
wire    [79:0]   write_mask_d1;
//
// added for atpg support
wire [4:0]   sehold_rd_adr;         // output of sehold mux - read adr. 
wire         sehold_rd_en;         // output of sehold mux - read pointer
wire         sehold_wr_en;         // output of sehold mux - write pointer vld
wire [19:0]  sehold_nib_wr_en; // output of sehold mux - enable write of a byte in tsa. 
wire [4:0]   sehold_wr_adr;         // output of sehold mux - write adr.
wire [79:0]  sehold_din;    // wr data for tsa.
 
wire [4:0]   rd_adr_d1;     // flopped read adr. 
wire         rd_en_d1;     // flopped read pointer
wire         wr_en_d1;     // flopped write pointer vld
wire [19:0]  nib_wr_en_d1; // flopped enable write of a byte in tsa. 
wire [4:0]   wr_adr_d1;     // flopped write adr.
wire [79:0]  din_d1;        // flopped wr data for tsa.
// wire [5:0]   local_scan1;
// wire [25:0]  local_scan2;
// wire [78:0]  local_scan3;
 
//
// creating local clock
assign clk=rclk;
// 
//=========================================================================================
//      support for atpg pattern generation
//=========================================================================================
//
// read controls
dp_mux2es #(6) mux_sehold_rd_ctrl (
    .in0  ({rd_adr[4:0], rd_en}),
    .in1  ({rd_adr_d1[4:0], rd_en_d1}),
    .sel  (sehold),
    .dout ({sehold_rd_adr[4:0],sehold_rd_en})
);
//
// modified to match circuit implementataion
dff_s #(6) dff_rd_ctrl_d1(
    .din ({sehold_rd_adr[4:0], sehold_rd_en}),
    .q   ({rd_adr_d1[4:0], rd_en_d1}),
    .clk (clk),
    .se  (se),
    `SIMPLY_RISC_SCANIN,
    .so  ()
);
//
// write controls
// modified to match circuit implementataion
dp_mux2es #(26) mux_sehold_wr_ctrl (
        .in0    ({nib_wr_en[19:0], wr_adr[4:0], wr_en}),
        .in1    ({nib_wr_en_d1[19:0], wr_adr_d1[4:0], wr_en_d1}),
        .sel    (sehold),
        .dout   ({sehold_nib_wr_en[19:0], sehold_wr_adr[4:0],sehold_wr_en})
);
 
// modified to match circuit implementataion
dff_s #(26) dff_wr_ctrl_d1(
    .din ({sehold_nib_wr_en[19:0], sehold_wr_adr[4:0], sehold_wr_en}),
    .q   ({nib_wr_en_d1[19:0], wr_adr_d1[4:0], wr_en_d1}),
    .clk (clk),
    .se  (se),
    `SIMPLY_RISC_SCANIN,
    .so  ()
);
//
// write data
dp_mux2es #(80) mux_sehold_din (
        .in0    (din[79:0]),
        .in1    (din_d1[79:0]),
        .sel    (sehold),
        .dout   (sehold_din[79:0])
);
 
dff_s #(80) dff_din_d1(
    .din (sehold_din[79:0]),
    .q   (din_d1[79:0]),
    .clk (clk),
    .se  (se),
    `SIMPLY_RISC_SCANIN,
    .so  ()
);
 
//
// diable write to register file during reset or scan
// assign wr_vld = sehold_wr_en & ~rst_tri_en & reset_l; 
assign wr_vld = sehold_wr_en & ~rst_tri_en;
assign wr_vld_d1 = wr_en_d1 & ~rst_tri_en;
 
//    always @ (posedge clk)
//      begin
//         so <= 1'bx;
//      end
 
//=========================================================================================
//      generate wordlines
//=========================================================================================
 
// Word-Line Generation skipped. Implicit in read and write.
 
//=========================================================================================
//      write or read to/from memory
//=========================================================================================
// creating the write mask from the nibble enable controls
 
assign  write_mask[79:0] =
        {{4{sehold_nib_wr_en[19]}},
         {4{sehold_nib_wr_en[18]}},
     {4{sehold_nib_wr_en[17]}},
         {4{sehold_nib_wr_en[16]}},
         {4{sehold_nib_wr_en[15]}},
         {4{sehold_nib_wr_en[14]}},
         {4{sehold_nib_wr_en[13]}},
         {4{sehold_nib_wr_en[12]}},
         {4{sehold_nib_wr_en[11]}},
         {4{sehold_nib_wr_en[10]}},
         {4{sehold_nib_wr_en[9]}},
         {4{sehold_nib_wr_en[8]}},
         {4{sehold_nib_wr_en[7]}},
         {4{sehold_nib_wr_en[6]}},
         {4{sehold_nib_wr_en[5]}},
         {4{sehold_nib_wr_en[4]}},
         {4{sehold_nib_wr_en[3]}},
         {4{sehold_nib_wr_en[2]}},
         {4{sehold_nib_wr_en[1]}},
         {4{sehold_nib_wr_en[0]}}
        };
 
assign  write_mask_d1[79:0] =
        {{4{nib_wr_en_d1[19]}},
         {4{nib_wr_en_d1[18]}},
     {4{nib_wr_en_d1[17]}},
         {4{nib_wr_en_d1[16]}},
         {4{nib_wr_en_d1[15]}},
         {4{nib_wr_en_d1[14]}},
         {4{nib_wr_en_d1[13]}},
         {4{nib_wr_en_d1[12]}},
         {4{nib_wr_en_d1[11]}},
         {4{nib_wr_en_d1[10]}},
         {4{nib_wr_en_d1[9]}},
         {4{nib_wr_en_d1[8]}},
         {4{nib_wr_en_d1[7]}},
         {4{nib_wr_en_d1[6]}},
         {4{nib_wr_en_d1[5]}},
         {4{nib_wr_en_d1[4]}},
         {4{nib_wr_en_d1[3]}},
         {4{nib_wr_en_d1[2]}},
         {4{nib_wr_en_d1[1]}},
         {4{nib_wr_en_d1[0]}}
        };
 
always @ ( negedge reset_l)
        begin
        local_dout[79:0] <= 80'h0;
    end
 
always @ ( posedge reset_l)
        begin
            if (rd_en_d1 & clk)
                      begin
                            if (wr_vld_d1 & (wr_adr_d1[4:0] == rd_adr_d1[4:0]) )
                                    local_dout[79:0] <= 80'hx;
                                else
                                    for (j=0;j<NUM_ENTRIES;j=j+1)
                                            begin
                                                    if (rd_adr_d1[4:0] == j)
                                                        local_dout[79:0] <= tsa_mem[j] ;
                                            end
                      end
        end
 
 
 
 
always @ ( posedge reset_l)
        begin
                if (wr_vld_d1 & clk)
                        for (i=0;i<NUM_ENTRIES;i=i+1)
                                begin
                                if (wr_adr_d1[4:0] == i)
                                        begin
                                        // read
                                        temp_tlvl[79:0] = tsa_mem[i];
                                        // modify & write
                                        tsa_mem[i] =
                                        (temp_tlvl[79:0] & ~write_mask_d1[79:0]) |
                                        (din_d1[79:0] &  write_mask_d1[79:0]) ;
                                        end
                                end
        end
 
 
always @ ( posedge clk)
        begin
                if (wr_vld & reset_l)
                        for (i=0;i<NUM_ENTRIES;i=i+1)
                                begin
                                if (sehold_wr_adr[4:0] == i)
                                        begin
                                        // read
                                        temp_tlvl[79:0] = tsa_mem[i];
                                        // modify & write
                                        tsa_mem[i] =
                                        (temp_tlvl[79:0] & ~write_mask[79:0]) |
                                        (sehold_din[79:0] &  write_mask[79:0]) ;
                                        end
                                end
        end
 
always @ ( posedge clk )
        begin
              begin
                                if (sehold_rd_en & reset_l)
                                        begin
                                                if (wr_vld & (sehold_wr_adr[4:0] == sehold_rd_adr[4:0]) )
                                                        local_dout[79:0] <= 80'hx;
                                                else
                                                        for (j=0;j<NUM_ENTRIES;j=j+1)
                                                        begin
                                                                if (sehold_rd_adr[4:0] == j)
                                                                local_dout[79:0] <= tsa_mem[j] ;
                                                        end
                                        end
            end
        end
 
assign dout[79:0] = local_dout[79:0];
 
 
endmodule
`endif
 

Line No.	Rev	Author	Line
1	95	fafa1971	`// ========== Copyright Header Begin ==========================================`
2			`//`
3			`// OpenSPARC T1 Processor File: bw_r_rf32x80.v`
4			`// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.`
5			`// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.`
6			`//`
7			`// The above named program is free software; you can redistribute it and/or`
8			`// modify it under the terms of the GNU General Public`
9			`// License version 2 as published by the Free Software Foundation.`
10			`//`
11			`// The above named program is distributed in the hope that it will be`
12			`// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
14			`// General Public License for more details.`
15			`//`
16			`// You should have received a copy of the GNU General Public`
17			`// License along with this work; if not, write to the Free Software`
18			`// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.`
19			`//`
20			`// ========== Copyright Header End ============================================`
21	113	albert.wat	`ifdef SIMPLY_RISC_TWEAKS
22			`define SIMPLY_RISC_SCANIN .si(0)
23			`else
24			`define SIMPLY_RISC_SCANIN .si()
25			`endif
26	95	fafa1971	`////////////////////////////////////////////////////////////////////////`
27			`/*`
28			`// Description: Trap Stack Array`
29			`// - Dual-Ported.`
30			`// - Port1 - Write Port; Used by wrpr, trap insertion.`
31			`// Write occurs in W Stage. (M1:M2:W).`
32			`// - Port2 - Read Port; Used by rdpr, done/retry.`
33			`// Read occurs in E Stage.`
34			`// - Arranged as 6(trap-levels/thread) x 4 threads = 24 entries.`
35			`// Trap-level and thread id used to index array.`
36			`*/`
37			`////////////////////////////////////////////////////////////////////////`
38			`// Local header file includes / local defines`
39			`////////////////////////////////////////////////////////////////////////`
40
41			`//FPGA_SYN enables all FPGA related modifications`
42	113	albert.wat	`ifdef FPGA_SYN
43			`define FPGA_SYN_32x80
44			`endif
45	95	fafa1971
46	113	albert.wat	`ifdef FPGA_SYN_32x80
47	95	fafa1971	`module bw_r_rf32x80 (/AUTOARG/`
48			`// Outputs`
49			`dout, so,`
50			`// Inputs`
51			`rd_en, rd_adr, wr_en, nib_wr_en, wr_adr, din,`
52			`si, se, sehold, rclk, rst_tri_en, reset_l);`
53
54			`parameter NUM_TPL = 6 ; // 6 supported trap levels.`
55			`parameter NUM_ENTRIES = 32 ; // 8 entries per thread`
56
57			`/AUTOINPUT/`
58			`// Beginning of automatic inputs (from unused autoinst inputs)`
59			`// End of automatics`
60			`input [4:0] rd_adr; // read adr.`
61			`input rd_en; // read pointer`
62			`input wr_en; // write pointer vld`
63			`input [19:0] nib_wr_en; // enable write of a byte in tsa.`
64			`input [4:0] wr_adr; // write adr.`
65			`input [79:0] din; // wr data for tsa.`
66			`input rclk; // clock`
67			`input reset_l; // active low reset`
68			`input rst_tri_en; // reset and scan`
69			`input sehold; // scan hold`
70			`input si; // scan in`
71			`input se; // scan enable`
72
73			`/AUTOOUTPUT/`
74			`// Beginning of automatic outputs (from unused autoinst outputs)`
75			`// End of automatics`
76			`output [79:0] dout ; // rd data for tsa.`
77			`output so ; // scan out write`
78
79			`wire [79:0] dout;`
80			`wire clk;`
81			`wire wr_vld, wr_vld_d1;`
82
83			`reg [79:0] tsa_rdata;`
84			`reg [79:0] local_dout;`
85			`// reg so;`
86
87			`integer i,j;`
88
89			`wire [79:0] write_mask;`
90			`wire [79:0] write_mask_d1;`
91			`//`
92			`// added for atpg support`
93			`wire [4:0] sehold_rd_adr; // output of sehold mux - read adr.`
94			`wire sehold_rd_en; // output of sehold mux - read pointer`
95			`wire sehold_wr_en; // output of sehold mux - write pointer vld`
96			`wire [19:0] sehold_nib_wr_en; // output of sehold mux - enable write of a byte in tsa.`
97			`wire [4:0] sehold_wr_adr; // output of sehold mux - write adr.`
98			`wire [79:0] sehold_din; // wr data for tsa.`
99
100			`reg [4:0] rd_adr_d1; // flopped read adr.`
101			`wire rd_en_d1; // flopped read pointer`
102			`wire wr_en_d1; // flopped write pointer vld`
103			`wire [19:0] nib_wr_en_d1; // flopped enable write of a byte in tsa.`
104			`reg [4:0] wr_adr_d1; // flopped write adr.`
105			`wire [79:0] din_d1; // flopped wr data for tsa.`
106			`// wire [5:0] local_scan1;`
107			`// wire [25:0] local_scan2;`
108			`// wire [78:0] local_scan3;`
109
110			`//`
111			`// creating local clock`
112			`assign clk=rclk;`
113			`//`
114			`//=========================================================================================`
115			`// support for atpg pattern generation`
116			`//=========================================================================================`
117			`//`
118			`// read controls`
119			`dp_mux2es #(1) mux_sehold_rd_ctrl (`
120			`.in0 ({rd_en}),`
121			`.in1 ({rd_en_d1}),`
122			`.sel (sehold),`
123			`.dout ({sehold_rd_en})`
124			`);`
125			`//`
126			`// modified to match circuit implementataion`
127	113	albert.wat	`dff_s #(1) dff_rd_ctrl_d1(`
128	95	fafa1971	`.din ({sehold_rd_en}),`
129			`.q ({rd_en_d1}),`
130			`.clk (clk),`
131			`.se (se),`
132	113	albert.wat	`SIMPLY_RISC_SCANIN,
133	95	fafa1971	`.so ()`
134			`);`
135			`//`
136			`// write controls`
137			`// modified to match circuit implementataion`
138			`dp_mux2es #(21) mux_sehold_wr_ctrl (`
139			`.in0 ({nib_wr_en[19:0], wr_en}),`
140			`.in1 ({nib_wr_en_d1[19:0], wr_en_d1}),`
141			`.sel (sehold),`
142			`.dout ({sehold_nib_wr_en[19:0], sehold_wr_en})`
143			`);`
144
145			`// modified to match circuit implementataion`
146	113	albert.wat	`dff_s #(21) dff_wr_ctrl_d1(`
147	95	fafa1971	`.din ({sehold_nib_wr_en[19:0], sehold_wr_en}),`
148			`.q ({nib_wr_en_d1[19:0], wr_en_d1}),`
149			`.clk (clk),`
150			`.se (se),`
151	113	albert.wat	`SIMPLY_RISC_SCANIN,
152	95	fafa1971	`.so ()`
153			`);`
154			`//`
155			`// write data`
156			`dp_mux2es #(80) mux_sehold_din (`
157			`.in0 (din[79:0]),`
158			`.in1 (din_d1[79:0]),`
159			`.sel (sehold),`
160			`.dout (sehold_din[79:0])`
161			`);`
162
163	113	albert.wat	`dff_s #(80) dff_din_d1(`
164	95	fafa1971	`.din (sehold_din[79:0]),`
165			`.q (din_d1[79:0]),`
166			`.clk (clk),`
167			`.se (se),`
168	113	albert.wat	`SIMPLY_RISC_SCANIN,
169	95	fafa1971	`.so ()`
170			`);`
171
172			`//`
173			`// diable write to register file during reset or scan`
174			`// assign wr_vld = sehold_wr_en & ~rst_tri_en & reset_l;`
175			`assign wr_vld = sehold_wr_en & ~rst_tri_en;`
176			`assign wr_vld_d1 = wr_en_d1 & ~rst_tri_en;`
177
178			`// always @ (posedge clk)`
179			`// begin`
180			`// so <= 1'bx;`
181			`// end`
182
183			`//=========================================================================================`
184			`// generate wordlines`
185			`//=========================================================================================`
186
187			`// Word-Line Generation skipped. Implicit in read and write.`
188
189			`//=========================================================================================`
190			`// write or read to/from memory`
191			`//=========================================================================================`
192			`// creating the write mask from the nibble enable controls`
193
194			`assign write_mask[79:0] =`
195			`{{4{sehold_nib_wr_en[19]}},`
196			`{4{sehold_nib_wr_en[18]}},`
197			`{4{sehold_nib_wr_en[17]}},`
198			`{4{sehold_nib_wr_en[16]}},`
199			`{4{sehold_nib_wr_en[15]}},`
200			`{4{sehold_nib_wr_en[14]}},`
201			`{4{sehold_nib_wr_en[13]}},`
202			`{4{sehold_nib_wr_en[12]}},`
203			`{4{sehold_nib_wr_en[11]}},`
204			`{4{sehold_nib_wr_en[10]}},`
205			`{4{sehold_nib_wr_en[9]}},`
206			`{4{sehold_nib_wr_en[8]}},`
207			`{4{sehold_nib_wr_en[7]}},`
208			`{4{sehold_nib_wr_en[6]}},`
209			`{4{sehold_nib_wr_en[5]}},`
210			`{4{sehold_nib_wr_en[4]}},`
211			`{4{sehold_nib_wr_en[3]}},`
212			`{4{sehold_nib_wr_en[2]}},`
213			`{4{sehold_nib_wr_en[1]}},`
214			`{4{sehold_nib_wr_en[0]}}`
215			`};`
216
217			`assign write_mask_d1[79:0] =`
218			`{{4{nib_wr_en_d1[19]}},`
219			`{4{nib_wr_en_d1[18]}},`
220			`{4{nib_wr_en_d1[17]}},`
221			`{4{nib_wr_en_d1[16]}},`
222			`{4{nib_wr_en_d1[15]}},`
223			`{4{nib_wr_en_d1[14]}},`
224			`{4{nib_wr_en_d1[13]}},`
225			`{4{nib_wr_en_d1[12]}},`
226			`{4{nib_wr_en_d1[11]}},`
227			`{4{nib_wr_en_d1[10]}},`
228			`{4{nib_wr_en_d1[9]}},`
229			`{4{nib_wr_en_d1[8]}},`
230			`{4{nib_wr_en_d1[7]}},`
231			`{4{nib_wr_en_d1[6]}},`
232			`{4{nib_wr_en_d1[5]}},`
233			`{4{nib_wr_en_d1[4]}},`
234			`{4{nib_wr_en_d1[3]}},`
235			`{4{nib_wr_en_d1[2]}},`
236			`{4{nib_wr_en_d1[1]}},`
237			`{4{nib_wr_en_d1[0]}}`
238			`};`
239
240			`reg [79:0] tsa_mem [NUM_ENTRIES-1:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;`
241
242			`reg [79:0] temp_tlvl;`
243			`wire [79:0] temp_tlvl2;`
244
245
246
247			`always @(posedge clk) begin`
248			`rd_adr_d1 <= sehold_rd_adr;`
249			`wr_adr_d1 <= sehold_wr_adr;`
250			`end`
251
252			`assign sehold_wr_adr = sehold ? wr_adr_d1 : wr_adr;`
253			`assign sehold_rd_adr = sehold ? rd_adr_d1 : rd_adr;`
254
255			`assign temp_tlvl2 = tsa_mem[sehold_rd_adr[4:0]];`
256
257			`always @(posedge clk)`
258			`if(~reset_l)`
259			`local_dout[79:0] <= 80'b0;`
260			`else`
261			`if (sehold_rd_en)`
262			`local_dout[79:0] <= temp_tlvl2;`
263
264			`always @ ( posedge clk) begin`
265			`temp_tlvl[79:0] = tsa_mem[sehold_wr_adr];`
266			`if (wr_vld & reset_l) begin`
267			`tsa_mem[sehold_wr_adr] = (temp_tlvl[79:0] & ~write_mask[79:0]) \| (sehold_din[79:0] & write_mask[79:0]) ;`
268			`end`
269			`end`
270
271
272			`assign dout[79:0] = local_dout;`
273
274
275
276			`endmodule`
277
278	113	albert.wat	`else
279	95	fafa1971
280	113	albert.wat	`module bw_r_rf32x80 (/AUTOARG/`
281			`// Outputs`
282			`dout, so,`
283			`// Inputs`
284			`rd_en, rd_adr, wr_en, nib_wr_en, wr_adr, din,`
285			`si, se, sehold, rclk, rst_tri_en, reset_l);`
286	95	fafa1971
287	113	albert.wat	`parameter NUM_TPL = 6 ; // 6 supported trap levels.`
288			`parameter NUM_ENTRIES = 32 ; // 8 entries per thread`
289	95	fafa1971
290	113	albert.wat	`/AUTOINPUT/`
291			`// Beginning of automatic inputs (from unused autoinst inputs)`
292			`// End of automatics`
293			`input [4:0] rd_adr; // read adr.`
294			`input rd_en; // read pointer`
295			`input wr_en; // write pointer vld`
296			`input [19:0] nib_wr_en; // enable write of a byte in tsa.`
297			`input [4:0] wr_adr; // write adr.`
298			`input [79:0] din; // wr data for tsa.`
299			`input rclk; // clock`
300			`input reset_l; // active low reset`
301			`input rst_tri_en; // reset and scan`
302			`input sehold; // scan hold`
303			`input si; // scan in`
304			`input se; // scan enable`
305	95	fafa1971
306	113	albert.wat	`/AUTOOUTPUT/`
307			`// Beginning of automatic outputs (from unused autoinst outputs)`
308			`// End of automatics`
309			`output [79:0] dout ; // rd data for tsa.`
310			`output so ; // scan out write`
311	95	fafa1971
312	113	albert.wat	`wire [79:0] dout;`
313			`wire clk;`
314			`wire wr_vld, wr_vld_d1;`
315	95	fafa1971
316	113	albert.wat	`reg [79:0] tsa_mem [NUM_ENTRIES-1:0];`
317			`reg [79:0] tsa_rdata;`
318			`reg [79:0] local_dout;`
319			`reg [79:0] temp_tlvl;`
320			`// reg so;`
321	95	fafa1971
322	113	albert.wat	`integer i,j;`
323	95	fafa1971
324	113	albert.wat	`wire [79:0] write_mask;`
325			`wire [79:0] write_mask_d1;`
326			`//`
327			`// added for atpg support`
328			`wire [4:0] sehold_rd_adr; // output of sehold mux - read adr.`
329			`wire sehold_rd_en; // output of sehold mux - read pointer`
330			`wire sehold_wr_en; // output of sehold mux - write pointer vld`
331			`wire [19:0] sehold_nib_wr_en; // output of sehold mux - enable write of a byte in tsa.`
332			`wire [4:0] sehold_wr_adr; // output of sehold mux - write adr.`
333			`wire [79:0] sehold_din; // wr data for tsa.`
334	95	fafa1971
335	113	albert.wat	`wire [4:0] rd_adr_d1; // flopped read adr.`
336			`wire rd_en_d1; // flopped read pointer`
337			`wire wr_en_d1; // flopped write pointer vld`
338			`wire [19:0] nib_wr_en_d1; // flopped enable write of a byte in tsa.`
339			`wire [4:0] wr_adr_d1; // flopped write adr.`
340			`wire [79:0] din_d1; // flopped wr data for tsa.`
341			`// wire [5:0] local_scan1;`
342			`// wire [25:0] local_scan2;`
343			`// wire [78:0] local_scan3;`
344	95	fafa1971
345	113	albert.wat	`//`
346			`// creating local clock`
347			`assign clk=rclk;`
348			`//`
349			`//=========================================================================================`
350			`// support for atpg pattern generation`
351			`//=========================================================================================`
352			`//`
353			`// read controls`
354			`dp_mux2es #(6) mux_sehold_rd_ctrl (`
355			`.in0 ({rd_adr[4:0], rd_en}),`
356			`.in1 ({rd_adr_d1[4:0], rd_en_d1}),`
357			`.sel (sehold),`
358			`.dout ({sehold_rd_adr[4:0],sehold_rd_en})`
359			`);`
360			`//`
361			`// modified to match circuit implementataion`
362			`dff_s #(6) dff_rd_ctrl_d1(`
363			`.din ({sehold_rd_adr[4:0], sehold_rd_en}),`
364			`.q ({rd_adr_d1[4:0], rd_en_d1}),`
365			`.clk (clk),`
366			`.se (se),`
367			`SIMPLY_RISC_SCANIN,
368			`.so ()`
369			`);`
370			`//`
371			`// write controls`
372			`// modified to match circuit implementataion`
373			`dp_mux2es #(26) mux_sehold_wr_ctrl (`
374			`.in0 ({nib_wr_en[19:0], wr_adr[4:0], wr_en}),`
375			`.in1 ({nib_wr_en_d1[19:0], wr_adr_d1[4:0], wr_en_d1}),`
376			`.sel (sehold),`
377			`.dout ({sehold_nib_wr_en[19:0], sehold_wr_adr[4:0],sehold_wr_en})`
378			`);`
379	95	fafa1971
380	113	albert.wat	`// modified to match circuit implementataion`
381			`dff_s #(26) dff_wr_ctrl_d1(`
382			`.din ({sehold_nib_wr_en[19:0], sehold_wr_adr[4:0], sehold_wr_en}),`
383			`.q ({nib_wr_en_d1[19:0], wr_adr_d1[4:0], wr_en_d1}),`
384			`.clk (clk),`
385			`.se (se),`
386			`SIMPLY_RISC_SCANIN,
387			`.so ()`
388			`);`
389			`//`
390			`// write data`
391			`dp_mux2es #(80) mux_sehold_din (`
392			`.in0 (din[79:0]),`
393			`.in1 (din_d1[79:0]),`
394			`.sel (sehold),`
395			`.dout (sehold_din[79:0])`
396			`);`
397	95	fafa1971
398	113	albert.wat	`dff_s #(80) dff_din_d1(`
399			`.din (sehold_din[79:0]),`
400			`.q (din_d1[79:0]),`
401			`.clk (clk),`
402			`.se (se),`
403			`SIMPLY_RISC_SCANIN,
404			`.so ()`
405			`);`
406	95	fafa1971
407	113	albert.wat	`//`
408			`// diable write to register file during reset or scan`
409			`// assign wr_vld = sehold_wr_en & ~rst_tri_en & reset_l;`
410			`assign wr_vld = sehold_wr_en & ~rst_tri_en;`
411			`assign wr_vld_d1 = wr_en_d1 & ~rst_tri_en;`
412	95	fafa1971
413	113	albert.wat	`// always @ (posedge clk)`
414			`// begin`
415			`// so <= 1'bx;`
416			`// end`
417	95	fafa1971
418	113	albert.wat	`//=========================================================================================`
419			`// generate wordlines`
420			`//=========================================================================================`
421	95	fafa1971
422	113	albert.wat	`// Word-Line Generation skipped. Implicit in read and write.`
423	95	fafa1971
424	113	albert.wat	`//=========================================================================================`
425			`// write or read to/from memory`
426			`//=========================================================================================`
427			`// creating the write mask from the nibble enable controls`
428	95	fafa1971
429	113	albert.wat	`assign write_mask[79:0] =`
430			`{{4{sehold_nib_wr_en[19]}},`
431			`{4{sehold_nib_wr_en[18]}},`
432			`{4{sehold_nib_wr_en[17]}},`
433			`{4{sehold_nib_wr_en[16]}},`
434			`{4{sehold_nib_wr_en[15]}},`
435			`{4{sehold_nib_wr_en[14]}},`
436			`{4{sehold_nib_wr_en[13]}},`
437			`{4{sehold_nib_wr_en[12]}},`
438			`{4{sehold_nib_wr_en[11]}},`
439			`{4{sehold_nib_wr_en[10]}},`
440			`{4{sehold_nib_wr_en[9]}},`
441			`{4{sehold_nib_wr_en[8]}},`
442			`{4{sehold_nib_wr_en[7]}},`
443			`{4{sehold_nib_wr_en[6]}},`
444			`{4{sehold_nib_wr_en[5]}},`
445			`{4{sehold_nib_wr_en[4]}},`
446			`{4{sehold_nib_wr_en[3]}},`
447			`{4{sehold_nib_wr_en[2]}},`
448			`{4{sehold_nib_wr_en[1]}},`
449			`{4{sehold_nib_wr_en[0]}}`
450			`};`
451	95	fafa1971
452	113	albert.wat	`assign write_mask_d1[79:0] =`
453			`{{4{nib_wr_en_d1[19]}},`
454			`{4{nib_wr_en_d1[18]}},`
455			`{4{nib_wr_en_d1[17]}},`
456			`{4{nib_wr_en_d1[16]}},`
457			`{4{nib_wr_en_d1[15]}},`
458			`{4{nib_wr_en_d1[14]}},`
459			`{4{nib_wr_en_d1[13]}},`
460			`{4{nib_wr_en_d1[12]}},`
461			`{4{nib_wr_en_d1[11]}},`
462			`{4{nib_wr_en_d1[10]}},`
463			`{4{nib_wr_en_d1[9]}},`
464			`{4{nib_wr_en_d1[8]}},`
465			`{4{nib_wr_en_d1[7]}},`
466			`{4{nib_wr_en_d1[6]}},`
467			`{4{nib_wr_en_d1[5]}},`
468			`{4{nib_wr_en_d1[4]}},`
469			`{4{nib_wr_en_d1[3]}},`
470			`{4{nib_wr_en_d1[2]}},`
471			`{4{nib_wr_en_d1[1]}},`
472			`{4{nib_wr_en_d1[0]}}`
473			`};`
474	95	fafa1971
475	113	albert.wat	`always @ ( negedge reset_l)`
476			`begin`
477			`local_dout[79:0] <= 80'h0;`
478			`end`
479	95	fafa1971
480	113	albert.wat	`always @ ( posedge reset_l)`
481			`begin`
482			`if (rd_en_d1 & clk)`
483			`begin`
484			`if (wr_vld_d1 & (wr_adr_d1[4:0] == rd_adr_d1[4:0]) )`
485			`local_dout[79:0] <= 80'hx;`
486			`else`
487			`for (j=0;j<NUM_ENTRIES;j=j+1)`
488			`begin`
489			`if (rd_adr_d1[4:0] == j)`
490			`local_dout[79:0] <= tsa_mem[j] ;`
491			`end`
492			`end`
493			`end`
494	95	fafa1971
495
496
497
498	113	albert.wat	`always @ ( posedge reset_l)`
499			`begin`
500			`if (wr_vld_d1 & clk)`

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