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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [cmp_sram_redhdr.v] - Blame information for rev 95

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// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T1 Processor File: cmp_sram_redhdr.v
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================
//
//    Cluster Name:  Efuse Cluster
//    Unit Name:  cmp_redhdr (sram redundancy header)
//    Block Name: EFC
//
//    This is the header used to read and write the fuse values to the
//    RAM blocks.  It is used to drive the ICD, DCD and L2T.  It is
//    outside the array it is driving.
//
//    Top level signal renaming:
//       s/ary/<your_ary_name>/g
//       s/xfuse/<your_ary_initial>fuse/g
//
//       E.g.  fuse_ary_wren -> fuse_icd_wren
//             efc_spc_xfuse_data -> efc_spc_ifuse_data, efc_sct_fuse_data
//
//-----------------------------------------------------------------------------
/*
/* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T1 Processor File: sys.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
// -*- verilog -*-
////////////////////////////////////////////////////////////////////////
/*
//
// Description:         Global header file that contain definitions that
//                      are common/shared at the systme level
*/
////////////////////////////////////////////////////////////////////////
//
// Setting the time scale
// If the timescale changes, JP_TIMESCALE may also have to change.
`timescale      1ps/1ps
 
//
// JBUS clock
// =========
//
 
 
 
// Afara Link Defines
// ==================
 
// Reliable Link
 
 
 
 
// Afara Link Objects
 
 
// Afara Link Object Format - Reliable Link
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Congestion
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Acknowledge
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Request
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Afara Link Object Format - Message
 
 
 
// Acknowledge Types
 
 
 
 
// Request Types
 
 
 
 
 
// Afara Link Frame
 
 
 
//
// UCB Packet Type
// ===============
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
// UCB Data Packet Format
// ======================
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Size encoding for the UCB_SIZE_HI/LO field
// 000 - byte
// 001 - half-word
// 010 - word
// 011 - double-word
// 111 - quad-word
 
 
 
 
 
 
 
//
// UCB Interrupt Packet Format
// ===========================
//
 
 
 
 
 
 
 
 
 
 
//`define UCB_THR_HI             9      // (6) cpu/thread ID shared with
//`define UCB_THR_LO             4             data packet format
//`define UCB_PKT_HI             3      // (4) packet type shared with
//`define UCB_PKT_LO             0      //     data packet format
 
 
 
 
 
 
 
//
// FCRAM Bus Widths
// ================
//
 
 
 
 
 
 
//
// ENET clock periods
// ==================
//
 
 
 
 
//
// JBus Bridge defines
// =================
//
 
 
 
 
 
 
 
 
 
 
 
//
// PCI Device Address Configuration
// ================================
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
/*
/* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T1 Processor File: iop.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
//-*- verilog -*-
////////////////////////////////////////////////////////////////////////
/*
//
//  Description:        Global header file that contain definitions that
//                      are common/shared at the IOP chip level
*/
////////////////////////////////////////////////////////////////////////
 
 
// Address Map Defines
// ===================
 
 
 
 
// CMP space
 
 
 
// IOP space
 
 
 
 
                               //`define ENET_ING_CSR     8'h84
                               //`define ENET_EGR_CMD_CSR 8'h85
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2 space
 
 
 
// More IOP space
 
 
 
 
 
//Cache Crossbar Width and Field Defines
//======================================
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//bits 133:128 are shared by different fields
//for different packet types.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//End cache crossbar defines
 
 
// Number of COS supported by EECU 
 
 
 
// 
// BSC bus sizes
// =============
//
 
// General
 
 
 
 
// CTags
 
 
 
 
 
 
 
 
 
 
 
 
 
// reinstated temporarily
 
 
 
 
// CoS
 
 
 
 
 
 
// L2$ Bank
 
 
 
// L2$ Req
 
 
 
 
 
 
 
 
 
 
 
 
 
// L2$ Ack
 
 
 
 
 
 
 
 
// Enet Egress Command Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Enet Egress Packet Unit
 
 
 
 
 
 
 
 
 
 
 
 
 
// This is cleaved in between Egress Datapath Ack's
 
 
 
 
 
 
 
 
// Enet Egress Datapath
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// In-Order / Ordered Queue: EEPU
// Tag is: TLEN, SOF, EOF, QID = 15
 
 
 
 
 
 
// Nack + Tag Info + CTag
 
 
 
 
// ENET Ingress Queue Management Req
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Queue Management Ack
 
 
 
 
 
 
 
 
// Enet Ingress Packet Unit
 
 
 
 
 
 
 
 
 
 
 
 
// ENET Ingress Packet Unit Ack
 
 
 
 
 
 
 
// In-Order / Ordered Queue: PCI
// Tag is: CTAG
 
 
 
 
 
// PCI-X Request
 
 
 
 
 
 
 
 
 
 
 
// PCI_X Acknowledge
 
 
 
 
 
 
 
 
 
 
 
//
// BSC array sizes
//================
//
 
 
 
 
 
 
 
 
 
 
 
 
// ECC syndrome bits per memory element
 
 
 
 
//
// BSC Port Definitions
// ====================
//
// Bits 7 to 4 of curr_port_id
 
 
 
 
 
 
 
 
// Number of ports of each type
 
 
// Bits needed to represent above
 
 
// How wide the linked list pointers are
// 60b for no payload (2CoS)
// 80b for payload (2CoS)
 
//`define BSC_OBJ_PTR   80
//`define BSC_HD1_HI    69
//`define BSC_HD1_LO    60
//`define BSC_TL1_HI    59
//`define BSC_TL1_LO    50
//`define BSC_CT1_HI    49
//`define BSC_CT1_LO    40
//`define BSC_HD0_HI    29
//`define BSC_HD0_LO    20
//`define BSC_TL0_HI    19
//`define BSC_TL0_LO    10
//`define BSC_CT0_HI     9
//`define BSC_CT0_LO     0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// I2C STATES in DRAMctl
 
 
 
 
 
 
 
//
// IOB defines
// ===========
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//`define IOB_INT_STAT_WIDTH   32
//`define IOB_INT_STAT_HI      31
//`define IOB_INT_STAT_LO       0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// fixme - double check address mapping
// CREG in `IOB_INT_CSR space
 
 
 
 
 
 
 
 
 
 
// CREG in `IOB_MAN_CSR space
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Address map for TAP access of SPARC ASI
 
 
 
 
 
 
 
 
 
 
 
 
 
//
// CIOP UCB Bus Width
// ==================
//
//`define IOB_EECU_WIDTH       16  // ethernet egress command
//`define EECU_IOB_WIDTH       16
 
//`define IOB_NRAM_WIDTH       16  // NRAM (RLDRAM previously)
//`define NRAM_IOB_WIDTH        4
 
 
 
 
//`define IOB_ENET_ING_WIDTH   32  // ethernet ingress
//`define ENET_ING_IOB_WIDTH    8
 
//`define IOB_ENET_EGR_WIDTH    4  // ethernet egress
//`define ENET_EGR_IOB_WIDTH    4
 
//`define IOB_ENET_MAC_WIDTH    4  // ethernet MAC
//`define ENET_MAC_IOB_WIDTH    4
 
 
 
 
//`define IOB_BSC_WIDTH         4  // BSC
//`define BSC_IOB_WIDTH         4
 
 
 
 
 
 
 
//`define IOB_CLSP_WIDTH        4  // clk spine unit
//`define CLSP_IOB_WIDTH        4
 
 
 
 
 
//
// CIOP UCB Buf ID Type
// ====================
//
 
 
 
//
// Interrupt Device ID
// ===================
//
// Caution: DUMMY_DEV_ID has to be 9 bit wide
//          for fields to line up properly in the IOB.
 
 
 
//
// Soft Error related definitions 
// ==============================
//
 
 
 
//
// CMP clock
// =========
//
 
 
 
 
//
// NRAM/IO Interface
// =================
//
 
 
 
 
 
 
 
 
 
 
//
// NRAM/ENET Interface
// ===================
//
 
 
 
 
 
 
 
//
// IO/FCRAM Interface
// ==================
//
 
 
 
 
 
 
//
// PCI Interface
// ==================
// Load/store size encodings
// -------------------------
// Size encoding
// 000 - byte
// 001 - half-word
// 010 - word
// 011 - double-word
// 100 - quad
 
 
 
 
 
 
//
// JBI<->SCTAG Interface
// =======================
// Outbound Header Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// Inbound Header Format
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
// JBI->IOB Mondo Header Format
// ============================
//
 
 
 
 
 
 
 
 
 
 
 
 
 
 
// JBI->IOB Mondo Bus Width/Cycle
// ==============================
// Cycle  1 Header[15:8]
// Cycle  2 Header[ 7:0]
// Cycle  3 J_AD[127:120]
// Cycle  4 J_AD[119:112]
// .....
// Cycle 18 J_AD[  7:  0]
 
 
 
//FPGA_SYN enables all FPGA related modifications
 
 
 
 
module cmp_sram_redhdr (/*AUTOARG*/
   // Outputs
   fuse_ary_wren, fuse_ary_rid, fuse_ary_repair_value,
   fuse_ary_repair_en, spc_efc_xfuse_data, scanout,
   // Inputs
   rclk, se, scanin, arst_l, testmode_l, efc_spc_fuse_clk1,
   efc_spc_fuse_clk2, efc_spc_xfuse_data, efc_spc_xfuse_ashift,
   efc_spc_xfuse_dshift, ary_fuse_repair_value, ary_fuse_repair_en
   );
 
   input                rclk;
   input                se;
   input                scanin;                 // CMP clock, L1 phase
   input    arst_l;
   input    testmode_l;
 
   // eFuse controller interface
   input                efc_spc_fuse_clk1;
   input                efc_spc_fuse_clk2;
   input                efc_spc_xfuse_data;
   input                efc_spc_xfuse_ashift;   // addr shift; low during rst
   input                efc_spc_xfuse_dshift;   // data shift; low during rst
 
   // interface to cache redundancy logic
   input [7:0] ary_fuse_repair_value;  //data out for redundancy register
   input [1:0] ary_fuse_repair_en;     //enable bits out 
 
 
   // outputs
   // interface to icache
   output      fuse_ary_wren;         //redundancy reg wr enable, qualified
   output [5:0] fuse_ary_rid;         //redundancy register id
   output [7:0] fuse_ary_repair_value;//data in for redundancy register
   output [1:0] fuse_ary_repair_en;   //enable bits to turn on redundancy
 
   // serial rd data to controller
   output       spc_efc_xfuse_data;
 
   // normal scan out
   output       scanout;
 
 
   assign fuse_ary_wren = 1'b0;
   assign fuse_ary_rid = 6'b0;
   assign fuse_ary_repair_value = 8'b0;
   assign fuse_ary_repair_en = 2'b0;
   assign spc_efc_xfuse_data = 1'b0;
   assign scanout = 1'b0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
endmodule // cmp_sram_redhdr
 
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// verilog-library-files:      ("../../common/rtl/swrvr_clib.v")
// verilog-auto-sense-defines-constant:t
// End:

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Subversion Repositories s1_core

[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [cmp_sram_redhdr.v] - Blame information for rev 95

Line No.	Rev	Author	Line
1	95	fafa1971	`// ========== Copyright Header Begin ==========================================`
2			`//`
3			`// OpenSPARC T1 Processor File: cmp_sram_redhdr.v`
4			`// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.`
5			`// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.`
6			`//`
7			`// The above named program is free software; you can redistribute it and/or`
8			`// modify it under the terms of the GNU General Public`
9			`// License version 2 as published by the Free Software Foundation.`
10			`//`
11			`// The above named program is distributed in the hope that it will be`
12			`// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
14			`// General Public License for more details.`
15			`//`
16			`// You should have received a copy of the GNU General Public`
17			`// License along with this work; if not, write to the Free Software`
18			`// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.`
19			`//`
20			`// ========== Copyright Header End ============================================`
21			`//`
22			`// Cluster Name: Efuse Cluster`
23			`// Unit Name: cmp_redhdr (sram redundancy header)`
24			`// Block Name: EFC`
25			`//`
26			`// This is the header used to read and write the fuse values to the`
27			`// RAM blocks. It is used to drive the ICD, DCD and L2T. It is`
28			`// outside the array it is driving.`
29			`//`
30			`// Top level signal renaming:`
31			`// s/ary/<your_ary_name>/g`
32			`// s/xfuse/<your_ary_initial>fuse/g`
33			`//`
34			`// E.g. fuse_ary_wren -> fuse_icd_wren`
35			`// efc_spc_xfuse_data -> efc_spc_ifuse_data, efc_sct_fuse_data`
36			`//`
37			`//-----------------------------------------------------------------------------`
38			`/*`
39			`/* ========== Copyright Header Begin ==========================================`
40			`*`
41			`* OpenSPARC T1 Processor File: sys.h`
42			`* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.`
43			`* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.`
44			`*`
45			`* The above named program is free software; you can redistribute it and/or`
46			`* modify it under the terms of the GNU General Public`
47			`* License version 2 as published by the Free Software Foundation.`
48			`*`
49			`* The above named program is distributed in the hope that it will be`
50			`* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of`
51			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
52			`* General Public License for more details.`
53			`*`
54			`* You should have received a copy of the GNU General Public`
55			`* License along with this work; if not, write to the Free Software`
56			`* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.`
57			`*`
58			`* ========== Copyright Header End ============================================`
59			`*/`
60			`// -- verilog --`
61			`////////////////////////////////////////////////////////////////////////`
62			`/*`
63			`//`
64			`// Description: Global header file that contain definitions that`
65			`// are common/shared at the systme level`
66			`*/`
67			`////////////////////////////////////////////////////////////////////////`
68			`//`
69			`// Setting the time scale`
70			`// If the timescale changes, JP_TIMESCALE may also have to change.`
71			`timescale 1ps/1ps
72
73			`//`
74			`// JBUS clock`
75			`// =========`
76			`//`
77
78
79
80			`// Afara Link Defines`
81			`// ==================`
82
83			`// Reliable Link`
84
85
86
87
88			`// Afara Link Objects`
89
90
91			`// Afara Link Object Format - Reliable Link`
92
93
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99
100
101
102			`// Afara Link Object Format - Congestion`
103
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111
112
113
114			`// Afara Link Object Format - Acknowledge`
115
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119
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123
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125
126			`// Afara Link Object Format - Request`
127
128
129
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131
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141
142
143
144			`// Afara Link Object Format - Message`
145
146
147
148			`// Acknowledge Types`
149
150
151
152
153			`// Request Types`
154
155
156
157
158
159			`// Afara Link Frame`
160
161
162
163			`//`
164			`// UCB Packet Type`
165			`// ===============`
166			`//`
167
168
169
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171
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181
182
183
184			`//`
185			`// UCB Data Packet Format`
186			`// ======================`
187			`//`
188
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216
217
218			`// Size encoding for the UCB_SIZE_HI/LO field`
219			`// 000 - byte`
220			`// 001 - half-word`
221			`// 010 - word`
222			`// 011 - double-word`
223			`// 111 - quad-word`
224
225
226
227
228
229
230
231			`//`
232			`// UCB Interrupt Packet Format`
233			`// ===========================`
234			`//`
235
236
237
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239
240
241
242
243
244
245			//`define UCB_THR_HI 9 // (6) cpu/thread ID shared with
246			//`define UCB_THR_LO 4 data packet format
247			//`define UCB_PKT_HI 3 // (4) packet type shared with
248			//`define UCB_PKT_LO 0 // data packet format
249
250
251
252
253
254
255
256			`//`
257			`// FCRAM Bus Widths`
258			`// ================`
259			`//`
260
261
262
263
264
265
266			`//`
267			`// ENET clock periods`
268			`// ==================`
269			`//`
270
271
272
273
274			`//`
275			`// JBus Bridge defines`
276			`// =================`
277			`//`
278
279
280
281
282
283
284
285
286
287
288
289			`//`
290			`// PCI Device Address Configuration`
291			`// ================================`
292			`//`
293
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315
316			`/*`
317			`/* ========== Copyright Header Begin ==========================================`
318			`*`
319			`* OpenSPARC T1 Processor File: iop.h`
320			`* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.`
321			`* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.`
322			`*`
323			`* The above named program is free software; you can redistribute it and/or`
324			`* modify it under the terms of the GNU General Public`
325			`* License version 2 as published by the Free Software Foundation.`
326			`*`
327			`* The above named program is distributed in the hope that it will be`
328			`* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of`
329			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
330			`* General Public License for more details.`
331			`*`
332			`* You should have received a copy of the GNU General Public`
333			`* License along with this work; if not, write to the Free Software`
334			`* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.`
335			`*`
336			`* ========== Copyright Header End ============================================`
337			`*/`
338			`//-- verilog --`
339			`////////////////////////////////////////////////////////////////////////`
340			`/*`
341			`//`
342			`// Description: Global header file that contain definitions that`
343			`// are common/shared at the IOP chip level`
344			`*/`
345			`////////////////////////////////////////////////////////////////////////`
346
347
348			`// Address Map Defines`
349			`// ===================`
350
351
352
353
354			`// CMP space`
355
356
357
358			`// IOP space`
359
360
361
362
363			//`define ENET_ING_CSR 8'h84
364			//`define ENET_EGR_CMD_CSR 8'h85
365
366
367
368
369
370
371
372
373
374
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376
377
378
379
380			`// L2 space`
381
382
383
384			`// More IOP space`
385
386
387
388
389
390			`//Cache Crossbar Width and Field Defines`
391			`//======================================`
392
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434
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436
437			`//bits 133:128 are shared by different fields`
438			`//for different packet types.`
439
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480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501			`//End cache crossbar defines`
502
503
504			`// Number of COS supported by EECU`
505
506
507
508			`//`
509			`// BSC bus sizes`
510			`// =============`
511			`//`
512
513			`// General`
514
515
516
517
518			`// CTags`
519
520
521
522
523
524
525
526
527
528
529
530
531
532			`// reinstated temporarily`
533
534
535
536
537			`// CoS`
538
539
540
541
542
543
544			`// L2$ Bank`
545
546
547
548			`// L2$ Req`
549
550
551
552
553
554
555
556
557
558
559
560
561
562			`// L2$ Ack`
563
564
565
566
567
568
569
570
571			`// Enet Egress Command Unit`
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586			`// Enet Egress Packet Unit`
587
588
589
590
591
592
593
594
595
596
597
598
599
600			`// This is cleaved in between Egress Datapath Ack's`
601
602
603
604
605
606
607
608
609			`// Enet Egress Datapath`
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626			`// In-Order / Ordered Queue: EEPU`
627			`// Tag is: TLEN, SOF, EOF, QID = 15`
628
629
630
631
632
633
634			`// Nack + Tag Info + CTag`
635
636
637
638
639			`// ENET Ingress Queue Management Req`
640
641
642
643
644
645
646
647
648
649
650
651
652			`// ENET Ingress Queue Management Ack`
653
654
655
656
657
658
659
660
661			`// Enet Ingress Packet Unit`
662
663
664
665
666
667
668
669
670
671
672
673
674			`// ENET Ingress Packet Unit Ack`
675
676
677
678
679
680
681
682			`// In-Order / Ordered Queue: PCI`
683			`// Tag is: CTAG`
684
685
686
687
688
689			`// PCI-X Request`
690
691
692
693
694
695
696
697
698
699
700
701			`// PCI_X Acknowledge`
702
703
704
705
706
707
708
709
710
711
712
713			`//`
714			`// BSC array sizes`
715			`//================`
716			`//`
717
718
719
720
721
722
723
724
725
726
727
728
729			`// ECC syndrome bits per memory element`
730
731
732
733
734			`//`
735			`// BSC Port Definitions`
736			`// ====================`
737			`//`
738			`// Bits 7 to 4 of curr_port_id`
739
740
741
742
743
744
745
746
747			`// Number of ports of each type`
748
749
750			`// Bits needed to represent above`
751
752
753			`// How wide the linked list pointers are`
754			`// 60b for no payload (2CoS)`
755			`// 80b for payload (2CoS)`
756
757			//`define BSC_OBJ_PTR 80
758			//`define BSC_HD1_HI 69
759			//`define BSC_HD1_LO 60
760			//`define BSC_TL1_HI 59
761			//`define BSC_TL1_LO 50
762			//`define BSC_CT1_HI 49
763			//`define BSC_CT1_LO 40
764			//`define BSC_HD0_HI 29
765			//`define BSC_HD0_LO 20
766			//`define BSC_TL0_HI 19
767			//`define BSC_TL0_LO 10
768			//`define BSC_CT0_HI 9
769			//`define BSC_CT0_LO 0
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804			`// I2C STATES in DRAMctl`
805
806
807
808
809
810
811
812			`//`
813			`// IOB defines`
814			`// ===========`
815			`//`
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835			//`define IOB_INT_STAT_WIDTH 32
836			//`define IOB_INT_STAT_HI 31
837			//`define IOB_INT_STAT_LO 0
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887			`// fixme - double check address mapping`
888			// CREG in `IOB_INT_CSR space
889
890
891
892
893
894
895
896
897
898
899			// CREG in `IOB_MAN_CSR space
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937			`// Address map for TAP access of SPARC ASI`
938
939
940
941
942
943
944
945
946
947
948
949
950
951			`//`
952			`// CIOP UCB Bus Width`
953			`// ==================`
954			`//`
955			//`define IOB_EECU_WIDTH 16 // ethernet egress command
956			//`define EECU_IOB_WIDTH 16
957
958			//`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
959			//`define NRAM_IOB_WIDTH 4
960
961
962
963
964			//`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
965			//`define ENET_ING_IOB_WIDTH 8
966
967			//`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
968			//`define ENET_EGR_IOB_WIDTH 4
969
970			//`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
971			//`define ENET_MAC_IOB_WIDTH 4
972
973
974
975
976			//`define IOB_BSC_WIDTH 4 // BSC
977			//`define BSC_IOB_WIDTH 4
978
979
980
981
982
983
984
985			//`define IOB_CLSP_WIDTH 4 // clk spine unit
986			//`define CLSP_IOB_WIDTH 4
987
988
989
990
991
992			`//`
993			`// CIOP UCB Buf ID Type`
994			`// ====================`
995			`//`
996
997
998
999			`//`
1000			`// Interrupt Device ID`
1001			`// ===================`
1002			`//`
1003			`// Caution: DUMMY_DEV_ID has to be 9 bit wide`
1004			`// for fields to line up properly in the IOB.`
1005
1006
1007
1008			`//`
1009			`// Soft Error related definitions`
1010			`// ==============================`
1011			`//`
1012
1013
1014
1015			`//`
1016			`// CMP clock`
1017			`// =========`
1018			`//`
1019
1020
1021
1022
1023			`//`
1024			`// NRAM/IO Interface`
1025			`// =================`
1026			`//`
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037			`//`
1038			`// NRAM/ENET Interface`
1039			`// ===================`
1040			`//`
1041
1042
1043
1044
1045
1046
1047
1048			`//`
1049			`// IO/FCRAM Interface`
1050			`// ==================`
1051			`//`
1052
1053
1054
1055
1056
1057
1058			`//`
1059			`// PCI Interface`
1060			`// ==================`
1061			`// Load/store size encodings`
1062			`// -------------------------`
1063			`// Size encoding`
1064			`// 000 - byte`
1065			`// 001 - half-word`
1066			`// 010 - word`
1067			`// 011 - double-word`
1068			`// 100 - quad`
1069
1070
1071
1072
1073
1074
1075			`//`
1076			`// JBI<->SCTAG Interface`
1077			`// =======================`
1078			`// Outbound Header Format`
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106			`// Inbound Header Format`
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127			`//`
1128			`// JBI->IOB Mondo Header Format`
1129			`// ============================`
1130			`//`
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145			`// JBI->IOB Mondo Bus Width/Cycle`
1146			`// ==============================`
1147			`// Cycle 1 Header[15:8]`
1148			`// Cycle 2 Header[ 7:0]`
1149			`// Cycle 3 J_AD[127:120]`
1150			`// Cycle 4 J_AD[119:112]`
1151			`// .....`
1152			`// Cycle 18 J_AD[ 7: 0]`
1153
1154
1155
1156			`//FPGA_SYN enables all FPGA related modifications`
1157
1158
1159
1160
1161			`module cmp_sram_redhdr (/AUTOARG/`
1162			`// Outputs`
1163			`fuse_ary_wren, fuse_ary_rid, fuse_ary_repair_value,`
1164			`fuse_ary_repair_en, spc_efc_xfuse_data, scanout,`
1165			`// Inputs`
1166			`rclk, se, scanin, arst_l, testmode_l, efc_spc_fuse_clk1,`
1167			`efc_spc_fuse_clk2, efc_spc_xfuse_data, efc_spc_xfuse_ashift,`
1168			`efc_spc_xfuse_dshift, ary_fuse_repair_value, ary_fuse_repair_en`
1169			`);`
1170
1171			`input rclk;`
1172			`input se;`
1173			`input scanin; // CMP clock, L1 phase`
1174			`input arst_l;`
1175			`input testmode_l;`
1176
1177			`// eFuse controller interface`
1178			`input efc_spc_fuse_clk1;`
1179			`input efc_spc_fuse_clk2;`
1180			`input efc_spc_xfuse_data;`
1181			`input efc_spc_xfuse_ashift; // addr shift; low during rst`
1182			`input efc_spc_xfuse_dshift; // data shift; low during rst`
1183
1184			`// interface to cache redundancy logic`
1185			`input [7:0] ary_fuse_repair_value; //data out for redundancy register`
1186			`input [1:0] ary_fuse_repair_en; //enable bits out`
1187
1188
1189			`// outputs`
1190			`// interface to icache`
1191			`output fuse_ary_wren; //redundancy reg wr enable, qualified`
1192			`output [5:0] fuse_ary_rid; //redundancy register id`
1193			`output [7:0] fuse_ary_repair_value;//data in for redundancy register`
1194			`output [1:0] fuse_ary_repair_en; //enable bits to turn on redundancy`
1195
1196			`// serial rd data to controller`
1197			`output spc_efc_xfuse_data;`
1198
1199			`// normal scan out`
1200			`output scanout;`
1201
1202
1203			`assign fuse_ary_wren = 1'b0;`
1204			`assign fuse_ary_rid = 6'b0;`
1205			`assign fuse_ary_repair_value = 8'b0;`
1206			`assign fuse_ary_repair_en = 2'b0;`
1207			`assign spc_efc_xfuse_data = 1'b0;`
1208			`assign scanout = 1'b0;`
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325			`endmodule // cmp_sram_redhdr`
1326
1327			`// Local Variables:`
1328			`// verilog-library-directories:("." "../../common/rtl")`
1329			`// verilog-library-files: ("../../common/rtl/swrvr_clib.v")`
1330			`// verilog-auto-sense-defines-constant:t`
1331			`// End:`