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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [include/] [sys.h] - Blame information for rev 113

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/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T1 Processor File: sys.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
// -*- verilog -*-
////////////////////////////////////////////////////////////////////////
/*
//
// Description:         Global header file that contain definitions that
//                      are common/shared at the systme level
*/
////////////////////////////////////////////////////////////////////////
//
// Setting the time scale
// If the timescale changes, JP_TIMESCALE may also have to change.
`timescale      1ps/1ps
 
//
// JBUS clock
// =========
//
`define SYSCLK_PERIOD   5000
 
 
// Afara Link Defines
// ==================
 
// Reliable Link
`define AL_RB_CNT       16
`define AL_RB_IDX        4
`define AL_RB_WINDOW    `AL_RB_IDX'd8
 
// Afara Link Objects
`define AL_OBJ_SZ      112
 
// Afara Link Object Format - Reliable Link
`define AL_RL_HI       111
`define AL_RL_LO       103
`define AL_RL_SZ         9
 
`define AL_ESN_HI      111
`define AL_ESN_LO      108
`define AL_SSN_HI      107
`define AL_SSN_LO      104
`define AL_ED          103
 
// Afara Link Object Format - Congestion
`define AL_CNG_HI      102
`define AL_CNG_LO       94
`define AL_CNG_SZ        9
 
`define AL_REQ_CNG     102
`define AL_BSCT_HI     101
`define AL_BSCT_LO      96
`define AL_EGR_P_CNG    95
`define AL_MARK         94
 
 
// Afara Link Object Format - Acknowledge
`define AL_ACK_SZ       21
`define AL_A_COS        93
`define AL_A_TYP_HI     92
`define AL_A_TYP_LO     91
`define AL_A_NACK       90
`define AL_A_TAG_HI     89
`define AL_A_TAG_LO     80
`define AL_A_PORT_HI    79
`define AL_A_PORT_LO    73
 
 
// Afara Link Object Format - Request
`define AL_REQ_SZ       73
`define AL_R_COS        72
`define AL_R_TYP_HI     71
`define AL_R_TYP_LO     70
`define AL_R_SCR_HI     69
`define AL_R_SCR_LO     67
`define AL_R_TCR_HI     66
`define AL_R_TCR_LO     64
`define AL_R_TAG_HI     63
`define AL_R_TAG_LO     54
`define AL_R_PORT_HI    53
`define AL_R_PORT_LO    47
`define AL_R_LEN_HI     46
`define AL_R_LEN_LO     40
`define AL_R_ADD_HI     39
`define AL_R_ADD_LO      0
 
// Afara Link Object Format - Message
`define AL_M_MQID_HI     2
`define AL_M_MQID_LO     0
 
// Acknowledge Types
`define AL_ACK_NONE   2'b00
`define AL_ACK_NPAY   2'b01
`define AL_ACK_WPAY   2'b10
 
// Request Types
`define AL_REQ_NONE   2'b00
`define AL_REQ_NPAY   2'b01
`define AL_REQ_WPAY   2'b10
`define AL_REQ_MSG    2'b11
 
// Afara Link Frame
`define AL_FRAME_SZ    144
 
 
//
// UCB Packet Type
// ===============
//
`define UCB_READ_NACK        4'b0000    // ack/nack types
`define UCB_READ_ACK         4'b0001
`define UCB_WRITE_ACK        4'b0010
`define UCB_IFILL_ACK        4'b0011
`define UCB_IFILL_NACK       4'b0111
 
`define UCB_READ_REQ         4'b0100    // req types
`define UCB_WRITE_REQ        4'b0101
`define UCB_IFILL_REQ        4'b0110
 
`define UCB_INT              4'b1000    // plain interrupt
`define UCB_INT_VEC          4'b1100    // interrupt with vector
`define UCB_RESET_VEC        4'b1101    // reset with vector
`define UCB_IDLE_VEC         4'b1110    // idle with vector
`define UCB_RESUME_VEC       4'b1111    // resume with vector
 
 
//
// UCB Data Packet Format
// ======================
//
`define UCB_NOPAY_PKT_WIDTH   64        // packet without payload
`define UCB_64PAY_PKT_WIDTH  128        // packet with 64 bit payload
`define UCB_128PAY_PKT_WIDTH 192        // packet with 128 bit payload
 
`define UCB_DATA_EXT_HI      191        // (64) extended data
`define UCB_DATA_EXT_LO      128
`define UCB_DATA_HI          127        // (64) data
`define UCB_DATA_LO           64
`define UCB_RSV_HI            63        // (9) reserved bits
`define UCB_RSV_LO            55
`define UCB_ADDR_HI           54        // (40) bit address
`define UCB_ADDR_LO           15
`define UCB_SIZE_HI           14        // (3) request size
`define UCB_SIZE_LO           12
`define UCB_BUF_HI            11        // (2) buffer ID
`define UCB_BUF_LO            10
`define UCB_THR_HI             9        // (6) cpu/thread ID
`define UCB_THR_LO             4
`define UCB_PKT_HI             3        // (4) packet type
`define UCB_PKT_LO             0
 
`define UCB_DATA_EXT_WIDTH    64
`define UCB_DATA_WIDTH        64
`define UCB_RSV_WIDTH          9
`define UCB_ADDR_WIDTH        40
`define UCB_SIZE_WIDTH         3
`define UCB_BUFID_WIDTH        2
`define UCB_THR_WIDTH          6
`define UCB_PKT_WIDTH          4
 
// Size encoding for the UCB_SIZE_HI/LO field
// 000 - byte
// 001 - half-word
// 010 - word
// 011 - double-word
// 111 - quad-word
`define UCB_SIZE_1B          3'b000
`define UCB_SIZE_2B          3'b001
`define UCB_SIZE_4B          3'b010
`define UCB_SIZE_8B          3'b011
`define UCB_SIZE_16B         3'b111
 
 
//
// UCB Interrupt Packet Format
// ===========================
//
`define UCB_INT_PKT_WIDTH     64
 
`define UCB_INT_RSV_HI        63        // (7) reserved bits
`define UCB_INT_RSV_LO        57
`define UCB_INT_VEC_HI        56        // (6) interrupt vector
`define UCB_INT_VEC_LO        51
`define UCB_INT_STAT_HI       50        // (32) interrupt status
`define UCB_INT_STAT_LO       19
`define UCB_INT_DEV_HI        18        // (9) device ID
`define UCB_INT_DEV_LO        10
//`define UCB_THR_HI             9      // (6) cpu/thread ID shared with
//`define UCB_THR_LO             4             data packet format
//`define UCB_PKT_HI             3      // (4) packet type shared with
//`define UCB_PKT_LO             0      //     data packet format
 
`define UCB_INT_RSV_WIDTH      7
`define UCB_INT_VEC_WIDTH      6
`define UCB_INT_STAT_WIDTH    32
`define UCB_INT_DEV_WIDTH      9
 
 
//
// FCRAM Bus Widths
// ================
//
`define FCRAM_DQ_WIDTH                16
`define FCRAM_DQS_WIDTH                2
`define FCRAM_ADDR_WIDTH              15
`define FCRAM_BA_WIDTH                 2
 
 
//
// ENET clock periods
// ==================
//
`define AXGRMII_CLK_PERIOD          6400 // 312.5MHz/2
`define ENET_GMAC_CLK_PERIOD        8000 // 125MHz
 
 
//
// JBus Bridge defines
// =================
//
`define      SYS_UPA_CLK        `SYS.upa_clk
`define      SYS_J_CLK          `SYS.j_clk
`define      SYS_P_CLK          `SYS.p_clk
`define      SYS_G_CLK          `SYS.g_clk
`define      JP_TIMESCALE       `timescale 1 ps / 1 ps
`define      PCI_CLK_PERIOD     15152                  //  66 MHz
`define      UPA_RD_CLK_PERIOD  6666                   // 150 MHz
`define      UPA_REF_CLK_PERIOD 7576                   // 132 MHz
`define      ICHIP_CLK_PERIOD   30304                  //  33 MHz
 
 
//
// PCI Device Address Configuration
// ================================
//
`define PRIM_SLAVE1_MEM0_L      64'h0000000000000000
`define PRIM_SLAVE1_MEM0_H      64'h000000003fff0000
`define PRIM_SLAVE1_IO0_L       64'h0000000000000000
`define PRIM_SLAVE1_IO0_H       64'h00000000002f0000
`define PRIM_SLAVE1_JBUS_BASE   64'h000007ff00000000
 
`define PRIM_SLAVE2_MEM0_L      64'h0000000040000000
`define PRIM_SLAVE2_MEM0_H      64'h00000000Dfffffff
`define PRIM_SLAVE2_IO0_L       64'h0000000000300000
`define PRIM_SLAVE2_IO0_H       64'h00000000005fffff
`define PRIM_SLAVE2_JBUS_BASE   64'h000007ff40000000
 
`define PCIB_SLAVE1_MEM0_L      64'h0000000000000000
`define PCIB_SLAVE1_MEM0_H      64'h000000003fff0000
`define PCIB_SLAVE1_IO0_L       64'h0000000000000000
`define PCIB_SLAVE1_IO0_H       64'h00000000002fffff
`define PCIB_SLAVE1_JBUS_BASE   64'h000007f780000000
 
`define PCIB_SLAVE2_MEM0_L      64'h0000000040000000
`define PCIB_SLAVE2_MEM0_H      64'h000000007fffffff
`define PCIB_SLAVE2_IO0_L       64'h0000000000300000
`define PCIB_SLAVE2_IO0_H       64'h00000000007fffff
`define PCIB_SLAVE2_JBUS_BASE   64'h000007f7c0000000

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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [include/] [sys.h] - Blame information for rev 113

Line No.	Rev	Author	Line
1	113	albert.wat	`/*`
2			`* ========== Copyright Header Begin ==========================================`
3			`*`
4			`* OpenSPARC T1 Processor File: sys.h`
5			`* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.`
6			`* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.`
7			`*`
8			`* The above named program is free software; you can redistribute it and/or`
9			`* modify it under the terms of the GNU General Public`
10			`* License version 2 as published by the Free Software Foundation.`
11			`*`
12			`* The above named program is distributed in the hope that it will be`
13			`* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
15			`* General Public License for more details.`
16			`*`
17			`* You should have received a copy of the GNU General Public`
18			`* License along with this work; if not, write to the Free Software`
19			`* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.`
20			`*`
21			`* ========== Copyright Header End ============================================`
22			`*/`
23			`// -- verilog --`
24			`////////////////////////////////////////////////////////////////////////`
25			`/*`
26			`//`
27			`// Description: Global header file that contain definitions that`
28			`// are common/shared at the systme level`
29			`*/`
30			`////////////////////////////////////////////////////////////////////////`
31			`//`
32			`// Setting the time scale`
33			`// If the timescale changes, JP_TIMESCALE may also have to change.`
34			`timescale 1ps/1ps
35
36			`//`
37			`// JBUS clock`
38			`// =========`
39			`//`
40			`define SYSCLK_PERIOD 5000
41
42
43			`// Afara Link Defines`
44			`// ==================`
45
46			`// Reliable Link`
47			`define AL_RB_CNT 16
48			`define AL_RB_IDX 4
49			`define AL_RB_WINDOW `AL_RB_IDX'd8
50
51			`// Afara Link Objects`
52			`define AL_OBJ_SZ 112
53
54			`// Afara Link Object Format - Reliable Link`
55			`define AL_RL_HI 111
56			`define AL_RL_LO 103
57			`define AL_RL_SZ 9
58
59			`define AL_ESN_HI 111
60			`define AL_ESN_LO 108
61			`define AL_SSN_HI 107
62			`define AL_SSN_LO 104
63			`define AL_ED 103
64
65			`// Afara Link Object Format - Congestion`
66			`define AL_CNG_HI 102
67			`define AL_CNG_LO 94
68			`define AL_CNG_SZ 9
69
70			`define AL_REQ_CNG 102
71			`define AL_BSCT_HI 101
72			`define AL_BSCT_LO 96
73			`define AL_EGR_P_CNG 95
74			`define AL_MARK 94
75
76
77			`// Afara Link Object Format - Acknowledge`
78			`define AL_ACK_SZ 21
79			`define AL_A_COS 93
80			`define AL_A_TYP_HI 92
81			`define AL_A_TYP_LO 91
82			`define AL_A_NACK 90
83			`define AL_A_TAG_HI 89
84			`define AL_A_TAG_LO 80
85			`define AL_A_PORT_HI 79
86			`define AL_A_PORT_LO 73
87
88
89			`// Afara Link Object Format - Request`
90			`define AL_REQ_SZ 73
91			`define AL_R_COS 72
92			`define AL_R_TYP_HI 71
93			`define AL_R_TYP_LO 70
94			`define AL_R_SCR_HI 69
95			`define AL_R_SCR_LO 67
96			`define AL_R_TCR_HI 66
97			`define AL_R_TCR_LO 64
98			`define AL_R_TAG_HI 63
99			`define AL_R_TAG_LO 54
100			`define AL_R_PORT_HI 53
101			`define AL_R_PORT_LO 47
102			`define AL_R_LEN_HI 46
103			`define AL_R_LEN_LO 40
104			`define AL_R_ADD_HI 39
105			`define AL_R_ADD_LO 0
106
107			`// Afara Link Object Format - Message`
108			`define AL_M_MQID_HI 2
109			`define AL_M_MQID_LO 0
110
111			`// Acknowledge Types`
112			`define AL_ACK_NONE 2'b00
113			`define AL_ACK_NPAY 2'b01
114			`define AL_ACK_WPAY 2'b10
115
116			`// Request Types`
117			`define AL_REQ_NONE 2'b00
118			`define AL_REQ_NPAY 2'b01
119			`define AL_REQ_WPAY 2'b10
120			`define AL_REQ_MSG 2'b11
121
122			`// Afara Link Frame`
123			`define AL_FRAME_SZ 144
124
125
126			`//`
127			`// UCB Packet Type`
128			`// ===============`
129			`//`
130			`define UCB_READ_NACK 4'b0000 // ack/nack types
131			`define UCB_READ_ACK 4'b0001
132			`define UCB_WRITE_ACK 4'b0010
133			`define UCB_IFILL_ACK 4'b0011
134			`define UCB_IFILL_NACK 4'b0111
135
136			`define UCB_READ_REQ 4'b0100 // req types
137			`define UCB_WRITE_REQ 4'b0101
138			`define UCB_IFILL_REQ 4'b0110
139
140			`define UCB_INT 4'b1000 // plain interrupt
141			`define UCB_INT_VEC 4'b1100 // interrupt with vector
142			`define UCB_RESET_VEC 4'b1101 // reset with vector
143			`define UCB_IDLE_VEC 4'b1110 // idle with vector
144			`define UCB_RESUME_VEC 4'b1111 // resume with vector
145
146
147			`//`
148			`// UCB Data Packet Format`
149			`// ======================`
150			`//`
151			`define UCB_NOPAY_PKT_WIDTH 64 // packet without payload
152			`define UCB_64PAY_PKT_WIDTH 128 // packet with 64 bit payload
153			`define UCB_128PAY_PKT_WIDTH 192 // packet with 128 bit payload
154
155			`define UCB_DATA_EXT_HI 191 // (64) extended data
156			`define UCB_DATA_EXT_LO 128
157			`define UCB_DATA_HI 127 // (64) data
158			`define UCB_DATA_LO 64
159			`define UCB_RSV_HI 63 // (9) reserved bits
160			`define UCB_RSV_LO 55
161			`define UCB_ADDR_HI 54 // (40) bit address
162			`define UCB_ADDR_LO 15
163			`define UCB_SIZE_HI 14 // (3) request size
164			`define UCB_SIZE_LO 12
165			`define UCB_BUF_HI 11 // (2) buffer ID
166			`define UCB_BUF_LO 10
167			`define UCB_THR_HI 9 // (6) cpu/thread ID
168			`define UCB_THR_LO 4
169			`define UCB_PKT_HI 3 // (4) packet type
170			`define UCB_PKT_LO 0
171
172			`define UCB_DATA_EXT_WIDTH 64
173			`define UCB_DATA_WIDTH 64
174			`define UCB_RSV_WIDTH 9
175			`define UCB_ADDR_WIDTH 40
176			`define UCB_SIZE_WIDTH 3
177			`define UCB_BUFID_WIDTH 2
178			`define UCB_THR_WIDTH 6
179			`define UCB_PKT_WIDTH 4
180
181			`// Size encoding for the UCB_SIZE_HI/LO field`
182			`// 000 - byte`
183			`// 001 - half-word`
184			`// 010 - word`
185			`// 011 - double-word`
186			`// 111 - quad-word`
187			`define UCB_SIZE_1B 3'b000
188			`define UCB_SIZE_2B 3'b001
189			`define UCB_SIZE_4B 3'b010
190			`define UCB_SIZE_8B 3'b011
191			`define UCB_SIZE_16B 3'b111
192
193
194			`//`
195			`// UCB Interrupt Packet Format`
196			`// ===========================`
197			`//`
198			`define UCB_INT_PKT_WIDTH 64
199
200			`define UCB_INT_RSV_HI 63 // (7) reserved bits
201			`define UCB_INT_RSV_LO 57
202			`define UCB_INT_VEC_HI 56 // (6) interrupt vector
203			`define UCB_INT_VEC_LO 51
204			`define UCB_INT_STAT_HI 50 // (32) interrupt status
205			`define UCB_INT_STAT_LO 19
206			`define UCB_INT_DEV_HI 18 // (9) device ID
207			`define UCB_INT_DEV_LO 10
208			//`define UCB_THR_HI 9 // (6) cpu/thread ID shared with
209			//`define UCB_THR_LO 4 data packet format
210			//`define UCB_PKT_HI 3 // (4) packet type shared with
211			//`define UCB_PKT_LO 0 // data packet format
212
213			`define UCB_INT_RSV_WIDTH 7
214			`define UCB_INT_VEC_WIDTH 6
215			`define UCB_INT_STAT_WIDTH 32
216			`define UCB_INT_DEV_WIDTH 9
217
218
219			`//`
220			`// FCRAM Bus Widths`
221			`// ================`
222			`//`
223			`define FCRAM_DQ_WIDTH 16
224			`define FCRAM_DQS_WIDTH 2
225			`define FCRAM_ADDR_WIDTH 15
226			`define FCRAM_BA_WIDTH 2
227
228
229			`//`
230			`// ENET clock periods`
231			`// ==================`
232			`//`
233			`define AXGRMII_CLK_PERIOD 6400 // 312.5MHz/2
234			`define ENET_GMAC_CLK_PERIOD 8000 // 125MHz
235
236
237			`//`
238			`// JBus Bridge defines`
239			`// =================`
240			`//`
241			`define SYS_UPA_CLK `SYS.upa_clk
242			`define SYS_J_CLK `SYS.j_clk
243			`define SYS_P_CLK `SYS.p_clk
244			`define SYS_G_CLK `SYS.g_clk
245			`define JP_TIMESCALE `timescale 1 ps / 1 ps
246			`define PCI_CLK_PERIOD 15152 // 66 MHz
247			`define UPA_RD_CLK_PERIOD 6666 // 150 MHz
248			`define UPA_REF_CLK_PERIOD 7576 // 132 MHz
249			`define ICHIP_CLK_PERIOD 30304 // 33 MHz
250
251
252			`//`
253			`// PCI Device Address Configuration`
254			`// ================================`
255			`//`
256			`define PRIM_SLAVE1_MEM0_L 64'h0000000000000000
257			`define PRIM_SLAVE1_MEM0_H 64'h000000003fff0000
258			`define PRIM_SLAVE1_IO0_L 64'h0000000000000000
259			`define PRIM_SLAVE1_IO0_H 64'h00000000002f0000
260			`define PRIM_SLAVE1_JBUS_BASE 64'h000007ff00000000
261
262			`define PRIM_SLAVE2_MEM0_L 64'h0000000040000000
263			`define PRIM_SLAVE2_MEM0_H 64'h00000000Dfffffff
264			`define PRIM_SLAVE2_IO0_L 64'h0000000000300000
265			`define PRIM_SLAVE2_IO0_H 64'h00000000005fffff
266			`define PRIM_SLAVE2_JBUS_BASE 64'h000007ff40000000
267
268			`define PCIB_SLAVE1_MEM0_L 64'h0000000000000000
269			`define PCIB_SLAVE1_MEM0_H 64'h000000003fff0000
270			`define PCIB_SLAVE1_IO0_L 64'h0000000000000000
271			`define PCIB_SLAVE1_IO0_H 64'h00000000002fffff
272			`define PCIB_SLAVE1_JBUS_BASE 64'h000007f780000000
273
274			`define PCIB_SLAVE2_MEM0_L 64'h0000000040000000
275			`define PCIB_SLAVE2_MEM0_H 64'h000000007fffffff
276			`define PCIB_SLAVE2_IO0_L 64'h0000000000300000
277			`define PCIB_SLAVE2_IO0_H 64'h00000000007fffff
278			`define PCIB_SLAVE2_JBUS_BASE 64'h000007f7c0000000