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// ========== Copyright Header Begin ==========================================

// 

// OpenSPARC T1 Processor File: lsu_dcdp.v

// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

// 

// The above named program is free software; you can redistribute it and/or

// modify it under the terms of the GNU General Public

// License version 2 as published by the Free Software Foundation.

// 

// The above named program is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

// General Public License for more details.

// 

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// ========== Copyright Header End ============================================

////////////////////////////////////////////////////////////////////////

/*

//      Description:    LSU Data Cache Data Path

//                      - Final Way-Select Mux.

//                      - Alignment, Sign-Extension, Endianness.

*/

////////////////////////////////////////////////////////////////////////

// Global header file includes

////////////////////////////////////////////////////////////////////////

// system level definition file which contains the /*

/* ========== Copyright Header Begin ==========================================

*

* OpenSPARC T1 Processor File: sys.h

* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

*

* The above named program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public

* License version 2 as published by the Free Software Foundation.

*

* The above named program is distributed in the hope that it will be

* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

* General Public License for more details.

*

* You should have received a copy of the GNU General Public

* License along with this work; if not, write to the Free Software

* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

*

* ========== Copyright Header End ============================================

*/

// -*- verilog -*-

////////////////////////////////////////////////////////////////////////

/*

//

// Description:         Global header file that contain definitions that

//                      are common/shared at the systme level

*/

////////////////////////////////////////////////////////////////////////

//

// Setting the time scale

// If the timescale changes, JP_TIMESCALE may also have to change.

`timescale      1ps/1ps

//

// JBUS clock

// =========

//

// Afara Link Defines

// ==================

// Reliable Link

// Afara Link Objects

// Afara Link Object Format - Reliable Link

// Afara Link Object Format - Congestion

// Afara Link Object Format - Acknowledge

// Afara Link Object Format - Request

// Afara Link Object Format - Message

// Acknowledge Types

// Request Types

// Afara Link Frame

//

// UCB Packet Type

// ===============

//

//

// UCB Data Packet Format

// ======================

//

// Size encoding for the UCB_SIZE_HI/LO field

// 000 - byte

// 001 - half-word

// 010 - word

// 011 - double-word

// 111 - quad-word

//

// UCB Interrupt Packet Format

// ===========================

//

//`define UCB_THR_HI             9      // (6) cpu/thread ID shared with

//`define UCB_THR_LO             4             data packet format

//`define UCB_PKT_HI             3      // (4) packet type shared with

//`define UCB_PKT_LO             0      //     data packet format

//

// FCRAM Bus Widths

// ================

//

//

// ENET clock periods

// ==================

//

//

// JBus Bridge defines

// =================

//

//

// PCI Device Address Configuration

// ================================

//

                                        // time scale definition

////////////////////////////////////////////////////////////////////////

// Local header file includes / local defines

////////////////////////////////////////////////////////////////////////

module lsu_dcdp ( /*AUTOARG*/

   // Outputs

   so, dcache_rdata_wb_buf, mbist_dcache_data_in,

   lsu_exu_dfill_data_w2, lsu_ffu_ld_data, stb_rdata_ramc_buf,

   // Inputs

   rclk, si, se, rst_tri_en, dcache_rdata_wb, dcache_rparity_wb,

   dcache_rdata_msb_w0_m, dcache_rdata_msb_w1_m,

   dcache_rdata_msb_w2_m, dcache_rdata_msb_w3_m, lsu_bist_rsel_way_e,

   dcache_alt_mx_sel_e, cache_way_hit_buf2, morphed_addr_m,

   signed_ldst_byte_m, signed_ldst_hw_m, signed_ldst_w_m,

   merge7_sel_byte0_m, merge7_sel_byte7_m, merge6_sel_byte1_m,

   merge6_sel_byte6_m, merge5_sel_byte2_m, merge5_sel_byte5_m,

   merge4_sel_byte3_m, merge4_sel_byte4_m, merge3_sel_byte0_m,

   merge3_sel_byte3_m, merge3_sel_byte4_m,

   merge3_sel_byte7_default_m, merge3_sel_byte_m, merge2_sel_byte1_m,

   merge2_sel_byte2_m, merge2_sel_byte5_m,

   merge2_sel_byte6_default_m, merge2_sel_byte_m, merge0_sel_byte0_m,

   merge0_sel_byte1_m, merge0_sel_byte2_m,

   merge0_sel_byte3_default_m, merge0_sel_byte4_m,

   merge0_sel_byte5_m, merge0_sel_byte6_m,

   merge0_sel_byte7_default_m, merge1_sel_byte0_m,

   merge1_sel_byte1_m, merge1_sel_byte2_m,

   merge1_sel_byte3_default_m, merge1_sel_byte4_m,

   merge1_sel_byte5_m, merge1_sel_byte6_m,

   merge1_sel_byte7_default_m, merge0_sel_byte_1h_m,

   merge1_sel_byte_1h_m, merge1_sel_byte_2h_m, stb_rdata_ramc

   ) ;

   input rclk;

   input si;

   input se;

   output so;

   input  rst_tri_en;

input  [63:0]  dcache_rdata_wb;

output [63:0]  dcache_rdata_wb_buf;

input [7:0] dcache_rparity_wb;

output [71:0] mbist_dcache_data_in;

output [63:0]            lsu_exu_dfill_data_w2;  // bypass data - d$ fill or hit

output [63:0]            lsu_ffu_ld_data ;             // ld data to frf

//=========================================

//dc_fill CP

//=========================================

   input [7:0]           dcache_rdata_msb_w0_m;    //from D$

   input [7:0]           dcache_rdata_msb_w1_m;    //from D$

   input [7:0]           dcache_rdata_msb_w2_m;    //from D$

   input [7:0]           dcache_rdata_msb_w3_m;    //from D$

   input [3:0]           lsu_bist_rsel_way_e;     //from qdp2

   input                 dcache_alt_mx_sel_e;

   input [3:0]           cache_way_hit_buf2;    //from dtlb

   input [7:0]           morphed_addr_m;  //from dctl

   input          signed_ldst_byte_m;    //from dctl

//   input          unsigned_ldst_byte_m;  //from dctl 

   input          signed_ldst_hw_m;      //from dctl

//   input          unsigned_ldst_hw_m;    //from dctl

   input          signed_ldst_w_m;       //from dctl

//   input          unsigned_ldst_w_m;     //from dctl

input                   merge7_sel_byte0_m;

input                   merge7_sel_byte7_m;

input                   merge6_sel_byte1_m;

input                   merge6_sel_byte6_m;

input                   merge5_sel_byte2_m;

input                   merge5_sel_byte5_m;

input                   merge4_sel_byte3_m;

input                   merge4_sel_byte4_m;

input                   merge3_sel_byte0_m;

input                   merge3_sel_byte3_m;

input                   merge3_sel_byte4_m;

input                   merge3_sel_byte7_default_m;

input                   merge3_sel_byte_m ;

input                   merge2_sel_byte1_m;

input                   merge2_sel_byte2_m;

input                   merge2_sel_byte5_m;

input                   merge2_sel_byte6_default_m;

input                   merge2_sel_byte_m ;

input                   merge0_sel_byte0_m, merge0_sel_byte1_m;

input                   merge0_sel_byte2_m, merge0_sel_byte3_default_m;

input                   merge0_sel_byte4_m, merge0_sel_byte5_m;

input                   merge0_sel_byte6_m, merge0_sel_byte7_default_m;

input                   merge1_sel_byte0_m, merge1_sel_byte1_m;

input                   merge1_sel_byte2_m, merge1_sel_byte3_default_m;

input                   merge1_sel_byte4_m, merge1_sel_byte5_m;

input                   merge1_sel_byte6_m, merge1_sel_byte7_default_m;

input                                merge0_sel_byte_1h_m ;

input                                merge1_sel_byte_1h_m, merge1_sel_byte_2h_m ;

   input [14:9]        stb_rdata_ramc;

   output [14:9]       stb_rdata_ramc_buf;

//wire   [3:1]           lsu_byp_byte_zero_extend ; // zero-extend for bypass bytes 7-1

wire   [7:1]           lsu_byp_byte_sign_extend ; // sign-extend by 1 for byp bytes 7-1

wire    [7:0]            byte0,byte1,byte2,byte3;

wire    [7:0]            byte4,byte5,byte6,byte7;

//wire [3:1] zero_extend_g;

wire [7:1] sign_extend_g;

wire    [7:0]            align_byte3 ;

wire    [7:0]            align_byte2 ;

wire    [7:0]            align_byte1_1h,align_byte1_2h;

wire    [7:0]            align_byte0_1h,align_byte0_2h ;

wire    [63:0]   align_byte ;

wire                   merge7_sel_byte0;

wire                   merge7_sel_byte7;

wire                   merge6_sel_byte1;

wire                   merge6_sel_byte6;

wire                   merge5_sel_byte2;

wire                   merge5_sel_byte5;

wire                   merge4_sel_byte3;

wire                   merge4_sel_byte4;

wire                   merge3_sel_byte0;

wire                   merge3_sel_byte3;

wire                   merge3_sel_byte4;

wire                   merge3_sel_byte7;

wire                   merge3_sel_byte ;

wire                   merge2_sel_byte1;

wire                   merge2_sel_byte2;

wire                   merge2_sel_byte5;

wire                   merge2_sel_byte6;

wire                   merge2_sel_byte ;

wire                   merge0_sel_byte0, merge0_sel_byte1;

wire                   merge0_sel_byte2, merge0_sel_byte3;

wire                   merge0_sel_byte4, merge0_sel_byte5;

wire                   merge0_sel_byte6, merge0_sel_byte7;

wire                   merge1_sel_byte0, merge1_sel_byte1;

wire                   merge1_sel_byte2, merge1_sel_byte3;

wire                   merge1_sel_byte4, merge1_sel_byte5;

wire                   merge1_sel_byte6, merge1_sel_byte7;

wire                                  merge0_sel_byte_1h ;

wire                                  merge1_sel_byte_1h, merge1_sel_byte_2h ;

   wire       clk;

   assign     clk = rclk;

   assign     stb_rdata_ramc_buf[14:9] = stb_rdata_ramc[14:9];

//=========================================================================================

//      Alignment of Fill Data

//=========================================================================================

// Alignment needs to be done for following reasons :

// - Write of data to irf on ld hit in l1.

// - Write of data to irf on ld fill to l1 after miss in l1.

// - Store of irf data to memory.

//      - Data must be aligned before write to stb.

//      - If data is bypassed from stb by ld then it will

//      need realignment thru dfq i.e., it looks like a fill.

// This applies to data either read from the dcache (hit) or dfq(fill on miss). 

assign  byte7[7:0] = dcache_rdata_wb[63:56];

assign  byte6[7:0] = dcache_rdata_wb[55:48];

assign  byte5[7:0] = dcache_rdata_wb[47:40];

assign  byte4[7:0] = dcache_rdata_wb[39:32];

assign  byte3[7:0] = dcache_rdata_wb[31:24];

assign  byte2[7:0] = dcache_rdata_wb[23:16];

assign  byte1[7:0] = dcache_rdata_wb[15:8];

assign  byte0[7:0] = dcache_rdata_wb[7:0];

//assign        zero_extend_g[3:1] = lsu_byp_byte_zero_extend[3:1] ;

assign  sign_extend_g[7:1] = lsu_byp_byte_sign_extend[7:1] ;

//buffer

   assign     dcache_rdata_wb_buf[63:0] = dcache_rdata_wb[63:0];

   assign     mbist_dcache_data_in[71:0] = {dcache_rdata_wb_buf[63:0], dcache_rparity_wb[7:0]};

// Final endian/justified/sign-extend Byte 0.

//assign        align_byte0_1h[7:0]

//      = merge0_sel_byte0 ? byte0[7:0] :

//                merge0_sel_byte1 ? byte1[7:0] :

//                        merge0_sel_byte2 ? byte2[7:0] :

//                                merge0_sel_byte3 ?  byte3[7:0] :

//                                        8'hxx ;

   wire       merge0_sel_byte0_mxsel0, merge0_sel_byte1_mxsel1, merge0_sel_byte2_mxsel2, merge0_sel_byte3_mxsel3;

   assign     merge0_sel_byte0_mxsel0 = merge0_sel_byte0 & ~rst_tri_en;

   assign     merge0_sel_byte1_mxsel1 = merge0_sel_byte1 & ~rst_tri_en;

   assign     merge0_sel_byte2_mxsel2 = merge0_sel_byte2 & ~rst_tri_en;

   assign     merge0_sel_byte3_mxsel3 = merge0_sel_byte3 |  rst_tri_en;

mux4ds #(8) align_byte0_1h_mx (

      .in0 (byte0[7:0]),

      .in1 (byte1[7:0]),

      .in2 (byte2[7:0]),

      .in3 (byte3[7:0]),

      .sel0(merge0_sel_byte0_mxsel0),

      .sel1(merge0_sel_byte1_mxsel1),

      .sel2(merge0_sel_byte2_mxsel2),

      .sel3(merge0_sel_byte3_mxsel3),

      .dout(align_byte0_1h[7:0])

);

//assign        align_byte0_2h[7:0]

//      = merge0_sel_byte4 ? byte4[7:0] :

//                merge0_sel_byte5 ? byte5[7:0] :

//                        merge0_sel_byte6 ? byte6[7:0] :

//                                merge0_sel_byte7 ? byte7[7:0] :

//                                        8'hxx ;

   wire       merge0_sel_byte4_mxsel0, merge0_sel_byte5_mxsel1, merge0_sel_byte6_mxsel2, merge0_sel_byte7_mxsel3;

   assign     merge0_sel_byte4_mxsel0 = merge0_sel_byte4 & ~rst_tri_en;

   assign     merge0_sel_byte5_mxsel1 = merge0_sel_byte5 & ~rst_tri_en;

   assign     merge0_sel_byte6_mxsel2 = merge0_sel_byte6 & ~rst_tri_en;

   assign     merge0_sel_byte7_mxsel3 = merge0_sel_byte7 |  rst_tri_en;

mux4ds #(8) align_byte0_2h_mx (

      .in0 (byte4[7:0]),

      .in1 (byte5[7:0]),

      .in2 (byte6[7:0]),

      .in3 (byte7[7:0]),

      .sel0(merge0_sel_byte4_mxsel0),

      .sel1(merge0_sel_byte5_mxsel1),

      .sel2(merge0_sel_byte6_mxsel2),

      .sel3(merge0_sel_byte7_mxsel3),

      .dout(align_byte0_2h[7:0])

);

// No sign-extension or zero-extension for byte0

//assign        align_byte[7:0] 

//      = merge0_sel_byte_1h ? align_byte0_1h[7:0] :

//                                      align_byte0_2h[7:0] ;

   assign align_byte[7:0] = merge0_sel_byte_1h ? align_byte0_1h[7:0] :

                                                 align_byte0_2h[7:0];

// Final endian/justified/sign-extend Byte 1.

// *** The path thru byte1 is the most critical ***

//assign        align_byte1_1h[7:0]

//      = merge1_sel_byte0 ? byte0[7:0] :

//                merge1_sel_byte1 ? byte1[7:0] :

//                        merge1_sel_byte2 ? byte2[7:0] :

//                                merge1_sel_byte3 ? byte3[7:0] :

//                                              8'hxx ;

   wire       merge1_sel_byte0_mxsel0, merge1_sel_byte1_mxsel1, merge1_sel_byte2_mxsel2, merge1_sel_byte3_mxsel3;

   assign     merge1_sel_byte0_mxsel0 = merge1_sel_byte0 & ~rst_tri_en;

   assign     merge1_sel_byte1_mxsel1 = merge1_sel_byte1 & ~rst_tri_en;

   assign     merge1_sel_byte2_mxsel2 = merge1_sel_byte2 & ~rst_tri_en;

   assign     merge1_sel_byte3_mxsel3 = merge1_sel_byte3 |  rst_tri_en;

mux4ds #(8) align_byte1_1h_mx (

    .in0 (byte0[7:0]),

    .in1 (byte1[7:0]),

    .in2 (byte2[7:0]),

    .in3 (byte3[7:0]),

    .sel0(merge1_sel_byte0_mxsel0),

    .sel1(merge1_sel_byte1_mxsel1),

    .sel2(merge1_sel_byte2_mxsel2),

    .sel3(merge1_sel_byte3_mxsel3),

    .dout(align_byte1_1h[7:0])

);

//assign        align_byte1_2h[7:0]

//      = merge1_sel_byte4 ? byte4[7:0] :

//                merge1_sel_byte5 ? byte5[7:0] :

//                        merge1_sel_byte6 ? byte6[7:0] :

//                                      merge1_sel_byte7 ? byte7[7:0] :

//                                              8'hxx ; 

   wire       merge1_sel_byte4_mxsel0, merge1_sel_byte5_mxsel1, merge1_sel_byte6_mxsel2, merge1_sel_byte7_mxsel3;

   assign     merge1_sel_byte4_mxsel0 = merge1_sel_byte4 & ~rst_tri_en;

   assign     merge1_sel_byte5_mxsel1 = merge1_sel_byte5 & ~rst_tri_en;

   assign     merge1_sel_byte6_mxsel2 = merge1_sel_byte6 & ~rst_tri_en;

   assign     merge1_sel_byte7_mxsel3 = merge1_sel_byte7 |  rst_tri_en;

mux4ds #(8) align_byte1_2h_mx (

    .in0 (byte4[7:0]),

    .in1 (byte5[7:0]),

    .in2 (byte6[7:0]),

    .in3 (byte7[7:0]),

    .sel0(merge1_sel_byte4_mxsel0),

    .sel1(merge1_sel_byte5_mxsel1),

    .sel2(merge1_sel_byte6_mxsel2),

    .sel3(merge1_sel_byte7_mxsel3),

    .dout(align_byte1_2h[7:0])

);

//assign        align_byte[15:8] =      

//      zero_extend_g[1] ? 8'h00 :

//              sign_extend_g[1] ? 8'hff :

//                      merge1_sel_byte_1h ? align_byte1_1h[7:0] :

//                              merge1_sel_byte_2h ? align_byte1_2h[7:0] :

//                                              8'hxx ;

//mux4ds #(8) align_byte1_mx (

//    .in0 (8'h00),

//    .in1 (8'hff),

//    .in2 (align_byte1_1h[7:0]), 

//    .in3 (align_byte1_2h[7:0]),

//    .sel0(zero_extend_g[1]),

//    .sel1(sign_extend_g[1]),

//    .sel2(merge1_sel_byte_1h),

//    .sel3(merge1_sel_byte_2h),

//    .dout(align_byte[15:8])

//);

   //change to aoi from pass gate

   //don't need zero_extend

assign  align_byte[15:8] =

 (sign_extend_g[1] ? 8'hff : 8'h00) |

 (merge1_sel_byte_1h ? align_byte1_1h[7:0] : 8'h00) |

 (merge1_sel_byte_2h ? align_byte1_2h[7:0] : 8'h00);

// Final endian/justified/sign-extend Byte 2.

//assign        align_byte2[7:0]

//      = merge2_sel_byte1 ? byte1[7:0] :

//                merge2_sel_byte2 ? byte2[7:0] :

//                                      merge2_sel_byte5 ? byte5[7:0] :

//           merge2_sel_byte6 ?  byte6[7:0] :

//                                                      8'hxx ;

   wire       merge2_sel_byte1_mxsel0, merge2_sel_byte2_mxsel1, merge2_sel_byte5_mxsel2, merge2_sel_byte6_mxsel3;

   assign     merge2_sel_byte1_mxsel0 = merge2_sel_byte1 & ~rst_tri_en;

   assign     merge2_sel_byte2_mxsel1 = merge2_sel_byte2 & ~rst_tri_en;

   assign     merge2_sel_byte5_mxsel2 = merge2_sel_byte5 & ~rst_tri_en;

   assign     merge2_sel_byte6_mxsel3 = merge2_sel_byte6 |  rst_tri_en;

mux4ds #(8) align_byte2_1st_mx (

         .in0 (byte1[7:0]),

         .in1 (byte2[7:0]),

         .in2 (byte5[7:0]),

         .in3 (byte6[7:0]),

         .sel0(merge2_sel_byte1_mxsel0),

         .sel1(merge2_sel_byte2_mxsel1),

         .sel2(merge2_sel_byte5_mxsel2),

         .sel3(merge2_sel_byte6_mxsel3),

         .dout(align_byte2[7:0])

                                );

//assign        align_byte[23:16] =     

//      zero_extend_g[2] ? 8'h00 :

//              sign_extend_g[2] ? 8'hff :

//                              merge2_sel_byte ? align_byte2[7:0] :

//                                                              8'hxx ;

//mux3ds #(8) align_byte2_2nd_mx  (

//         .in0 (8'h00),

//         .in1 (8'hff),

//         .in2 (align_byte2[7:0]),

//         .sel0(zero_extend_g[2]),

//         .sel1(sign_extend_g[2]),

//         .sel2(merge2_sel_byte),

//         .dout(align_byte[23:16])

//                                      );

assign    align_byte[23:16] =

( sign_extend_g[2] ? 8'hff : 8'h00) |

(  merge2_sel_byte ? align_byte2[7:0] : 8'h00);

// Final endian/justified/sign-extend Byte 3.

//assign        align_byte3[7:0]

//      = merge3_sel_byte0 ? byte0[7:0] :

//                      merge3_sel_byte3 ? byte3[7:0] :

//                              merge3_sel_byte4 ? byte4[7:0] :

//                              merge3_sel_byte7 ? byte7[7:0] :

//                                        8'hxx ;

   wire       merge3_sel_byte0_mxsel0, merge3_sel_byte3_mxsel1, merge3_sel_byte4_mxsel2, merge3_sel_byte7_mxsel3;

   assign     merge3_sel_byte0_mxsel0 = merge3_sel_byte0 & ~rst_tri_en;

   assign     merge3_sel_byte3_mxsel1 = merge3_sel_byte3 & ~rst_tri_en;

   assign     merge3_sel_byte4_mxsel2 = merge3_sel_byte4 & ~rst_tri_en;

   assign     merge3_sel_byte7_mxsel3 = merge3_sel_byte7 |  rst_tri_en;

mux4ds #(8) align_byte3_1st_mx (

         .in0 (byte0[7:0]),

         .in1 (byte3[7:0]),

         .in2 (byte4[7:0]),

         .in3 (byte7[7:0]),

         .sel0(merge3_sel_byte0_mxsel0),

         .sel1(merge3_sel_byte3_mxsel1),

         .sel2(merge3_sel_byte4_mxsel2),

         .sel3(merge3_sel_byte7_mxsel3),

         .dout(align_byte3[7:0])

                                     );

//assign        align_byte[31:24] =     

//      zero_extend_g[3] ? 8'h00 :

//              sign_extend_g[3] ? 8'hff :

//                      merge3_sel_byte ? align_byte3[7:0] :

//                              8'hxx ;

//mux3ds #(8) align_byte3_2nd_mx (

//         .in0 (8'h00),

//         .in1 (8'hff), 

//         .in2 (align_byte3[7:0]),

//         .sel0(zero_extend_g[3]),

//         .sel1(sign_extend_g[3]),

//         .sel2(merge3_sel_byte),

//         .dout(align_byte[31:24])

//                                     );

assign    align_byte[31:24] =

  (sign_extend_g[3] ? 8'hff : 8'h00 ) |

  (merge3_sel_byte  ?  align_byte3[7:0] : 8'h00);

// Final endian/justified/sign-extend Byte 4.