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// ========== Copyright Header Begin ==========================================

// 

// OpenSPARC T1 Processor File: lsu_excpctl.v

// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

// 

// The above named program is free software; you can redistribute it and/or

// modify it under the terms of the GNU General Public

// License version 2 as published by the Free Software Foundation.

// 

// The above named program is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

// General Public License for more details.

// 

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// ========== Copyright Header End ============================================

`ifdef SIMPLY_RISC_TWEAKS

`define SIMPLY_RISC_SCANIN .si(0)

`else

`define SIMPLY_RISC_SCANIN .si()

`endif

/////////////////////////////////////////////////////////////////

`include "sys.h"

`include "lsu.h"

module lsu_excpctl ( /*AUTOARG*/

   // Outputs

   so, lsu_exu_st_dtlb_perr_g, lsu_ffu_st_dtlb_perr_g,

   lsu_defr_trp_taken_g, lsu_tlu_defr_trp_taken_g,

   lsu_mmu_defr_trp_taken_g, lsu_st_dtlb_perr_g,

   lsu_dmmu_sfsr_trp_wr, lsu_dsfsr_din_g, lsu_tlb_perr_ld_rq_kill_w,

   lsu_spu_early_flush_g, lsu_local_early_flush_g,

   lsu_tlu_early_flush_w, lsu_tlu_early_flush2_w, lsu_ttype_vld_m2,

   lsu_ttype_vld_m2_bf1, lsu_ifu_flush_pipe_w, lsu_exu_flush_pipe_w,

   lsu_mmu_flush_pipe_w, lsu_ffu_flush_pipe_w, lsu_tlu_wtchpt_trp_g,

   lsu_tlu_dmmu_miss_g, lsu_tlu_misalign_addr_ldst_atm_m,

   lsu_tlu_daccess_excptn_g, lsu_tlu_daccess_prot_g,

   lsu_tlu_priv_action_g, lsu_ifu_tlb_data_su, lsu_ifu_tlb_data_ue,

   lsu_ifu_tlb_tag_ue, lsu_tlu_ttype_m2, lsu_tlu_ttype_vld_m2,

   stb_cam_sqsh_msk, stb_cam_hit_bf, stb_cam_hit_bf1,

   tte_data_perror_unc, asi_tte_data_perror, asi_tte_tag_perror,

   // Inputs

   rclk, si, se, grst_l, arst_l, tlb_rd_tte_data_ebit,

   tlb_rd_tte_data_pbit, tlb_rd_tte_data_nfobit,

   tlb_rd_tte_data_wbit, tlb_cam_hit, tlb_pgnum_b39,

   lsu_ldst_va_b39_m, lsu_sun4r_va_m_l, lsu_sun4r_pgsz_b2t0_e,

   lsu_sun4v_pgsz_b2t0_e, tlu_early_flush_pipe_w, ifu_lsu_flush_w,

   ifu_lsu_nceen, lsu_tlb_asi_data_perr_g, lsu_tlb_asi_tag_perr_g,

   stb_state_vld0, stb_state_vld1, stb_state_vld2, stb_state_vld3,

   ifu_tlu_thrid_e, tlu_lsu_priv_trap_m, tlu_lsu_pstate_priv,

   st_inst_vld_e, ld_inst_vld_e, ifu_lsu_alt_space_e, lsu_ldst_va_m,

   hpv_priv_m, hpstate_en_m, stb_cam_hit, dtlb_bypass_m,

   lsu_alt_space_m, atomic_m, ldst_dbl_m, fp_ldst_m, lda_internal_m,

   sta_internal_m, cam_real_m, data_rd_vld_g, tag_rd_vld_g,

   ldst_sz_m, asi_internal_m, rd_only_ltlb_asi_e, wr_only_ltlb_asi_e,

   dfill_tlb_asi_e, ifill_tlb_asi_e, nofault_asi_m, as_if_user_asi_m,

   atomic_asi_m, phy_use_ec_asi_m, phy_byp_ec_asi_m, quad_asi_m,

   binit_quad_asi_m, blk_asi_m, recognized_asi_m, strm_asi_m,

   mmu_rd_only_asi_m, rd_only_asi_m, wr_only_asi_m, unimp_asi_m,

   lsu_nonalt_nucl_access_m, va_wtchpt_cmp_en_m,

   lsu_va_match_b47_b32_m, lsu_va_match_b31_b3_m,

   va_wtchpt_msk_match_m, ifu_tlu_inst_vld_m,

   exu_tlu_misalign_addr_jmpl_rtn_m, exu_tlu_va_oor_m,

   tlu_dsfsr_flt_vld, tlu_lsu_pstate_cle, tlu_lsu_pstate_am,

   lsu_excpctl_asi_state_m, lsu_tlu_nonalt_ldst_m,

   lsu_squash_va_oor_m, lsu_tlu_xslating_ldst_m, lsu_tlu_ctxt_sel_m,

   lsu_tlu_write_op_m, lsu_memref_m, lsu_flsh_inst_m,

   tte_data_parity_error, tte_tag_parity_error

   );

   input rclk;

   input si;

   input se;

   input grst_l;

   input arst_l;

   output so;

   //=================================================================

   // input from tlb

//   input [`STLB_DATA_NFO:`STLB_DATA_W] tlb_rd_tte_data ; // tte data from tlb

   input  tlb_rd_tte_data_ebit;

   input  tlb_rd_tte_data_pbit;

   input  tlb_rd_tte_data_nfobit;

   input  tlb_rd_tte_data_wbit;

   input                               tlb_cam_hit;

   input                               tlb_pgnum_b39;

//   input                               tlb_rd_tte_data_locked ;    // lock bit from tte

   //=================================================================

   input        lsu_ldst_va_b39_m ;

   input        lsu_sun4r_va_m_l ;

   input [2:0]   lsu_sun4r_pgsz_b2t0_e ;

   input [2:0]   lsu_sun4v_pgsz_b2t0_e ;

   input         tlu_early_flush_pipe_w;

   input         ifu_lsu_flush_w;

   input [3:0]   ifu_lsu_nceen ;             // uncorrectible error enable 

   input        lsu_tlb_asi_data_perr_g ;

   input        lsu_tlb_asi_tag_perr_g ;

   input [7:0]  stb_state_vld0 ;  // valid bits - stb0

   input [7:0]   stb_state_vld1 ;  // valid bits - stb1

   input [7:0]  stb_state_vld2 ;  // valid bits - stb2

   input [7:0]  stb_state_vld3 ;  // valid bits - stb3

   input [1:0]  ifu_tlu_thrid_e ; // thread-id.

   input        tlu_lsu_priv_trap_m ;   // daccess-excp in tlu

   output       lsu_exu_st_dtlb_perr_g ;

   output       lsu_ffu_st_dtlb_perr_g ;

   output       lsu_defr_trp_taken_g ;

   output       lsu_tlu_defr_trp_taken_g ;

   output       lsu_mmu_defr_trp_taken_g ;

   output [3:0]  lsu_st_dtlb_perr_g ;

   output [3:0]  lsu_dmmu_sfsr_trp_wr;      // sfsr wr based on trap.

   output [23:0] lsu_dsfsr_din_g;

   output lsu_tlb_perr_ld_rq_kill_w ;

   output lsu_spu_early_flush_g;

   output lsu_local_early_flush_g;   //to lsu

//   output lsu_dctl_early_flush_w;

   output lsu_tlu_early_flush_w;

   output lsu_tlu_early_flush2_w;

   output lsu_ttype_vld_m2;

   output lsu_ttype_vld_m2_bf1;

//   output     lsu_stbctl_flush_pipe_w ;

//   output     lsu_stbrwctl_flush_pipe_w ;

   //output lsu_flush_pipe_w;

   output lsu_ifu_flush_pipe_w;

   output lsu_exu_flush_pipe_w;

   output lsu_mmu_flush_pipe_w;

   output lsu_ffu_flush_pipe_w;

   output lsu_tlu_wtchpt_trp_g ;        // watchpt trap has occurred.

   output lsu_tlu_dmmu_miss_g;

   output lsu_tlu_misalign_addr_ldst_atm_m ; // mem_addr unaligned

//   output lsu_tlu_priv_violtn_g;

   wire   lsu_tlu_priv_violtn_g;

   output lsu_tlu_daccess_excptn_g;

   output lsu_tlu_daccess_prot_g;

   output lsu_tlu_priv_action_g;

//   output lsu_tlu_tte_ebit_g;

//   output lsu_tlu_spec_access_epage_g;

//   output lsu_tlu_uncache_atomic_g;

//   output lsu_tlu_illegal_asi_action_g;

//   output lsu_tlu_flt_ld_nfo_pg_g;

   //output lsu_tlu_asi_rd_unc;

   output lsu_ifu_tlb_data_su ;   // specific to st ue

   output lsu_ifu_tlb_data_ue ;   // dtlb data asi rd parity error ; now ld ue

   output lsu_ifu_tlb_tag_ue ;    // dtlb tag asi rd parity error

output [8:0]            lsu_tlu_ttype_m2;

output                  lsu_tlu_ttype_vld_m2;

   output  [7:0]   stb_cam_sqsh_msk ;  // squash spurious hits

   output       stb_cam_hit_bf;           // buffered stb_cam_hit for qctl1.

   output       stb_cam_hit_bf1;                // buffered stb_cam_hit for stb_rwctl, dctl.

   input [3:0]          tlu_lsu_pstate_priv ;

//   input [3:0]          tlu_lsu_hpv_priv;

//   input [3:0]          tlu_lsu_hpstate_en;

   input                st_inst_vld_e;

   input                ld_inst_vld_e;

   input                ifu_lsu_alt_space_e;        // alternate space ld/st

   //interface between lsu_dctldp

   input [7:0]          lsu_ldst_va_m;

   //interface between lsu_excpctl and lsu_dctl

   output               tte_data_perror_unc;

   //output               tte_data_perror_corr;

   output               asi_tte_data_perror ;

   output               asi_tte_tag_perror ;

   input hpv_priv_m;

   input hpstate_en_m;

   input                stb_cam_hit ;

   input                dtlb_bypass_m;

   input                lsu_alt_space_m;

   input                atomic_m;

//   input                atomic_g;

   input                ldst_dbl_m;

   input                fp_ldst_m;

//   input                lsu_inst_vld_w;

   input                lda_internal_m;

   input                sta_internal_m;

   input                cam_real_m;

//   input                va_wtchpt_match;

   input                data_rd_vld_g;

   input                tag_rd_vld_g;

   input [1:0]          ldst_sz_m;

   input                asi_internal_m;

//   input                dfill_thread0;

//   input                dfill_thread1;

//   input                dfill_thread2;

//   input                dfill_thread3;

   wire                ld_inst_vld_unflushed;

   wire                st_inst_vld_unflushed;

//   input                flsh_inst_g;

//   input                unc_err_trap_g;

   //asi decode

   input                rd_only_ltlb_asi_e;

   input                wr_only_ltlb_asi_e;

   input                dfill_tlb_asi_e;

   input                ifill_tlb_asi_e;

   input                nofault_asi_m;

   input                as_if_user_asi_m;

   input                atomic_asi_m;

   input                phy_use_ec_asi_m;

   input                phy_byp_ec_asi_m;

//   input                tlb_byp_asi_m;

   input                quad_asi_m;

   input                binit_quad_asi_m;

   input                blk_asi_m;

//   input                blk_cmt_asi_m;

   input                recognized_asi_m;

   input                strm_asi_m;

   input                mmu_rd_only_asi_m;

   input                rd_only_asi_m;

   input                wr_only_asi_m;

   input                unimp_asi_m;

   input                lsu_nonalt_nucl_access_m ;

   input    va_wtchpt_cmp_en_m;    //from dctl

   input    lsu_va_match_b47_b32_m;        //from qdp1

   input    lsu_va_match_b31_b3_m;         //from qdp1

   input    va_wtchpt_msk_match_m; //from dctldp

   input                ifu_tlu_inst_vld_m ;

input           exu_tlu_misalign_addr_jmpl_rtn_m;// misaligned addr - jmpl or return addr

input           exu_tlu_va_oor_m;               // ??? - to be used in sfsr

input [3:0]     tlu_dsfsr_flt_vld;

input [3:0]      tlu_lsu_pstate_cle ;       // current little endian

input [3:0]      tlu_lsu_pstate_am ;        // address mask

input  [7:0]    lsu_excpctl_asi_state_m ;   // ASI State + imm asi

input           lsu_tlu_nonalt_ldst_m ; // non-alternate load or store // FORCE

input           lsu_squash_va_oor_m ;   // squash va_oor for mem-op. // FORCE

input           lsu_tlu_xslating_ldst_m ;// xslating ldst,atomic etc // FORCE

input   [2:0]   lsu_tlu_ctxt_sel_m;           // context selected:0-p,1-s,2-n // FORCE

input           lsu_tlu_write_op_m; // FORCE

input           lsu_memref_m ;

input           lsu_flsh_inst_m ;

input    tte_data_parity_error ;

input    tte_tag_parity_error ;

wire    other_flush_pipe_w ;

wire    defr_trp_taken ;

wire    defr_trp_taken_m, defr_trp_taken_byp, defr_trp_taken_m_din ;

wire    tlb_tte_vld_m, tlb_tte_vld_g ;

wire    priv_pg_usr_mode_m, priv_pg_usr_mode_g, priv_pg_usr_mode;

wire    nfo_pg_nonnfo_asi_m, nfo_pg_nonnfo_asi_g, nfo_pg_nonnfo_asi;

wire    spec_access_epage_m, spec_access_epage_g, spec_access_epage ;

wire    nonwr_pg_st_access;

`ifdef SIMPLY_RISC_TWEAKS

wire va_wtchpt_en_g;

`endif

//=========================================================================================

// MISCELLANEOUS

//=========================================================================================

   wire       clk;

   assign     clk = rclk;

   wire       reset;

   wire       dbb_reset_l;

    dffrl_async rstff(.din (grst_l),

                        .q   (dbb_reset_l),

                        .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so(),

                        .rst_l (arst_l));

   assign reset = ~dbb_reset_l ;

bw_u1_buf_30x UZsize_stb_cam_hit_bf1  (.a(stb_cam_hit),   .z(stb_cam_hit_bf1));  //to dctl, stb_rwctl

bw_u1_buf_30x UZsize_stb_cam_hit_bf   (.a(stb_cam_hit),   .z(stb_cam_hit_bf ));  //to qctl1

wire                ld_inst_vld_m;

wire                st_inst_vld_m;

dff_s #(2) inst_vld_stgm (

   .din ({ld_inst_vld_e, st_inst_vld_e}),

   .q   ({ld_inst_vld_m, st_inst_vld_m}),

   .clk    (clk),

   .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

);

dff_s #(2) inst_vld_stgg (

   .din ({ld_inst_vld_m, st_inst_vld_m}),

   .q   ({ld_inst_vld_unflushed, st_inst_vld_unflushed}),

   .clk    (clk),

   .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

);

wire    tlu_priv_trap_g ;

dff_s #(1) tprivtrp_g (

   .din (tlu_lsu_priv_trap_m),

   .q   (tlu_priv_trap_g),

   .clk    (clk),

   .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

);

//=========================================================================================

//  Thread Staging

//=========================================================================================

wire [1:0] thrid_m, thrid_g ;

dff_s #(2)  tid_stgm (

        .din    (ifu_tlu_thrid_e[1:0]),

        .q      (thrid_m[1:0]),

        .clk    (clk),

        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

        );

wire    thread0_m, thread1_m, thread2_m, thread3_m;

assign  thread0_m = ~thrid_m[1] & ~thrid_m[0] ;

assign  thread1_m = ~thrid_m[1] &  thrid_m[0] ;

assign  thread2_m =  thrid_m[1] & ~thrid_m[0] ;

assign  thread3_m =  thrid_m[1] &  thrid_m[0] ;

wire thread0_g, thread1_g, thread2_g, thread3_g ;

dff_s #(4)  tid_stgg (

        .din    ({thread0_m, thread1_m, thread2_m, thread3_m}),

        .q      ({thread0_g, thread1_g, thread2_g, thread3_g}),

        .clk    (clk),

        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

        );

//=========================================================================================

//  INST_VLD_W GENERATION

//=========================================================================================

assign  thrid_g[0] = thread1_g | thread3_g ;

assign  thrid_g[1] = thread2_g | thread3_g ;

wire    flush_w_inst_vld_m ;

wire    lsu_inst_vld_w ;

wire    lsu_flush_pipe_w;

assign  flush_w_inst_vld_m =

        ifu_tlu_inst_vld_m &

        ~(lsu_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w

dff_s  stgw_ivld (

        .din    (flush_w_inst_vld_m),

        .q      (lsu_inst_vld_w),

        .clk    (clk),

        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

        );

//========================================================================

//      Miscellaneous

//========================================================================

// Moved to excpctl from stb_rwctl as excpctl is closer to stb-cam.

mux4ds  #(8) stbvld_mx (

  .in0  (~stb_state_vld0[7:0]),

  .in1  (~stb_state_vld1[7:0]),

  .in2  (~stb_state_vld2[7:0]),

  .in3  (~stb_state_vld3[7:0]),

  .sel0 (thread0_g),

  .sel1 (thread1_g),

  .sel2 (thread2_g),

  .sel3 (thread3_g),

  .dout (stb_cam_sqsh_msk[7:0])

);

//========================================================================

//  Exception Handling Begin

//========================================================================

//va watch point

   wire va_match_g;

   wire va_wtchpt_msk_match_g;

wire    va_wtchpt_en_m ;

assign  va_wtchpt_en_m =

va_wtchpt_cmp_en_m &

(((~asi_internal_m & recognized_asi_m) & lsu_alt_space_m) | ~lsu_alt_space_m) // Bug5226

& (ld_inst_vld_m | st_inst_vld_m) & //bug 3681

 ~(hpv_priv_m & hpstate_en_m)  // ECO 4178

& ~cam_real_m ;                // ECO 5470 (TO_2_0)

//bug6480   

   wire lsu_va_match_m;

   wire pstate_am_m ;

assign lsu_va_match_m = ((lsu_va_match_b47_b32_m & lsu_va_match_b31_b3_m) & ~pstate_am_m) |

                          (lsu_va_match_b31_b3_m & pstate_am_m);

dff_s #(3)  stgwtch_g (

        .din    ({va_wtchpt_en_m,

                  lsu_va_match_m,

                  va_wtchpt_msk_match_m}),

        .q      ({va_wtchpt_en_g,

                  va_match_g,

                  va_wtchpt_msk_match_g}),

        .clk    (clk),

        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

        );

// These signals will eventually generate exceptions.

   wire va_wtchpt_match;

assign  va_wtchpt_match =

        va_match_g &  va_wtchpt_msk_match_g & lsu_inst_vld_w & va_wtchpt_en_g;

assign  lsu_tlu_wtchpt_trp_g = va_wtchpt_match ;

// tlb related exceptions/errors

wire  tlb_daccess_excptn_e, tlb_daccess_excptn_m ;

wire  tlb_daccess_excptn_e_d1;

wire    tlb_illgl_pgsz_m ;

assign  tlb_daccess_excptn_e  =

  ((rd_only_ltlb_asi_e &  st_inst_vld_e)  |

   (wr_only_ltlb_asi_e &  ld_inst_vld_e)) & ifu_lsu_alt_space_e   ;

dff_s  #(1) tlbex_stgm (

        .din    ({tlb_daccess_excptn_e}),

        .q      ({tlb_daccess_excptn_e_d1}),

        .clk    (clk),

        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

        );

assign tlb_daccess_excptn_m = tlb_daccess_excptn_e_d1 | tlb_illgl_pgsz_m;

wire pstate_priv_m;

//wire pstate_priv;

mux4ds  #(1) pstate_priv_m_mux (

        .in0    (tlu_lsu_pstate_priv[0]),

        .in1    (tlu_lsu_pstate_priv[1]),

        .in2    (tlu_lsu_pstate_priv[2]),

        .in3    (tlu_lsu_pstate_priv[3]),

        .sel0   (thread0_m),

        .sel1   (thread1_m),

        .sel2   (thread2_m),

        .sel3   (thread3_m),

        .dout   (pstate_priv_m)

);

//dff #(1)  priv_stgg (

//        .din    (pstate_priv_m),

//        .q      (pstate_priv),

//        .clk    (clk),

//        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

//        );

// privilege violation - priv page accessed in user mode

//timing 

//assign  priv_pg_usr_mode =  // data access exception; TT=h30

//  (ld_inst_vld_unflushed | st_inst_vld_unflushed) & ~(pstate_priv | hpv_priv) & tlb_rd_tte_data_pbit ;

//SC2   wire hpv_priv_m;

   assign priv_pg_usr_mode_m = (ld_inst_vld_m | st_inst_vld_m) & ~(pstate_priv_m | hpv_priv_m);

dff_s #(1) priv_pg_usr_mode_stgg  (

        .din    (priv_pg_usr_mode_m),

        .q      (priv_pg_usr_mode_g),

        .clk    (clk),

        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

        );

   assign priv_pg_usr_mode = priv_pg_usr_mode_g & tlb_rd_tte_data_pbit ;

// protection violation - store to a page that does not have write permission

//timing

//assign  nonwr_pg_st_access =  // data access protection; TT=h33

//  st_inst_vld_unflushed   & 

//  ~tlb_rd_tte_data_wbit & ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;

//   //lsu_dtlb_bypass_g) ; // W=1 in bypass mode - In bypass mode this trap will never happen !!!

   assign nonwr_pg_st_access = ~tlb_rd_tte_data_wbit & st_inst_vld_unflushed & tlb_tte_vld_g;

wire  daccess_prot ;

assign  daccess_prot = nonwr_pg_st_access  ;

    //((~lsu_dtlb_bypass_g & tlb_cam_hit_g) | (tlb_byp_asi_g & lsu_alt_space_g)) ;

// access to a page marked with the nfo with an asi other than nfo asi.

//timing

//assign  nfo_pg_nonnfo_asi  =  // data access exception; TT=h30

//  (ld_inst_vld_unflushed | st_inst_vld_unflushed) &   // any access

//  ((~nofault_asi_g & lsu_alt_space_g) | ~lsu_alt_space_g) // in alternate space or not

//  & tlb_rd_tte_data_nfobit ;

assign nfo_pg_nonnfo_asi_m = (ld_inst_vld_m | st_inst_vld_m) &

                             ((~nofault_asi_m & lsu_alt_space_m) | ~lsu_alt_space_m) ;

dff_s #(1) nfo_pg_nonnfo_asi_stgg   (

        .din    (nfo_pg_nonnfo_asi_m),

        .q      (nfo_pg_nonnfo_asi_g),

        .clk    (clk),

        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

        );

assign    nfo_pg_nonnfo_asi = nfo_pg_nonnfo_asi_g & tlb_rd_tte_data_nfobit ;

// as_if_usr asi accesses priv page.

//timing

//assign  as_if_usr_priv_pg  =  // data access exception; TT=h30

//  (ld_inst_vld_unflushed | st_inst_vld_unflushed) & as_if_user_asi_g & lsu_alt_space_g & 

//      tlb_rd_tte_data_pbit ;

   wire   as_if_usr_priv_pg_m, as_if_usr_priv_pg_g, as_if_usr_priv_pg;

   assign as_if_usr_priv_pg_m = (ld_inst_vld_m | st_inst_vld_m) & as_if_user_asi_m & lsu_alt_space_m;

dff_s #(1) as_if_usr_priv_pg_stgg   (

        .din    (as_if_usr_priv_pg_m),

        .q      (as_if_usr_priv_pg_g),

        .clk    (clk),

        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

        );

   assign  as_if_usr_priv_pg =  as_if_usr_priv_pg_g & tlb_rd_tte_data_pbit ;

// non-cacheable address - iospace PA[39] = 1 

// atomic access to non-cacheable space.

   wire    atm_access_w_nc, atomic_g;

dff_s #(1) atm_stgg (

        .din    (atomic_m),

        .q      (atomic_g),

        .clk    (clk),

        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

        );

assign  atm_access_w_nc = atomic_g & tlb_pgnum_b39 ; // io space 

// atomic inst with unsupported asi.

//timing

//assign  atm_access_unsup_asi = atomic_g & ~atomic_asi_g & lsu_alt_space_g ;

   wire atm_access_unsup_asi_m, atm_access_unsup_asi;

assign  atm_access_unsup_asi_m = atomic_m & ~atomic_asi_m & lsu_alt_space_m;

dff_s #(1) atm_access_unsup_asi_stgg   (

        .din    (atm_access_unsup_asi_m),

        .q      (atm_access_unsup_asi),

        .clk    (clk),

        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

        );

//timing

//assign  tlb_tte_vld_g = ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;

wire    dmmu_va_oor_m ;

assign  tlb_tte_vld_m = ~dtlb_bypass_m & tlb_cam_hit &

                        ~((unimp_asi_m | asi_internal_m | ~recognized_asi_m) &

                                lsu_alt_space_m) & // Bug 3541,5186

                        ~dmmu_va_oor_m ; // Bug 5070

dff_s #(1) tlb_tte_vld_stgg   (

        .din    (tlb_tte_vld_m),

        .q      (tlb_tte_vld_g),

        .clk    (clk),

        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

        );

wire  pg_with_ebit_m, pg_with_ebit_g, pg_with_ebit  ;

//timing   

//assign        pg_with_ebit = 

//      (tlb_rd_tte_data_ebit & tlb_tte_vld_g)  | // tte

//        (lsu_dtlb_bypass_g & ~(phy_use_ec_asi_g & lsu_alt_space_g)) | // regular bypass 

//        (tlb_byp_asi_g & ~phy_use_ec_asi_g & lsu_alt_space_g) ; // phy_byp

assign  pg_with_ebit_m =

        (dtlb_bypass_m & ~(phy_use_ec_asi_m & lsu_alt_space_m) &

        (lsu_ldst_va_b39_m & ~pstate_am_m)) |

        // regular bypass // Bug 4296,5050 related.

        (dtlb_bypass_m & (phy_byp_ec_asi_m & lsu_alt_space_m)) ; // phy_byp

dff_s #(1) pg_with_ebit_stgg   (

        .din    (pg_with_ebit_m),

        .q      (pg_with_ebit_g),

        .clk    (clk),

        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

        );

assign  pg_with_ebit = (tlb_rd_tte_data_ebit & tlb_tte_vld_g)  | // tte  

                              pg_with_ebit_g;

//timing

//assign  spec_access_epage = 

//  ((ld_inst_vld_unflushed & nofault_asi_g & lsu_alt_space_g) |  // spec load

//  flsh_inst_g) & // flush inst

//  pg_with_ebit ; // page with side effects

////  tlb_rd_tte_data_ebit ; // page with side effects

assign  spec_access_epage_m =

// Bug 5166

((ld_inst_vld_m & ~atomic_m) & nofault_asi_m & lsu_alt_space_m);   // spec load

dff_s #(1) spec_access_epage_stgg   (

        .din    (spec_access_epage_m),

        .q      (spec_access_epage_g),

        .clk    (clk),

        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

        );

// remove flsh_inst_g ??   

//assign spec_access_epage = (spec_access_epage_g  | flsh_inst_g) & pg_with_ebit;

assign spec_access_epage = (spec_access_epage_g) & pg_with_ebit;

   wire quad_asi_non_ldstda_m;

   // covers regular quad asi AND binit. 

   assign quad_asi_non_ldstda_m =

        quad_asi_m & lsu_alt_space_m &

                ((~ldst_dbl_m & ld_inst_vld_m) | // only lddbl should use

                (fp_ldst_m & (ld_inst_vld_m | st_inst_vld_m))) ; // float should not use

   wire true_quad_non_ldda_m ;

   // catches case where st or non-ldd uses asi

   assign true_quad_non_ldda_m =

        (quad_asi_m & ~binit_quad_asi_m) & lsu_alt_space_m &

  ((~ldst_dbl_m & ld_inst_vld_m) | st_inst_vld_m) ;

wire  blk_asi_non_ldstdfa_m ;

assign  blk_asi_non_ldstdfa_m = blk_asi_m & lsu_alt_space_m &

     ~(ldst_dbl_m & fp_ldst_m) & (ld_inst_vld_m | st_inst_vld_m) ;

// trap on illegal asi

wire  illegal_asi_trap_m, illegal_asi_trap_g, illegal_asi_trap_m_d1 ;

assign  illegal_asi_trap_m =

((ld_inst_vld_m | st_inst_vld_m) & lsu_alt_space_m & ~recognized_asi_m) |

((ld_inst_vld_m | st_inst_vld_m) & asi_internal_m & fp_ldst_m & lsu_alt_space_m) | // Bug 4382

blk_asi_non_ldstdfa_m |

quad_asi_non_ldstda_m |

true_quad_non_ldda_m  ;

dff_s #(1) illegal_asi_trap_stgg   (

        .din    (illegal_asi_trap_m),

        .q      (illegal_asi_trap_m_d1),

        .clk    (clk),

        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()

        );

   //need lsu_inst_vld_w ??

//   assign illegal_asi_trap_g = illegal_asi_trap_m_d1 & lsu_inst_vld_w;