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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [lsu_qdp1.v] - Blame information for rev 113

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1 95 fafa1971 
// ========== Copyright Header Begin ==========================================
2 
//
3 
// OpenSPARC T1 Processor File: lsu_qdp1.v
4 
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
5 
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6 
//
7 
// The above named program is free software; you can redistribute it and/or
8 
// modify it under the terms of the GNU General Public
9 
// License version 2 as published by the Free Software Foundation.
10 
//
11 
// The above named program is distributed in the hope that it will be
12 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 
// General Public License for more details.
15 
//
16 
// You should have received a copy of the GNU General Public
17 
// License along with this work; if not, write to the Free Software
18 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19 
//
20 
// ========== Copyright Header End ============================================
21 113 albert.wat 
`ifdef SIMPLY_RISC_TWEAKS
22 
`define SIMPLY_RISC_SCANIN .si(0)
23 
`else
24 
`define SIMPLY_RISC_SCANIN .si()
25 
`endif
26 95 fafa1971 
///////////////////////////////////////////////////////////////////////
27 
/*
28 
//  Description:  LSU PCX Datapath - QDP1
29 
*/
30 
////////////////////////////////////////////////////////////////////////
31 
// header file includes
32 
////////////////////////////////////////////////////////////////////////
33 113 albert.wat 
`include  "sys.h" // system level definition file which contains the
34 95 fafa1971 
          // time scale definition
35 113 albert.wat 
`include  "iop.h"
36 
`include  "lsu.h"
37 95 fafa1971 
 
38 
////////////////////////////////////////////////////////////////////////
39 
// Local header file includes / local defines
40 
////////////////////////////////////////////////////////////////////////
41 
 
42 
//FPGA_SYN enables all FPGA related modifications
43 113 albert.wat 
`ifdef FPGA_SYN
44 
`define FPGA_SYN_CLK_EN
45 
`define FPGA_SYN_CLK_DFF
46 
`endif
47 95 fafa1971 
 
48 
module lsu_qdp1 ( /*AUTOARG*/
49 
   // Outputs
50 
   so, lsu_va_match_b47_b32_m, lsu_va_match_b31_b3_m, lsu_va_wtchpt_addr, spc_pcx_data_pa,
51 
   dtag_wdata_m, lmq0_byp_misc_sz, lmq1_byp_misc_sz,
52 
   lmq2_byp_misc_sz, lmq3_byp_misc_sz, lsu_byp_misc_sz_e,
53 
   lsu_l2fill_sign_extend_m, lsu_l2fill_bendian_m, lmq0_l2fill_fpld,
54 
   lmq1_l2fill_fpld, lmq2_l2fill_fpld, lmq3_l2fill_fpld, lmq_ld_rd1,
55 
   lmq0_ncache_ld, lmq1_ncache_ld, lmq2_ncache_ld, lmq3_ncache_ld,
56 
   lmq0_ld_rq_type, lmq1_ld_rq_type, lmq2_ld_rq_type,
57 
   lmq3_ld_rq_type, lmq0_ldd_vld, lmq1_ldd_vld, lmq2_ldd_vld,
58 
   lmq3_ldd_vld, ld_sec_hit_thrd0, ld_sec_hit_thrd1,
59 
   ld_sec_hit_thrd2, ld_sec_hit_thrd3, lmq0_pcx_pkt_addr,
60 
   lmq1_pcx_pkt_addr, lmq2_pcx_pkt_addr, lmq3_pcx_pkt_addr,
61 
   lsu_mmu_rs3_data_g, lsu_tlu_rs3_data_g, lsu_diagnstc_wr_data_b0,
62 
   lsu_diagnstc_wr_data_e, lsu_ifu_stxa_data,
63 
   lsu_ifu_ld_icache_index, lsu_ifu_ld_pcxpkt_tid, lsu_error_pa_m,
64 
   lsu_pref_pcx_req, st_rs3_data_g, lsu_ldst_va_way_g,
65 
   dcache_alt_data_w0_m,
66 
   // Inputs
67 
   rclk, si, se, lsu_dcache_iob_rd_w, lsu_ramtest_rd_w,
68 
   lsu_pcx_rq_sz_b3, lsu_diagnstc_data_sel, pcx_pkt_src_sel,
69 
   lsu_stb_pcx_rvld_d1, imiss_pcx_mx_sel, fwd_int_fp_pcx_mx_sel,
70 
   spu_lsu_ldst_pckt, tlu_lsu_pcxpkt, const_cpuid, ifu_pcx_pkt,
71 
   lmq_byp_data_en_w2, lmq_byp_data_sel0, lmq_byp_data_sel1,
72 
   lmq_byp_data_sel2, lmq_byp_data_sel3, lmq_byp_ldxa_sel0,
73 
   lmq_byp_ldxa_sel1, lmq_byp_ldxa_sel2, lmq_byp_ldxa_sel3,
74 
   lmq_byp_data_fmx_sel, exu_lsu_rs3_data_e, ifu_lsu_ldxa_data_w2,
75 
   tlu_lsu_int_ldxa_data_w2, spu_lsu_ldxa_data_w2, stb_rdata_ramd,
76 
   stb_rdata_ramc, lmq_byp_misc_sel, dfq_byp_sel, ld_pcx_rq_sel,
77 
   ld_pcx_thrd, lmq_enable, ld_pcx_pkt_g, ffu_lsu_data,
78 
   lsu_tlb_st_sel_m, lsu_pcx_fwd_pkt, lsu_pcx_fwd_reply,
79 
   lsu_diagnstc_dtagv_prty_invrt_e, lsu_misc_rdata_w2,
80 
   lsu_stb_rd_tid, lsu_iobrdge_rply_data_sel, lsu_iobrdge_rd_data,
81 
   lsu_atomic_pkt2_bsel_g, lsu_pcx_ld_dtag_perror_w2,
82 
   lsu_dcache_rdata_w, lsu_va_wtchpt0_wr_en_l,
83 
   lsu_va_wtchpt1_wr_en_l, lsu_va_wtchpt2_wr_en_l,
84 
   lsu_va_wtchpt3_wr_en_l, thread0_m, thread1_m, thread2_m,
85 
   thread3_m, lsu_thread_g, lsu_ldst_va_m, tlb_pgnum, lsu_bld_pcx_rq,
86 
   lsu_bld_rq_addr, lmq0_pcx_pkt_way, lmq1_pcx_pkt_way,
87 
   lmq2_pcx_pkt_way, lmq3_pcx_pkt_way, lsu_dfq_ld_vld,
88 
   lsu_ifu_asi_data_en_l, lsu_ld0_spec_vld_kill_w2,
89 
   lsu_ld1_spec_vld_kill_w2, lsu_ld2_spec_vld_kill_w2,
90 
   lsu_ld3_spec_vld_kill_w2, lsu_fwd_rply_sz1_unc, rst_tri_en,
91 
   lsu_l2fill_data, l2fill_vld_m, ld_thrd_byp_sel_m, sehold
92 
   ) ;
93 
 
94 
input                     rclk ;
95 
input                     si;
96 
input                     se;
97 
input                     sehold;
98 
//input                   tmb_l;
99 
 
100 
output                    so;
101 
input                     lsu_dcache_iob_rd_w ;
102 
input                     lsu_ramtest_rd_w ;
103 
 
104 
input                    lsu_pcx_rq_sz_b3 ;
105 
 
106 
input  [3:0]               lsu_diagnstc_data_sel ;
107 
 
108 
input   [3:0]             pcx_pkt_src_sel ;       // sel 1/4 pkt src for pcx.
109 
input                     lsu_stb_pcx_rvld_d1 ;   // stb has been read-delayby1cycle
110 
input                     imiss_pcx_mx_sel ;      // select imiss over spu.
111 
input   [2:0]             fwd_int_fp_pcx_mx_sel ; // select fwd/intrpt/fpop
112 
 
113 113 albert.wat 
input   [`PCX_WIDTH-1:0]  spu_lsu_ldst_pckt ;     // stream ld/st pkt for pcx.
114 95 fafa1971 
input   [25:0]            tlu_lsu_pcxpkt ;        // truncated pcx interrupt pkt.
115 
input   [2:0]             const_cpuid ;           // cpu id
116 
input   [51:0]            ifu_pcx_pkt ;           // ifu imiss request.
117 
input   [3:0]             lmq_byp_data_en_w2 ;
118 
input   [3:0]             lmq_byp_data_sel0 ;     // ldxa/stb/cas bypass data sel.
119 
input   [3:0]             lmq_byp_data_sel1 ;     // ldxa/stb/cas bypass data sel.
120 
input   [3:0]             lmq_byp_data_sel2 ;     // ldxa/stb/cas bypass data sel.
121 
input   [3:0]             lmq_byp_data_sel3 ;     // ldxa/stb/cas bypass data sel.
122 
input   [2:0]             lmq_byp_ldxa_sel0 ;     // ldxa data sel - thread0
123 
input   [2:0]             lmq_byp_ldxa_sel1 ;     // ldxa data sel - thread1
124 
input   [2:0]             lmq_byp_ldxa_sel2 ;     // ldxa data sel - thread2
125 
input   [2:0]             lmq_byp_ldxa_sel3 ;     // ldxa data sel - thread3
126 
input   [3:0]              lmq_byp_data_fmx_sel ;  // final sel for lmq data.
127 
input   [63:0]            exu_lsu_rs3_data_e ;    // rs3_data for cas pkt 2.
128 
input   [63:0]            ifu_lsu_ldxa_data_w2 ;  // ldxa data from ifu.
129 
//input   [63:0]            tlu_lsu_ldxa_data_w2 ;  // ldxa data from tlu (mmu)
130 
input   [63:0]            tlu_lsu_int_ldxa_data_w2 ;  // ldxa data from tlu (intrpt/scpd)
131 
input   [63:0]            spu_lsu_ldxa_data_w2 ;  // ldxa data from spu
132 
input   [75:0]            stb_rdata_ramd ;        // stb0 data ram output.
133 
input   [44:9]            stb_rdata_ramc ;        // stb0 tag ram output.
134 
input   [3:0]             lmq_byp_misc_sel ;      // select g-stage lmq source
135 
input   [3:0]             dfq_byp_sel ;
136 
input   [3:0]             ld_pcx_rq_sel ;
137 
input   [1:0]             ld_pcx_thrd ;
138 
 
139 
input   [3:0]             lmq_enable ;             // 4 enables for lmq.
140 113 albert.wat 
input   [`LMQ_WIDTH-1:40]  ld_pcx_pkt_g ;           // ld miss pkt for thread.
141 95 fafa1971 
input   [80:0]            ffu_lsu_data ;
142 
input   [3:0]             lsu_tlb_st_sel_m ;
143 
//input   [3:0]             lsu_tlb_st_sel_g ;
144 
//input                     lsu_tlb_st_vld_g ;
145 
input   [107:0]           lsu_pcx_fwd_pkt ;         // local fwd reply/req
146 
input                     lsu_pcx_fwd_reply ;       // fwd reply on pcx pkt
147 
input                     lsu_diagnstc_dtagv_prty_invrt_e ;
148 
//input                     lsu_diagnstc_wr_src_sel_e ;// dcache/dtag/v write - diag
149 
//input   [47:0]            lsu_local_ldxa_data_w2 ;   // local ldxa data
150 
input   [63:0]            lsu_misc_rdata_w2 ;   // local ldxa data
151 
input   [1:0]             lsu_stb_rd_tid ;           // thread for which stb rd occurs
152 
input   [2:0]             lsu_iobrdge_rply_data_sel ;
153 
input   [43:0]            lsu_iobrdge_rd_data ;
154 
input   [2:0]             lsu_atomic_pkt2_bsel_g ;
155 
input                     lsu_pcx_ld_dtag_perror_w2 ;
156 
input   [63:0]             lsu_dcache_rdata_w ;
157 
//input   [47:0]            tlu_lsu_iobrdge_pc_data ;  // NOTE: unused: remove this in sync w/ tlu
158 
 
159 
input         lsu_va_wtchpt0_wr_en_l;
160 
input         lsu_va_wtchpt1_wr_en_l;
161 
input         lsu_va_wtchpt2_wr_en_l;
162 
input         lsu_va_wtchpt3_wr_en_l;
163 
input         thread0_m;
164 
input         thread1_m;
165 
input         thread2_m;
166 
input         thread3_m;
167 
 
168 
   input [3:0] lsu_thread_g;
169 
 
170 
 
171 
//input         lsu_pa_wtchpt_wr_en_l;
172 
input [47:0]  lsu_ldst_va_m;
173 
input [39:13] tlb_pgnum;
174 
input         lsu_bld_pcx_rq ;        // cycle after request
175 
input [1:0]   lsu_bld_rq_addr ;       // cycle after request
176 
 
177 
//input  [1:0]           lsu_lmq_pkt_way_g;
178 
input  [1:0]           lmq0_pcx_pkt_way;
179 
input  [1:0]           lmq1_pcx_pkt_way;
180 
input  [1:0]           lmq2_pcx_pkt_way;
181 
input  [1:0]           lmq3_pcx_pkt_way;
182 
 
183 
input           lsu_dfq_ld_vld ;
184 
input           lsu_ifu_asi_data_en_l ;
185 
 
186 
input           lsu_ld0_spec_vld_kill_w2 ;
187 
input           lsu_ld1_spec_vld_kill_w2 ;
188 
input           lsu_ld2_spec_vld_kill_w2 ;
189 
input           lsu_ld3_spec_vld_kill_w2 ;
190 
 
191 
input           lsu_fwd_rply_sz1_unc ;
192 
 
193 
input           rst_tri_en ;
194 
 
195 
output        lsu_va_match_b47_b32_m;
196 
output        lsu_va_match_b31_b3_m;
197 
 
198 
//output        lsu_pa_match_b39_13_g;
199 
//output        lsu_pa_match_b12_3_m;
200 
output [47:3] lsu_va_wtchpt_addr;
201 
//output [39:3] lsu_pa_wtchpt_addr;
202 
 
203 
//output  [63:0]            ld_stb_bypass_data ;  // st to load bypass data.
204 
 
205 113 albert.wat 
output  [`PCX_WIDTH-1:0]  spc_pcx_data_pa ;
206 95 fafa1971 
output  [29:0]            dtag_wdata_m ;            // tag to write to dtag.
207 
//output  [3:0]             lsu_byp_misc_addr_m ;     // lower 3bits of addr for ldxa/raw etc
208 
//output  [1:0]             lsu_byp_misc_sz_m ;       // size for ldxa/raw etc
209 
output  [1:0]             lmq0_byp_misc_sz ;
210 
output  [1:0]             lmq1_byp_misc_sz ;
211 
output  [1:0]             lmq2_byp_misc_sz ;
212 
output  [1:0]             lmq3_byp_misc_sz ;
213 
 
214 
output  [1:0]             lsu_byp_misc_sz_e ;       // size for ldxa/raw etc
215 
output                    lsu_l2fill_sign_extend_m ;// requires sign-extend else zero extend
216 
output                    lsu_l2fill_bendian_m ;    // big endian fill/bypass.
217 
//output                    lsu_l2fill_fpld_e ;       // fp load
218 
output                    lmq0_l2fill_fpld ;       // fp load
219 
output                    lmq1_l2fill_fpld ;       // fp load
220 
output                    lmq2_l2fill_fpld ;       // fp load
221 
output                    lmq3_l2fill_fpld ;       // fp load
222 
 
223 
output  [4:0]             lmq_ld_rd1 ;              // rd for all loads
224 
//output                    lsu_ncache_ld_e ;         // non-cacheable ld from dfq
225 
output                    lmq0_ncache_ld ;         // non-cacheable ld from dfq
226 
output                    lmq1_ncache_ld ;         // non-cacheable ld from dfq
227 
output                    lmq2_ncache_ld ;         // non-cacheable ld from dfq
228 
output                    lmq3_ncache_ld ;         // non-cacheable ld from dfq
229 
//output  [2:0]             lsu_ld_rq_type_e ;        // for identifying atomic ld.
230 
 
231 
output  [2:0]             lmq0_ld_rq_type ;        // for identifying atomic ld.
232 
output  [2:0]             lmq1_ld_rq_type ;        // for identifying atomic ld.
233 
output  [2:0]             lmq2_ld_rq_type ;        // for identifying atomic ld.
234 
output  [2:0]             lmq3_ld_rq_type ;        // for identifying atomic ld.
235 
 
236 
output                    lmq0_ldd_vld ;             // ld double
237 
output                    lmq1_ldd_vld ;             // ld double
238 
output                    lmq2_ldd_vld ;             // ld double
239 
output                    lmq3_ldd_vld ;             // ld double
240 
 
241 
output                    ld_sec_hit_thrd0 ;        // ld has sec. hit against th0
242 
output                    ld_sec_hit_thrd1 ;        // ld has sec. hit against th1
243 
output                    ld_sec_hit_thrd2 ;        // ld has sec. hit against th2
244 
output                    ld_sec_hit_thrd3 ;        // ld has sec. hit against th3
245 
//output  [1:0]             lmq_pcx_pkt_sz ;
246 
//output  [39:0]            lmq_pcx_pkt_addr ;
247 
output  [10:0]            lmq0_pcx_pkt_addr;
248 
output  [10:0]            lmq1_pcx_pkt_addr;
249 
output  [10:0]            lmq2_pcx_pkt_addr;
250 
output  [10:0]            lmq3_pcx_pkt_addr;
251 
 
252 
//output  [63:0]            lsu_tlu_st_rs3_data_g ;
253 
output  [63:0]            lsu_mmu_rs3_data_g ;
254 
output  [63:0]            lsu_tlu_rs3_data_g ;
255 
 
256 
output                    lsu_diagnstc_wr_data_b0 ; // diagnostic wr data - bit 0
257 
output  [63:0]            lsu_diagnstc_wr_data_e ;
258 
 
259 
output  [47:0]            lsu_ifu_stxa_data ;       // stxa related data
260 
 
261 
output  [11:5]            lsu_ifu_ld_icache_index ;
262 
output  [1:0]             lsu_ifu_ld_pcxpkt_tid ;
263 
 
264 
//output  [1:0]             lmq_ld_way ;              // cache set way for ld fill
265 
 
266 
output  [28:0]            lsu_error_pa_m ;          // error phy addr
267 
//output  [13:0]            lsu_spu_rsrv_data_m ;     // rs3 data for reserved fields.
268 
output                    lsu_pref_pcx_req ;        // pref sent to pcx
269 
 
270 
   output [63:0]          st_rs3_data_g;
271 
 
272 
output  [1:0]             lsu_ldst_va_way_g ;          // 12:11 for direct map
273 
//====================================================================
274 
//dc_fill CP
275 
 
276 
   input [63:0]           lsu_l2fill_data; //from qdp2
277 
   input                  l2fill_vld_m;    //from dctl
278 
   input   [3:0]          ld_thrd_byp_sel_m;//from dctl
279 
 
280 
   output [63:0]          dcache_alt_data_w0_m;  //to d$
281 
//   output [7:0]           lsu_l2fill_or_byp_msb_m;   //to dctl
282 
//====================================================================
283 
 
284 
 
285 113 albert.wat 
wire  [`STB_PCX_WIDTH-1:0]  store_pcx_pkt ;
286 
wire  [`PCX_WIDTH-1:0]  pcx_pkt_data ;
287 
wire  [`STB_PCX_WIDTH-1:0]  stb_pcx_pkt ;
288 
wire  [`PCX_WIDTH-1:0]  imiss_strm_pcx_pkt ;
289 
wire  [`PCX_WIDTH-1:0]  intrpt_full_pcxpkt ;
290 
wire  [`PCX_WIDTH-1:0]  ifu_full_pcx_pkt_e ;
291 95 fafa1971 
wire  [51:0]      ifu_pcx_pkt_e ;
292 
wire  [63:0]      cas_pkt2_data ;
293 
wire  [63:0]      lmq0_bypass_data_in,lmq1_bypass_data_in ;
294 
wire  [63:0]      lmq2_bypass_data_in,lmq3_bypass_data_in ;
295 
wire  [63:0]      lmq0_bypass_data, lmq1_bypass_data ;
296 
wire  [63:0]      lmq2_bypass_data, lmq3_bypass_data ;
297 
wire  [39:0]      lmq_ld_addr ;
298 113 albert.wat 
wire  [`LMQ_WIDTH:0]    load_pcx_pkt ;
299 
wire  [`LMQ_WIDTH-1:0]  lmq0_pcx_pkt, lmq1_pcx_pkt ;
300 
wire  [`LMQ_WIDTH-1:0]  lmq2_pcx_pkt, lmq3_pcx_pkt ;
301 
wire  [`PCX_WIDTH-1:0]  fpop_full_pcxpkt ;
302 95 fafa1971 
wire  [63:0]      tlb_st_data ;
303 
//wire    [63:0]      formatted_tte_tag ;
304 
//wire    [63:0]      formatted_tte_data ;
305 
wire  [63:0]      lmq0_bypass_ldxa_data ;
306 
wire  [63:0]      lmq1_bypass_ldxa_data ;
307 
wire  [63:0]      lmq2_bypass_ldxa_data ;
308 
wire  [63:0]      lmq3_bypass_ldxa_data ;
309 113 albert.wat 
wire  [`PCX_WIDTH-1:0]  fwd_full_pcxpkt ;
310 95 fafa1971 
wire  [47:3]            lsu_tlu_st_rs3_data_g ;
311 
 
312 
 
313 
//===================================================
314 
//  clock buffer
315 
//===================================================
316 
//wire   lsu_qdp1_clk ;
317 
wire   clk;
318 
assign  clk = rclk;
319 
 
320 
wire         thread0_g;
321 
wire         thread1_g;
322 
wire         thread2_g;
323 
wire         thread3_g;
324 
 
325 
   assign    thread0_g = lsu_thread_g[0];
326 
   assign    thread1_g = lsu_thread_g[1];
327 
   assign    thread2_g = lsu_thread_g[2];
328 
   assign    thread3_g = lsu_thread_g[3];
329 
 
330 
//=================================================================================================
331 
//    LMQ DP
332 
//=================================================================================================
333 
 
334 
wire  [12:0]  ldst_va_g;
335 
 
336 113 albert.wat 
dff_s  #(13) ff_ldst_va_g (
337 95 fafa1971 
        .din    (lsu_ldst_va_m[12:0]),
338 
        .q      (ldst_va_g[12:0]),
339 
        .clk    (clk),
340 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
341 95 fafa1971 
        );
342 
 
343 
assign  lsu_ldst_va_way_g[1:0] =  ldst_va_g[12:11];
344 
 
345 113 albert.wat 
wire  [`LMQ_VLD:0]  ld_pcx_pkt_g_tmp;
346 95 fafa1971 
 
347 113 albert.wat 
assign ld_pcx_pkt_g_tmp[`LMQ_VLD:0] =  {ld_pcx_pkt_g[`LMQ_WIDTH-1:44],
348 95 fafa1971 
                                        2'b00,      // done after the flop
349 
                                        //lsu_lmq_pkt_way_g[1:0],
350 
                                        ld_pcx_pkt_g[41:40],
351 
                                        tlb_pgnum[39:13],ldst_va_g[12:0]};
352 
 
353 
// Unfortunately ld_pcx_pkt_g is now 65 bits wide. Grape-mapper needs to give feedback.
354 
// THREAD 0.
355 
/*
356 113 albert.wat 
dffe_s  #(`LMQ_WIDTH) lmq0 (
357 95 fafa1971 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
358 
        .q      (lmq0_pcx_pkt[`LMQ_VLD:0]),
359 
        .en     (lmq_enable[0]), .clk (clk),
360 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
361 95 fafa1971 
        );
362 
*/
363 
wire lmq0_clk;
364 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
365 
`else
366 
clken_buf lmq0_clkbuf (
367 
                .rclk   (clk),
368 
                .enb_l  (~lmq_enable[0]),
369 
                .tmb_l  (~se),
370 
                .clk    (lmq0_clk)
371 
                ) ;
372 
`endif
373 
wire  [`LMQ_VLD:0]  lmq0_pcx_pkt_tmp ;
374 95 fafa1971 
 
375 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
376 
dffe_s  #(`LMQ_WIDTH) lmq0 (
377 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
378 
        .q      (lmq0_pcx_pkt_tmp[`LMQ_VLD:0]),
379 95 fafa1971 
        .en (~(~lmq_enable[0])), .clk(clk),
380 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
381 95 fafa1971 
        );
382 113 albert.wat 
`else
383 
dff_s  #(`LMQ_WIDTH) lmq0 (
384 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
385 
        .q      (lmq0_pcx_pkt_tmp[`LMQ_VLD:0]),
386 
        .clk    (lmq0_clk),
387 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
388 
        );
389 
`endif
390 95 fafa1971 
 
391 
//bug2705 - speculative pick in w-cycle
392 
wire    lmq0_pcx_pkt_vld ;
393 113 albert.wat 
assign  lmq0_pcx_pkt_vld  =  lmq0_pcx_pkt_tmp[`LMQ_VLD] & ~lsu_ld0_spec_vld_kill_w2 ;
394 95 fafa1971 
 
395 113 albert.wat 
assign  lmq0_pcx_pkt[`LMQ_VLD:0]  = {lmq0_pcx_pkt_vld,
396 
                                     lmq0_pcx_pkt_tmp[`LMQ_VLD-1:44],
397 95 fafa1971 
                                     lmq0_pcx_pkt_way[1:0],
398 
                                     lmq0_pcx_pkt_tmp[41:0]};
399 
 
400 
// Needs to be multi-threaded.
401 
//assign lmq_pcx_pkt_sz[1:0] = lmq0_pcx_pkt[`LMQ_SZ_HI:`LMQ_SZ_LO]  ;
402 
 
403 
assign  ld_sec_hit_thrd0 =
404 113 albert.wat 
(ld_pcx_pkt_g_tmp[`LMQ_AD_HI:`LMQ_AD_LO+4] == lmq0_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO+4]) ;
405 95 fafa1971 
 
406 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
407 
  assign load_pcx_pkt[`LMQ_WIDTH-1:0] = lmq0_pcx_pkt[`LMQ_WIDTH-1:0];
408 
`else
409 95 fafa1971 
// THREAD 1.
410 
/*
411 113 albert.wat 
dffe_s  #(`LMQ_WIDTH) lmq1 (
412 95 fafa1971 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
413 
        .q      (lmq1_pcx_pkt[`LMQ_VLD:0]),
414 
        .en     (lmq_enable[1]), .clk (clk),
415 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
416 95 fafa1971 
        );
417 
*/
418 
wire lmq1_clk;
419 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
420 
`else
421 
clken_buf lmq1_clkbuf (
422 
                .rclk   (clk),
423 
                .enb_l  (~lmq_enable[1]),
424 
                .tmb_l  (~se),
425 
                .clk    (lmq1_clk)
426 
                ) ;
427 
`endif
428 95 fafa1971 
 
429 113 albert.wat 
wire  [`LMQ_VLD:0]  lmq1_pcx_pkt_tmp;
430 95 fafa1971 
 
431 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
432 
dffe_s  #(`LMQ_WIDTH) lmq1 (
433 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
434 
        .q      (lmq1_pcx_pkt_tmp[`LMQ_VLD:0]),
435 95 fafa1971 
        .en (~(~lmq_enable[1])), .clk(clk),
436 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
437 95 fafa1971 
        );
438 113 albert.wat 
`else
439 
dff_s  #(`LMQ_WIDTH) lmq1 (
440 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
441 
        .q      (lmq1_pcx_pkt_tmp[`LMQ_VLD:0]),
442 
        .clk    (lmq1_clk),
443 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
444 
        );
445 
`endif
446 95 fafa1971 
 
447 
//bug2705 - speculative pick in w-cycle
448 
wire    lmq1_pcx_pkt_vld ;
449 113 albert.wat 
assign  lmq1_pcx_pkt_vld  =  lmq1_pcx_pkt_tmp[`LMQ_VLD] & ~lsu_ld1_spec_vld_kill_w2 ;
450 95 fafa1971 
 
451 113 albert.wat 
assign  lmq1_pcx_pkt[`LMQ_VLD:0]  =  {lmq1_pcx_pkt_vld,
452 
                                      lmq1_pcx_pkt_tmp[`LMQ_VLD-1:44],
453 95 fafa1971 
                                      lmq1_pcx_pkt_way[1:0],
454 
                                      lmq1_pcx_pkt_tmp[41:0]};
455 
 
456 
assign  ld_sec_hit_thrd1 =
457 113 albert.wat 
(ld_pcx_pkt_g_tmp[`LMQ_AD_HI:`LMQ_AD_LO+4] == lmq1_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO+4]) ;
458 95 fafa1971 
 
459 
// THREAD 2.
460 
/*
461 113 albert.wat 
dffe_s  #(`LMQ_WIDTH) lmq2 (
462 95 fafa1971 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
463 
        .q      (lmq2_pcx_pkt[`LMQ_VLD:0]),
464 
        .en     (lmq_enable[2]), .clk (clk),
465 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
466 95 fafa1971 
        );
467 
*/
468 
wire lmq2_clk;
469 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
470 
`else
471 
clken_buf lmq2_clkbuf (
472 
                .rclk   (clk),
473 
                .enb_l  (~lmq_enable[2]),
474 
                .tmb_l  (~se),
475 
                .clk    (lmq2_clk)
476 
                ) ;
477 
`endif
478 95 fafa1971 
 
479 113 albert.wat 
wire  [`LMQ_VLD:0]  lmq2_pcx_pkt_tmp;
480 95 fafa1971 
 
481 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
482 
dffe_s  #(`LMQ_WIDTH) lmq2 (
483 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
484 
        .q      (lmq2_pcx_pkt_tmp[`LMQ_VLD:0]),
485 95 fafa1971 
        .en (~(~lmq_enable[2])), .clk(clk),
486 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
487 95 fafa1971 
        );
488 113 albert.wat 
`else
489 
dff_s  #(`LMQ_WIDTH) lmq2 (
490 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
491 
        .q      (lmq2_pcx_pkt_tmp[`LMQ_VLD:0]),
492 
        .clk    (lmq2_clk),
493 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
494 
        );
495 
`endif
496 95 fafa1971 
 
497 
//bug2705 - speculative pick in w-cycle
498 
wire    lmq2_pcx_pkt_vld ;
499 113 albert.wat 
assign  lmq2_pcx_pkt_vld  =  lmq2_pcx_pkt_tmp[`LMQ_VLD] & ~lsu_ld2_spec_vld_kill_w2 ;
500 95 fafa1971 
 
501 
 
502 113 albert.wat 
assign  lmq2_pcx_pkt[`LMQ_VLD:0]  =  {lmq2_pcx_pkt_vld,
503 
                                      lmq2_pcx_pkt_tmp[`LMQ_VLD-1:44],
504 95 fafa1971 
                                      lmq2_pcx_pkt_way[1:0],
505 
                                      lmq2_pcx_pkt_tmp[41:0]};
506 
 
507 
assign  ld_sec_hit_thrd2 =
508 113 albert.wat 
(ld_pcx_pkt_g_tmp[`LMQ_AD_HI:`LMQ_AD_LO+4] == lmq2_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO+4]) ;
509 95 fafa1971 
 
510 
// THREAD 3.
511 
/*
512 113 albert.wat 
dffe_s  #(`LMQ_WIDTH) lmq3 (
513 95 fafa1971 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
514 
        .q      (lmq3_pcx_pkt[`LMQ_VLD:0]),
515 
        .en     (lmq_enable[3]), .clk (clk),
516 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
517 95 fafa1971 
        );
518 
*/
519 
wire lmq3_clk;
520 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
521 
`else
522 
clken_buf lmq3_clkbuf (
523 
                .rclk   (clk),
524 
                .enb_l  (~lmq_enable[3]),
525 
                .tmb_l  (~se),
526 
                .clk    (lmq3_clk)
527 
                ) ;
528 
`endif
529 95 fafa1971 
 
530 113 albert.wat 
wire  [`LMQ_VLD:0]  lmq3_pcx_pkt_tmp;
531 95 fafa1971 
 
532 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
533 
dffe_s  #(`LMQ_WIDTH) lmq3 (
534 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
535 
        .q      (lmq3_pcx_pkt_tmp[`LMQ_VLD:0]),
536 95 fafa1971 
        .en (~(~lmq_enable[3])), .clk(clk),
537 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
538 95 fafa1971 
        );
539 113 albert.wat 
`else
540 
dff_s  #(`LMQ_WIDTH) lmq3 (
541 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
542 
        .q      (lmq3_pcx_pkt_tmp[`LMQ_VLD:0]),
543 
        .clk    (lmq3_clk),
544 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
545 
        );
546 
`endif
547 95 fafa1971 
 
548 
//bug2705 - speculative pick in w-cycle
549 
wire    lmq3_pcx_pkt_vld ;
550 113 albert.wat 
assign  lmq3_pcx_pkt_vld  =  lmq3_pcx_pkt_tmp[`LMQ_VLD] & ~lsu_ld3_spec_vld_kill_w2 ;
551 95 fafa1971 
 
552 
 
553 113 albert.wat 
assign  lmq3_pcx_pkt[`LMQ_VLD:0]  =  {lmq3_pcx_pkt_vld,
554 
                                      lmq3_pcx_pkt_tmp[`LMQ_VLD-1:44],
555 95 fafa1971 
                                      lmq3_pcx_pkt_way[1:0],
556 
                                      lmq3_pcx_pkt_tmp[41:0]};
557 
 
558 
 
559 
assign  ld_sec_hit_thrd3 =
560 113 albert.wat 
(ld_pcx_pkt_g_tmp[`LMQ_AD_HI:`LMQ_AD_LO+4] == lmq3_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO+4]) ;
561 95 fafa1971 
 
562 
// Select 1 of 4 LMQ Contents.
563 
// selection is based on which thread's load is chosen for pcx.
564 113 albert.wat 
mux4ds  #(`LMQ_WIDTH) lmq_pthrd_sel (
565 
  .in0  (lmq0_pcx_pkt[`LMQ_WIDTH-1:0]),
566 
  .in1  (lmq1_pcx_pkt[`LMQ_WIDTH-1:0]),
567 
  .in2  (lmq2_pcx_pkt[`LMQ_WIDTH-1:0]),
568 
  .in3  (lmq3_pcx_pkt[`LMQ_WIDTH-1:0]),
569 95 fafa1971 
  .sel0 (ld_pcx_rq_sel[0]),
570 
  .sel1   (ld_pcx_rq_sel[1]),
571 
  .sel2 (ld_pcx_rq_sel[2]),
572 
  .sel3   (ld_pcx_rq_sel[3]),
573 113 albert.wat 
  .dout (load_pcx_pkt[`LMQ_WIDTH-1:0])
574 95 fafa1971 
);
575 113 albert.wat 
`endif
576 95 fafa1971 
 
577 113 albert.wat 
assign  lsu_pref_pcx_req = load_pcx_pkt[`LMQ_PREF] ;
578 95 fafa1971 
 
579 
// Choose data to src for fill/bypass.
580 
// E-stage muxing : required for fills specifically.
581 
 
582 113 albert.wat 
   assign lmq0_ldd_vld =   lmq0_pcx_pkt[`LMQ_RD2_VLD];
583 
`ifdef FPGA_SYN_1THREAD
584 
   assign lmq1_ldd_vld =   1'b0;
585 
   assign lmq2_ldd_vld =   1'b0;
586 
   assign lmq3_ldd_vld =   1'b0;
587 
`else
588 
   assign lmq1_ldd_vld =   lmq1_pcx_pkt[`LMQ_RD2_VLD];
589 
   assign lmq2_ldd_vld =   lmq2_pcx_pkt[`LMQ_RD2_VLD];
590 
   assign lmq3_ldd_vld =   lmq3_pcx_pkt[`LMQ_RD2_VLD];
591 
`endif
592 95 fafa1971 
 
593 113 albert.wat 
   assign lmq0_pcx_pkt_addr[10:0] =  lmq0_pcx_pkt[`LMQ_AD_LO + 10 :`LMQ_AD_LO];
594 
`ifdef FPGA_SYN_1THREAD
595 
   assign lmq1_pcx_pkt_addr[10:0] =  11'b0;
596 
   assign lmq2_pcx_pkt_addr[10:0] =  11'b0;
597 
   assign lmq3_pcx_pkt_addr[10:0] =  11'b0;
598 
`else
599 
   assign lmq1_pcx_pkt_addr[10:0] =  lmq1_pcx_pkt[`LMQ_AD_LO + 10 :`LMQ_AD_LO];
600 
   assign lmq2_pcx_pkt_addr[10:0] =  lmq2_pcx_pkt[`LMQ_AD_LO + 10 :`LMQ_AD_LO];
601 
   assign lmq3_pcx_pkt_addr[10:0] =  lmq3_pcx_pkt[`LMQ_AD_LO + 10 :`LMQ_AD_LO];
602 
`endif
603 95 fafa1971 
 
604 113 albert.wat 
   assign lmq0_ld_rq_type[2:0] = lmq0_pcx_pkt[`LMQ_RQ_HI:`LMQ_RQ_LO];
605 
`ifdef FPGA_SYN_1THREAD
606 
   assign lmq1_ld_rq_type[2:0] = 3'b0;
607 
   assign lmq2_ld_rq_type[2:0] = 3'b0;
608 
   assign lmq3_ld_rq_type[2:0] = 3'b0;
609 
`else
610 
   assign lmq1_ld_rq_type[2:0] = lmq1_pcx_pkt[`LMQ_RQ_HI:`LMQ_RQ_LO];
611 
   assign lmq2_ld_rq_type[2:0] = lmq2_pcx_pkt[`LMQ_RQ_HI:`LMQ_RQ_LO];
612 
   assign lmq3_ld_rq_type[2:0] = lmq3_pcx_pkt[`LMQ_RQ_HI:`LMQ_RQ_LO];
613 
`endif
614 95 fafa1971 
 
615 113 albert.wat 
    assign lmq0_l2fill_fpld =  lmq0_pcx_pkt[`LMQ_FPLD];
616 
`ifdef FPGA_SYN_1THREAD
617 
    assign lmq1_l2fill_fpld =  1'b0;
618 
    assign lmq2_l2fill_fpld =  1'b0;
619 
    assign lmq3_l2fill_fpld =  1'b0;
620 
`else
621 
    assign lmq1_l2fill_fpld =  lmq1_pcx_pkt[`LMQ_FPLD];
622 
    assign lmq2_l2fill_fpld =  lmq2_pcx_pkt[`LMQ_FPLD];
623 
    assign lmq3_l2fill_fpld =  lmq3_pcx_pkt[`LMQ_FPLD];
624 
`endif
625 95 fafa1971 
/*
626 
   wire    lsu_l2fill_fpld_e;
627 
 
628 
mux4ds  #(44) lmq_dthrd_sel1 (
629 
  .in0  ({lmq0_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], lmq0_pcx_pkt[`LMQ_NC],
630 
          lmq0_pcx_pkt[`LMQ_FPLD],lmq0_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
631 
  .in1  ({lmq1_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], lmq1_pcx_pkt[`LMQ_NC],
632 
          lmq1_pcx_pkt[`LMQ_FPLD],lmq1_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
633 
  .in2  ({lmq2_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], lmq2_pcx_pkt[`LMQ_NC],
634 
          lmq2_pcx_pkt[`LMQ_FPLD],lmq2_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
635 
  .in3  ({lmq3_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], lmq3_pcx_pkt[`LMQ_NC],
636 
          lmq3_pcx_pkt[`LMQ_FPLD],lmq3_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
637 
  .sel0 (dfq_byp_sel[0]),
638 
  .sel1 (dfq_byp_sel[1]),
639 
  .sel2 (dfq_byp_sel[2]),
640 
  .sel3 (dfq_byp_sel[3]),
641 
  .dout ({lmq_ld_addr[39:0], lsu_ncache_ld_e,
642 
          lsu_l2fill_fpld_e, lsu_byp_misc_sz_e[1:0]})
643 
);
644 
*/
645 
 
646 113 albert.wat 
   assign  lmq0_ncache_ld =   lmq0_pcx_pkt[`LMQ_NC];
647 
`ifdef FPGA_SYN_1THREAD
648 
   assign  lmq1_ncache_ld =   1'b0;
649 
   assign  lmq2_ncache_ld =   1'b0;
650 
   assign  lmq3_ncache_ld =   1'b0;
651 
`else
652 
   assign  lmq1_ncache_ld =   lmq1_pcx_pkt[`LMQ_NC];
653 
   assign  lmq2_ncache_ld =   lmq2_pcx_pkt[`LMQ_NC];
654 
   assign  lmq3_ncache_ld =   lmq3_pcx_pkt[`LMQ_NC];
655 
`endif
656 95 fafa1971 
 
657 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
658 
   assign lmq_ld_addr[39:0] =  lmq0_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO];
659 
   assign lsu_byp_misc_sz_e[1:0] = lmq0_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO];
660 
   assign lmq_ld_rd1[4:0] = lmq0_pcx_pkt[`LMQ_RD1_HI: `LMQ_RD1_LO];
661 
   assign lsu_l2fill_bendian_m = lmq0_pcx_pkt[`LMQ_BIGEND];
662 
   assign lsu_l2fill_sign_extend_m = lmq0_pcx_pkt[`LMQ_SIGNEXT];
663 
`else
664 95 fafa1971 
mux4ds  #(42) lmq_dthrd_sel1 (
665 113 albert.wat 
  .in0  ({lmq0_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO],
666 
          lmq0_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
667 
  .in1  ({lmq1_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO],
668 
          lmq1_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
669 
  .in2  ({lmq2_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO],
670 
          lmq2_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
671 
  .in3  ({lmq3_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO],
672 
          lmq3_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
673 95 fafa1971 
  .sel0 (dfq_byp_sel[0]),
674 
  .sel1 (dfq_byp_sel[1]),
675 
  .sel2 (dfq_byp_sel[2]),
676 
  .sel3 (dfq_byp_sel[3]),
677 
  .dout ({lmq_ld_addr[39:0], lsu_byp_misc_sz_e[1:0]})
678 
);
679 
 
680 
// POR
681 
// M-stage muxing : require for alignment and bypassing to exu.
682 
// flopped then used in qctl/dctl G-stage
683 
// lmq_ld_rd1 to lsu_qctl
684 
// others to lsu_dctl
685 
 
686 
// M-Stage Muxing
687 
 
688 
mux4ds  #(7) lmq_dthrd_sel2 (
689 113 albert.wat 
  .in0  ({lmq0_pcx_pkt[`LMQ_RD1_HI: `LMQ_RD1_LO],lmq0_pcx_pkt[`LMQ_BIGEND],
690 
    lmq0_pcx_pkt[`LMQ_SIGNEXT]}),
691 
  .in1  ({lmq1_pcx_pkt[`LMQ_RD1_HI: `LMQ_RD1_LO],lmq1_pcx_pkt[`LMQ_BIGEND],
692 
    lmq1_pcx_pkt[`LMQ_SIGNEXT]}),
693 
  .in2  ({lmq2_pcx_pkt[`LMQ_RD1_HI: `LMQ_RD1_LO],lmq2_pcx_pkt[`LMQ_BIGEND],
694 
    lmq2_pcx_pkt[`LMQ_SIGNEXT]}),
695 
  .in3  ({lmq3_pcx_pkt[`LMQ_RD1_HI: `LMQ_RD1_LO],lmq3_pcx_pkt[`LMQ_BIGEND],
696 
    lmq3_pcx_pkt[`LMQ_SIGNEXT]}),
697 95 fafa1971 
  .sel0 (lmq_byp_misc_sel[0]),
698 
  .sel1 (lmq_byp_misc_sel[1]),
699 
  .sel2 (lmq_byp_misc_sel[2]),
700 
  .sel3 (lmq_byp_misc_sel[3]),
701 
  .dout ({lmq_ld_rd1[4:0],lsu_l2fill_bendian_m,lsu_l2fill_sign_extend_m})
702 
);
703 113 albert.wat 
`endif
704 95 fafa1971 
 
705 113 albert.wat 
   assign  lmq0_byp_misc_sz[1:0] = lmq0_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO];
706 
`ifdef FPGA_SYN_1THREAD
707 
   assign  lmq1_byp_misc_sz[1:0] = 2'b0;
708 
   assign  lmq2_byp_misc_sz[1:0] = 2'b0;
709 
   assign  lmq3_byp_misc_sz[1:0] = 2'b0;
710 
`else
711 
   assign  lmq1_byp_misc_sz[1:0] = lmq1_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO];
712 
   assign  lmq2_byp_misc_sz[1:0] = lmq2_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO];
713 
   assign  lmq3_byp_misc_sz[1:0] = lmq3_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO];
714 
`endif
715 95 fafa1971 
 
716 
 
717 
//assign  lmq_pcx_pkt_addr[10:0] = lmq_ld_addr[10:0] ;
718 
 
719 
 
720 
   wire [28:0] dtag_wdata_e;
721 
 
722 
assign  dtag_wdata_e[28:0] =
723 
        ~lsu_dfq_ld_vld ?
724 
        lsu_diagnstc_wr_data_e[29:1] : lmq_ld_addr[39:11] ;
725 
 
726 
// Parity Generation for Tag. Match with macro.
727 
wire    dtag_wr_parity ;
728 
//assign  dtag_wr_parity = ^dtag_wdata_e[28:0] ;
729 
//assign  dtag_wdata_e[29] =
730 
//        ~lsu_dfq_ld_vld ?
731 
//        lsu_diagnstc_dtagv_prty_invrt_e^dtag_wr_parity : dtag_wr_parity ;
732 
 
733 
   wire dtag_wr_parity_7_0, dtag_wr_parity_15_8,
734 
        dtag_wr_parity_23_16,  dtag_wr_parity_28_24;
735 
 
736 
   assign dtag_wr_parity_7_0  =  ^dtag_wdata_e[7:0];   //zzpar8
737 
   assign dtag_wr_parity_15_8 =  ^dtag_wdata_e[15:8];  //zzpar8
738 
   assign dtag_wr_parity_23_16 = ^dtag_wdata_e[23:16]; //zzpar8
739 
   assign dtag_wr_parity_28_24 = ^dtag_wdata_e[28:24]; //zzpar8
740 
 
741 
   wire   dtag_wr_parity_28_24_with_invrt;
742 
 
743 
   assign dtag_wr_parity_28_24_with_invrt =
744 
           (^dtag_wdata_e[28:24]) ^ lsu_diagnstc_dtagv_prty_invrt_e; //zzpar8
745 
 
746 
 
747 
   wire dtag_wr_parity_7_0_m, dtag_wr_parity_15_8_m,
748 
        dtag_wr_parity_23_16_m,  dtag_wr_parity_28_24_m;
749 
   wire lsu_dfq_ld_vld_m;
750 
   wire dtag_wr_parity_28_24_with_invrt_m;
751 
 
752 
 
753 
// 12/12/03 : Change for Macrotest. I didn't mention
754 
// these 4 bits ! Pls check for a max time violation.
755 
wire    dtag_wr_parity_7_0_din, dtag_wr_parity_15_8_din ;
756 
wire    dtag_wr_parity_23_16_din, dtag_wr_parity_28_24_din ;
757 
assign  dtag_wr_parity_7_0_din =
758 
sehold ? dtag_wr_parity_7_0_m : dtag_wr_parity_7_0 ;
759 
assign  dtag_wr_parity_15_8_din =
760 
sehold ? dtag_wr_parity_15_8_m : dtag_wr_parity_15_8 ;
761 
assign  dtag_wr_parity_23_16_din =
762 
sehold ? dtag_wr_parity_23_16_m : dtag_wr_parity_23_16 ;
763 
assign  dtag_wr_parity_28_24_din =
764 
sehold ? dtag_wr_parity_28_24_m : dtag_wr_parity_28_24 ;
765 
 
766 113 albert.wat 
dff_s #(6) tag_parity_m (
767 95 fafa1971 
     .din ({dtag_wr_parity_7_0_din, dtag_wr_parity_15_8_din,
768 
            dtag_wr_parity_23_16_din, dtag_wr_parity_28_24_din,
769 
            lsu_dfq_ld_vld,   dtag_wr_parity_28_24_with_invrt}),
770 
     .q   ({dtag_wr_parity_7_0_m, dtag_wr_parity_15_8_m,
771 
            dtag_wr_parity_23_16_m, dtag_wr_parity_28_24_m,
772 
            lsu_dfq_ld_vld_m, dtag_wr_parity_28_24_with_invrt_m}),
773 
     .clk  (clk),
774 113 albert.wat 
     .se   (1'b0),     `SIMPLY_RISC_SCANIN,          .so ()
775 95 fafa1971 
);
776 
 
777 
assign dtag_wr_parity = dtag_wr_parity_7_0_m ^ dtag_wr_parity_15_8_m ^
778 
                        dtag_wr_parity_23_16_m ^ dtag_wr_parity_28_24_m;
779 
 
780 
   wire dtag_wr_parity_with_invrt;
781 
 
782 
assign dtag_wr_parity_with_invrt =
783 
       dtag_wr_parity_7_0_m ^ dtag_wr_parity_15_8_m ^
784 
       dtag_wr_parity_23_16_m ^ dtag_wr_parity_28_24_with_invrt_m;
785 
 
786 
wire [29:0] dtag_wdata_m;
787 
 
788 
// 12/12/03 : Change for Macrotest.
789 
assign dtag_wdata_m[29] =
790 
        ~(lsu_dfq_ld_vld_m | sehold) ?
791 
        dtag_wr_parity_with_invrt : dtag_wr_parity ;
792 
 
793 
// 12/12/03 : Change for Macrotest.
794 
wire [28:0] dtag_wdata_e_din ;
795 
assign  dtag_wdata_e_din[28:0] =
796 
sehold ? dtag_wdata_m[28:0] : dtag_wdata_e[28:0] ;
797 
 
798 113 albert.wat 
dff_s  #(29) tag_stgm (
799 95 fafa1971 
        .din  (dtag_wdata_e_din[28:0]),
800 
        .q    (dtag_wdata_m[28:0]),
801 
        .clk  (clk),
802 113 albert.wat 
        .se   (1'b0),     `SIMPLY_RISC_SCANIN,          .so ()
803 95 fafa1971 
        );
804 
 
805 
   assign      lsu_error_pa_m[28:0] =  dtag_wdata_m[28:0];
806 
 
807 
 
808 
//=================================================================================================
809 
//    RS3 DATA ALIGNMENT FOR CAS
810 
//=================================================================================================
811 
 
812 
wire  [7:0] rs3_byte0, rs3_byte1, rs3_byte2, rs3_byte3 ;
813 
wire  [7:0] rs3_byte4, rs3_byte5, rs3_byte6, rs3_byte7 ;
814 
wire  [63:0]  atm_byte_g ;
815 
wire  [63:0]  st_rs3_data_m,st_rs3_data_g ;
816 
 
817 113 albert.wat 
dff_s  #(64) rs3_stgm (
818 95 fafa1971 
        .din  (exu_lsu_rs3_data_e[63:0]),
819 
        .q    (st_rs3_data_m[63:0]),
820 
        .clk  (clk),
821 113 albert.wat 
        .se   (1'b0),     `SIMPLY_RISC_SCANIN,          .so ()
822 95 fafa1971 
        );
823 
 
824 
// rm (along with spu).
825 
//assign  lsu_spu_rsrv_data_m[13:0] =
826 
//  {st_rs3_data_m[27:23],st_rs3_data_m[21:16],st_rs3_data_m[8:6]} ;
827 
 
828 113 albert.wat 
dff_s  #(64) rs3_stgg (
829 95 fafa1971 
        .din  (st_rs3_data_m[63:0]),
830 
        .q    (st_rs3_data_g[63:0]),
831 
        .clk  (clk),
832 113 albert.wat 
        .se   (1'b0),     `SIMPLY_RISC_SCANIN,          .so ()
833 95 fafa1971 
        );
834 
 
835 
assign  rs3_byte0[7:0] = st_rs3_data_g[7:0] ;
836 
assign  rs3_byte1[7:0] = st_rs3_data_g[15:8] ;
837 
assign  rs3_byte2[7:0] = st_rs3_data_g[23:16] ;
838 
assign  rs3_byte3[7:0] = st_rs3_data_g[31:24] ;
839 
assign  rs3_byte4[7:0] = st_rs3_data_g[39:32] ;
840 
assign  rs3_byte5[7:0] = st_rs3_data_g[47:40] ;
841 
assign  rs3_byte6[7:0] = st_rs3_data_g[55:48] ;
842 
assign  rs3_byte7[7:0] = st_rs3_data_g[63:56] ;
843 
 
844 
//assign  atm_byte_g[7:0] =
845 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte0[7:0] :
846 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte3[7:0] :
847 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte7[7:0] : 8'bxxxx_xxxx ;
848 
 
849 
mux3ds #(8) mx_atm_byte_g_7_0 (
850 
    .in0 (rs3_byte0[7:0]),
851 
    .in1 (rs3_byte3[7:0]),
852 
    .in2 (rs3_byte7[7:0]),
853 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
854 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
855 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
856 
    .dout(atm_byte_g[7:0]));
857 
 
858 
 
859 
//assign  atm_byte_g[15:8] =
860 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte1[7:0] :
861 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte2[7:0] :
862 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte6[7:0] : 8'bxxxx_xxxx ;
863 
 
864 
mux3ds #(8) mx_atm_byte_g_15_8 (
865 
    .in0 (rs3_byte1[7:0]),
866 
    .in1 (rs3_byte2[7:0]),
867 
    .in2 (rs3_byte6[7:0]),
868 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
869 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
870 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
871 
    .dout(atm_byte_g[15:8]));
872 
 
873 
//assign  atm_byte_g[23:16] =
874 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte2[7:0] :
875 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte1[7:0] :
876 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte5[7:0] : 8'bxxxx_xxxx ;
877 
 
878 
mux3ds #(8) mx_atm_byte_g_23_16 (
879 
    .in0 (rs3_byte2[7:0]),
880 
    .in1 (rs3_byte1[7:0]),
881 
    .in2 (rs3_byte5[7:0]),
882 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
883 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
884 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
885 
    .dout(atm_byte_g[23:16]));
886 
 
887 
//assign  atm_byte_g[31:24] =
888 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte3[7:0] :
889 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte0[7:0] :
890 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte4[7:0] : 8'bxxxx_xxxx ;
891 
 
892 
mux3ds #(8) mx_atm_byte_g_31_24 (
893 
    .in0 (rs3_byte3[7:0]),
894 
    .in1 (rs3_byte0[7:0]),
895 
    .in2 (rs3_byte4[7:0]),
896 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
897 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
898 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
899 
    .dout(atm_byte_g[31:24]));
900 
 
901 
//assign  atm_byte_g[39:32] =
902 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte4[7:0] :
903 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte0[7:0] :
904 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte3[7:0] : 8'bxxxx_xxxx ;
905 
 
906 
mux3ds #(8) mx_atm_byte_g_39_32 (
907 
    .in0 (rs3_byte4[7:0]),
908 
    .in1 (rs3_byte0[7:0]),
909 
    .in2 (rs3_byte3[7:0]),
910 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
911 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
912 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
913 
    .dout(atm_byte_g[39:32]));
914 
 
915 
//assign  atm_byte_g[47:40] =
916 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte5[7:0] :
917 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte1[7:0] :
918 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte2[7:0] : 8'bxxxx_xxxx ;
919 
 
920 
mux3ds #(8) mx_atm_byte_g_47_40(
921 
    .in0 (rs3_byte5[7:0]),
922 
    .in1 (rs3_byte1[7:0]),
923 
    .in2 (rs3_byte2[7:0]),
924 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
925 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
926 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
927 
    .dout(atm_byte_g[47:40]));
928 
 
929 
//assign  atm_byte_g[55:48] =
930 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte6[7:0] :
931 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte2[7:0] :
932 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte1[7:0] : 8'bxxxx_xxxx ;
933 
 
934 
mux3ds #(8) mx_atm_byte_g_55_48(
935 
    .in0 (rs3_byte6[7:0]),
936 
    .in1 (rs3_byte2[7:0]),
937 
    .in2 (rs3_byte1[7:0]),
938 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
939 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
940 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
941 
    .dout(atm_byte_g[55:48]));
942 
 
943 
//assign  atm_byte_g[63:56] =
944 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte7[7:0] :
945 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte3[7:0] :
946 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte0[7:0] : 8'bxxxx_xxxx ;
947 
 
948 
mux3ds #(8) mx_atm_byte_g_63_56 (
949 
    .in0 (rs3_byte7[7:0]),
950 
    .in1 (rs3_byte3[7:0]),
951 
    .in2 (rs3_byte0[7:0]),
952 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
953 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
954 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
955 
    .dout(atm_byte_g[63:56]));
956 
 
957 
//=================================================================================================
958 
//    STB/LDXA DATA BYPASSING
959 
//=================================================================================================
960 
 
961 
// Add STB to load bypass data flops.
962 
// Attempt is made to bypass data in G-stage for load. If not
963 
// possible then flop data and wait for next available bubble.
964 
// Once bypass occurs then load can be considered resolved.
965 
// Load Full Raw bypassing does not have to use DFQ.
966 
 
967 
// ldxa data will reside in bypass flops until an opportunity
968 
// is available to write to irf. ldxa's must write to lmq
969 
// in order to provide information such as rd to irf.
970 
 
971 
// ** The two conditions are mutually exclusive. **
972 
 
973 
// lsu_local_ldxa_data_w2 w/ lsu_misc_rdata_w2 for all 4 threads
974 
 
975 
// 1-hot fix: 8/1/03 - can be multihot during scan
976 
// grape mapper convert the 1 of the inverter used for the select to the logic below
977 
wire  [2:0]  lmq_byp_ldxa_sel0_1hot ;
978 
assign  lmq_byp_ldxa_sel0_1hot[0]  =  lmq_byp_ldxa_sel0[0] & ~rst_tri_en;
979 
assign  lmq_byp_ldxa_sel0_1hot[1]  =  lmq_byp_ldxa_sel0[1] & ~rst_tri_en;
980 
assign  lmq_byp_ldxa_sel0_1hot[2]  =  lmq_byp_ldxa_sel0[2] |  rst_tri_en;
981 
 
982 
 
983 
// THREAD 0
984 
mux3ds  #(64) ldbyp0_ldxa_mx (
985 
  .in0  (ifu_lsu_ldxa_data_w2[63:0]), // ifu-ldxa bypass data
986 
  //.in1  (tlu_lsu_ldxa_data_w2[63:0]), // tlu-ldxa bypass data
987 
  .in1  (spu_lsu_ldxa_data_w2[63:0]), // spu-ldxa bypass data
988 
  .in2  (lsu_misc_rdata_w2[63:0]),    // local asi bypass data
989 
  .sel0 (lmq_byp_ldxa_sel0_1hot[0]),
990 
  //.sel1 (lmq_byp_ldxa_sel0[1]),
991 
  .sel1 (lmq_byp_ldxa_sel0_1hot[1]),
992 
  .sel2 (lmq_byp_ldxa_sel0_1hot[2]),
993 
  .dout (lmq0_bypass_ldxa_data[63:0])
994 
);
995 
 
996 
// 1-hot fix: 8/1/03 - can be multihot during scan
997 
// grape mapper convert the 1 of the inverter used for the select to the logic below
998 
wire  [3:0]  lmq_byp_data_sel0_1hot ;
999 
assign  lmq_byp_data_sel0_1hot[0]  =  lmq_byp_data_sel0[0] ;
1000 
assign  lmq_byp_data_sel0_1hot[1]  =  lmq_byp_data_sel0[1] ;
1001 
assign  lmq_byp_data_sel0_1hot[2]  =  lmq_byp_data_sel0[2] ;
1002 
assign  lmq_byp_data_sel0_1hot[3]  =  lmq_byp_data_sel0[3] ;
1003 
 
1004 
wire    [63:0]   lmq0_bypass_misc_data ;
1005 
mux4ds  #(64) ldbyp0_data_mx (
1006 
  .in0  (stb_rdata_ramd[63:0]),   // stb bypass data
1007 
  .in1  (exu_lsu_rs3_data_e[63:0]), // rs3 data
1008 
  .in2  (atm_byte_g[63:0]),   // cas formatted data
1009 
  .in3  (lmq0_bypass_ldxa_data[63:0]),  // ldxa bypass data
1010 
  .sel0 (lmq_byp_data_sel0_1hot[0]),
1011 
  .sel1 (lmq_byp_data_sel0_1hot[1]),
1012 
  .sel2 (lmq_byp_data_sel0_1hot[2]),
1013 
  .sel3 (lmq_byp_data_sel0_1hot[3]),
1014 
  .dout (lmq0_bypass_misc_data[63:0])
1015 
);
1016 
 
1017 
 
1018 
// 2:1 mux for additional data bus from tlu.
1019 
// Grape : merge into mux-flop.
1020 
mux2ds  #(64) ldbyp0_fmx (
1021 
  .in0  (lmq0_bypass_misc_data[63:0]),
1022 
  .in1  (tlu_lsu_int_ldxa_data_w2[63:0]),
1023 
  .sel0 (~lmq_byp_data_fmx_sel[0]),
1024 
  .sel1 (lmq_byp_data_fmx_sel[0]),
1025 
  .dout (lmq0_bypass_data_in[63:0])
1026 
);
1027 
 
1028 
/*
1029 113 albert.wat 
dffe_s  #(64) ldbyp0_data_ff (
1030 95 fafa1971 
        .din    (lmq0_bypass_data_in[63:0]),
1031 
        .q      (lmq0_bypass_data[63:0]),
1032 
        .en     (lmq_byp_data_en_w2[0]), .clk (clk),
1033 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1034 95 fafa1971 
        );
1035 
*/
1036 
wire ldbyp0_data_clk;
1037 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1038 
`else
1039 
clken_buf ldbyp0_data_clkbuf (
1040 
                .rclk   (clk),
1041 
                .enb_l  (~lmq_byp_data_en_w2[0]),
1042 
                .tmb_l  (~se),
1043 
                .clk    (ldbyp0_data_clk)
1044 
                ) ;
1045 
`endif
1046 95 fafa1971 
 
1047 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1048 
dffe_s  #(64) ldbyp0_data_ff (
1049 95 fafa1971 
        .din    (lmq0_bypass_data_in[63:0]),
1050 
        .q      (lmq0_bypass_data[63:0]),
1051 
        .en (~(~lmq_byp_data_en_w2[0])), .clk(clk),
1052 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1053 95 fafa1971 
        );
1054 113 albert.wat 
`else
1055 
dff_s  #(64) ldbyp0_data_ff (
1056 
        .din    (lmq0_bypass_data_in[63:0]),
1057 
        .q      (lmq0_bypass_data[63:0]),
1058 
        .clk    (ldbyp0_data_clk),
1059 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1060 
        );
1061 
`endif
1062 95 fafa1971 
 
1063 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
1064 
`else
1065 95 fafa1971 
 
1066 
// THREAD 1
1067 
// 1-hot fix: 8/1/03 - can be multihot during scan
1068 
// grape mapper convert the 1 of the inverter used for the select to the logic below
1069 
wire  [2:0]  lmq_byp_ldxa_sel1_1hot ;
1070 
assign  lmq_byp_ldxa_sel1_1hot[0]  =  lmq_byp_ldxa_sel1[0] & ~rst_tri_en;
1071 
assign  lmq_byp_ldxa_sel1_1hot[1]  =  lmq_byp_ldxa_sel1[1] & ~rst_tri_en;
1072 
assign  lmq_byp_ldxa_sel1_1hot[2]  =  lmq_byp_ldxa_sel1[2] |  rst_tri_en;
1073 
 
1074 
 
1075 
mux3ds  #(64) ldbyp1_ldxa_mx (
1076 
        .in0    (ifu_lsu_ldxa_data_w2[63:0]),   // ifu-ldxa bypass data
1077 
        //.in1    (tlu_lsu_ldxa_data_w2[63:0]),   // tlu-ldxa bypass data
1078 
        .in1    (spu_lsu_ldxa_data_w2[63:0]), // spu-ldxa bypass data
1079 
        .in2    (lsu_misc_rdata_w2[63:0]),// local asi bypass data
1080 
        .sel0   (lmq_byp_ldxa_sel1_1hot[0]),
1081 
        //.sel1   (lmq_byp_ldxa_sel1[1]),
1082 
        .sel1   (lmq_byp_ldxa_sel1_1hot[1]),
1083 
        .sel2   (lmq_byp_ldxa_sel1_1hot[2]),
1084 
        .dout   (lmq1_bypass_ldxa_data[63:0])
1085 
);
1086 
 
1087 
// 1-hot fix: 8/1/03 - can be multihot during scan
1088 
// grape mapper convert the 1 of the inverter used for the select to the logic below
1089 
wire  [3:0]  lmq_byp_data_sel1_1hot ;
1090 
assign  lmq_byp_data_sel1_1hot[0]  =  lmq_byp_data_sel1[0] ;
1091 
assign  lmq_byp_data_sel1_1hot[1]  =  lmq_byp_data_sel1[1] ;
1092 
assign  lmq_byp_data_sel1_1hot[2]  =  lmq_byp_data_sel1[2] ;
1093 
assign  lmq_byp_data_sel1_1hot[3]  =  lmq_byp_data_sel1[3] ;
1094 
 
1095 
 
1096 
wire    [63:0]   lmq1_bypass_misc_data ;
1097 
mux4ds  #(64) ldbyp1_data_mx (
1098 
  .in0  (stb_rdata_ramd[63:0]),   // stb bypass data
1099 
  .in1  (exu_lsu_rs3_data_e[63:0]), // rs3 data
1100 
  .in2  (atm_byte_g[63:0]),   // cas formatted data
1101 
  .in3  (lmq1_bypass_ldxa_data[63:0]),  // ldxa bypass data
1102 
  .sel0 (lmq_byp_data_sel1_1hot[0]),
1103 
  .sel1 (lmq_byp_data_sel1_1hot[1]),
1104 
  .sel2 (lmq_byp_data_sel1_1hot[2]),
1105 
  .sel3 (lmq_byp_data_sel1_1hot[3]),
1106 
  .dout (lmq1_bypass_misc_data[63:0])
1107 
);
1108 
 
1109 
// 2:1 mux for additional data bus from tlu.
1110 
// Grape : merge into mux-flop.
1111 
mux2ds  #(64) ldbyp1_fmx (
1112 
  .in0  (lmq1_bypass_misc_data[63:0]),
1113 
  .in1  (tlu_lsu_int_ldxa_data_w2[63:0]),
1114 
  .sel0 (~lmq_byp_data_fmx_sel[1]),
1115 
  .sel1 (lmq_byp_data_fmx_sel[1]),
1116 
  .dout (lmq1_bypass_data_in[63:0])
1117 
);
1118 
 
1119 
/*
1120 113 albert.wat 
dffe_s  #(64) ldbyp1_data_ff (
1121 95 fafa1971 
        .din    (lmq1_bypass_data_in[63:0]),
1122 
        .q      (lmq1_bypass_data[63:0]),
1123 
        .en     (lmq_byp_data_en_w2[1]), .clk (clk),
1124 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1125 95 fafa1971 
        );
1126 
*/
1127 
wire ldbyp1_data_clk;
1128 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1129 
`else
1130 
clken_buf ldbyp1_data_clkbuf (
1131 
                .rclk   (clk),
1132 
                .enb_l  (~lmq_byp_data_en_w2[1]),
1133 
                .tmb_l  (~se),
1134 
                .clk    (ldbyp1_data_clk)
1135 
                ) ;
1136 
`endif
1137 95 fafa1971 
 
1138 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1139 
dffe_s  #(64) ldbyp1_data_ff (
1140 95 fafa1971 
        .din    (lmq1_bypass_data_in[63:0]),
1141 
        .q      (lmq1_bypass_data[63:0]),
1142 
        .en (~(~lmq_byp_data_en_w2[1])), .clk(clk),
1143 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1144 95 fafa1971 
        );
1145 113 albert.wat 
`else
1146 
dff_s  #(64) ldbyp1_data_ff (
1147 
        .din    (lmq1_bypass_data_in[63:0]),
1148 
        .q      (lmq1_bypass_data[63:0]),
1149 
        .clk    (ldbyp1_data_clk),
1150 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1151 
        );
1152 
`endif
1153 95 fafa1971 
 
1154 
// THREAD 2
1155 
// 1-hot fix: 8/1/03 - can be multihot during scan
1156 
// grape mapper convert the 1 of the inverter used for the select to the logic below
1157 
wire  [2:0]  lmq_byp_ldxa_sel2_1hot ;
1158 
assign  lmq_byp_ldxa_sel2_1hot[0]  =  lmq_byp_ldxa_sel2[0] & ~rst_tri_en;
1159 
assign  lmq_byp_ldxa_sel2_1hot[1]  =  lmq_byp_ldxa_sel2[1] & ~rst_tri_en;
1160 
assign  lmq_byp_ldxa_sel2_1hot[2]  =  lmq_byp_ldxa_sel2[2] |  rst_tri_en;
1161 
 
1162 
 
1163 
mux3ds  #(64) ldbyp2_data_mx (
1164 
        .in0    (ifu_lsu_ldxa_data_w2[63:0]),   // ifu-ldxa bypass data
1165 
        //.in1    (tlu_lsu_ldxa_data_w2[63:0]),   // tlu-ldxa bypass data
1166 
        .in1    (spu_lsu_ldxa_data_w2[63:0]), // spu-ldxa bypass data
1167 
        .in2    (lsu_misc_rdata_w2[63:0]),// local asi bypass data
1168 
        .sel0   (lmq_byp_ldxa_sel2_1hot[0]),
1169 
        //.sel1   (lmq_byp_ldxa_sel2[1]),
1170 
        .sel1 (lmq_byp_ldxa_sel2_1hot[1]),
1171 
        .sel2 (lmq_byp_ldxa_sel2_1hot[2]),
1172 
        .dout   (lmq2_bypass_ldxa_data[63:0])
1173 
);
1174 
 
1175 
// 1-hot fix: 8/1/03 - can be multihot during scan
1176 
// grape mapper convert the 1 of the inverter used for the select to the logic below
1177 
wire  [3:0]  lmq_byp_data_sel2_1hot ;
1178 
assign  lmq_byp_data_sel2_1hot[0]  =  lmq_byp_data_sel2[0] ;
1179 
assign  lmq_byp_data_sel2_1hot[1]  =  lmq_byp_data_sel2[1] ;
1180 
assign  lmq_byp_data_sel2_1hot[2]  =  lmq_byp_data_sel2[2] ;
1181 
assign  lmq_byp_data_sel2_1hot[3]  =  lmq_byp_data_sel2[3] ;
1182 
 
1183 
 
1184 
wire    [63:0]   lmq2_bypass_misc_data ;
1185 
mux4ds  #(64) ldbyp2_ldxa_mx (
1186 
  .in0  (stb_rdata_ramd[63:0]),   // stb bypass data
1187 
  .in1  (exu_lsu_rs3_data_e[63:0]), // rs3 data
1188 
  .in2  (atm_byte_g[63:0]),   // cas formatted data
1189 
  .in3  (lmq2_bypass_ldxa_data[63:0]),  // ldxa bypass data
1190 
  .sel0 (lmq_byp_data_sel2_1hot[0]),
1191 
  .sel1 (lmq_byp_data_sel2_1hot[1]),
1192 
  .sel2 (lmq_byp_data_sel2_1hot[2]),
1193 
  .sel3 (lmq_byp_data_sel2_1hot[3]),
1194 
  .dout (lmq2_bypass_misc_data[63:0])
1195 
);
1196 
 
1197 
// 2:1 mux for additional data bus from tlu.
1198 
// Grape : merge into mux-flop.
1199 
mux2ds  #(64) ldbyp2_fmx (
1200 
  .in0  (lmq2_bypass_misc_data[63:0]),
1201 
  .in1  (tlu_lsu_int_ldxa_data_w2[63:0]),
1202 
  .sel0 (~lmq_byp_data_fmx_sel[2]),
1203 
  .sel1 (lmq_byp_data_fmx_sel[2]),
1204 
  .dout (lmq2_bypass_data_in[63:0])
1205 
);
1206 
 
1207 
/*
1208 113 albert.wat 
dffe_s  #(64) ldbyp2_data_ff (
1209 95 fafa1971 
        .din    (lmq2_bypass_data_in[63:0]),
1210 
        .q      (lmq2_bypass_data[63:0]),
1211 
        .en     (lmq_byp_data_en_w2[2]), .clk (clk),
1212 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1213 95 fafa1971 
        );
1214 
*/
1215 
wire ldbyp2_data_clk;
1216 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1217 
`else
1218 
clken_buf ldbyp2_data_clkbuf (
1219 
                .rclk   (clk),
1220 
                .enb_l  (~lmq_byp_data_en_w2[2]),
1221 
                .tmb_l  (~se),
1222 
                .clk    (ldbyp2_data_clk)
1223 
                ) ;
1224 
`endif
1225 95 fafa1971 
 
1226 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1227 
dffe_s  #(64) ldbyp2_data_ff (
1228 95 fafa1971 
        .din    (lmq2_bypass_data_in[63:0]),
1229 
        .q      (lmq2_bypass_data[63:0]),
1230 
        .en (~(~lmq_byp_data_en_w2[2])), .clk(clk),
1231 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1232 95 fafa1971 
        );
1233 113 albert.wat 
`else
1234 
dff_s  #(64) ldbyp2_data_ff (
1235 
        .din    (lmq2_bypass_data_in[63:0]),
1236 
        .q      (lmq2_bypass_data[63:0]),
1237 
        .clk    (ldbyp2_data_clk),
1238 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1239 
        );
1240 
`endif
1241 95 fafa1971 
 
1242 
// THREAD 3
1243 
// 1-hot fix: 8/1/03 - can be multihot during scan
1244 
// grape mapper convert the 1 of the inverter used for the select to the logic below
1245 
wire  [2:0]  lmq_byp_ldxa_sel3_1hot ;
1246 
assign  lmq_byp_ldxa_sel3_1hot[0]  =  lmq_byp_ldxa_sel3[0] & ~rst_tri_en;
1247 
assign  lmq_byp_ldxa_sel3_1hot[1]  =  lmq_byp_ldxa_sel3[1] & ~rst_tri_en;
1248 
assign  lmq_byp_ldxa_sel3_1hot[2]  =  lmq_byp_ldxa_sel3[2] |  rst_tri_en;
1249 
 
1250 
 
1251 
mux3ds  #(64) ldbyp3_data_mx (
1252 
        .in0    (ifu_lsu_ldxa_data_w2[63:0]),   // ifu-ldxa bypass data
1253 
        //.in1    (tlu_lsu_ldxa_data_w2[63:0]),   // tlu-ldxa bypass data
1254 
        .in1    (spu_lsu_ldxa_data_w2[63:0]), // spu-ldxa bypass data
1255 
        .in2    (lsu_misc_rdata_w2[63:0]),// local asi bypass data
1256 
        .sel0   (lmq_byp_ldxa_sel3_1hot[0]),
1257 
        //.sel1   (lmq_byp_ldxa_sel3[1]),
1258 
        .sel1   (lmq_byp_ldxa_sel3_1hot[1]),
1259 
        .sel2   (lmq_byp_ldxa_sel3_1hot[2]),
1260 
        .dout   (lmq3_bypass_ldxa_data[63:0])
1261 
);
1262 
 
1263 
// 1-hot fix: 8/1/03 - can be multihot during scan
1264 
// grape mapper convert the 1 of the inverter used for the select to the logic below
1265 
wire  [3:0]  lmq_byp_data_sel3_1hot ;
1266 
assign  lmq_byp_data_sel3_1hot[0]  =  lmq_byp_data_sel3[0] ;
1267 
assign  lmq_byp_data_sel3_1hot[1]  =  lmq_byp_data_sel3[1] ;
1268 
assign  lmq_byp_data_sel3_1hot[2]  =  lmq_byp_data_sel3[2] ;
1269 
assign  lmq_byp_data_sel3_1hot[3]  =  lmq_byp_data_sel3[3] ;
1270 
 
1271 
 
1272 
wire    [63:0]   lmq3_bypass_misc_data ;
1273 
mux4ds  #(64) ldbyp3_ldxa_mx (
1274 
  .in0  (stb_rdata_ramd[63:0]),   // stb bypass data
1275 
  .in1  (exu_lsu_rs3_data_e[63:0]), // rs3 data
1276 
  .in2  (atm_byte_g[63:0]),   // cas formatted data
1277 
  .in3  (lmq3_bypass_ldxa_data[63:0]),  // ldxa bypass data
1278 
  .sel0 (lmq_byp_data_sel3_1hot[0]),
1279 
  .sel1 (lmq_byp_data_sel3_1hot[1]),
1280 
  .sel2 (lmq_byp_data_sel3_1hot[2]),
1281 
  .sel3 (lmq_byp_data_sel3_1hot[3]),
1282 
  .dout (lmq3_bypass_misc_data[63:0])
1283 
);
1284 
 
1285 
// 2:1 mux for additional data bus from tlu.
1286 
// Grape : merge into mux-flop.
1287 
mux2ds  #(64) ldbyp3_fmx (
1288 
  .in0  (lmq3_bypass_misc_data[63:0]),
1289 
  .in1  (tlu_lsu_int_ldxa_data_w2[63:0]),
1290 
  .sel0 (~lmq_byp_data_fmx_sel[3]),
1291 
  .sel1 (lmq_byp_data_fmx_sel[3]),
1292 
  .dout (lmq3_bypass_data_in[63:0])
1293 
);
1294 
 
1295 
/*
1296 113 albert.wat 
dffe_s  #(64) ldbyp3_data_ff (
1297 95 fafa1971 
        .din    (lmq3_bypass_data_in[63:0]),
1298 
        .q      (lmq3_bypass_data[63:0]),
1299 
        .en     (lmq_byp_data_en_w2[3]), .clk (clk),
1300 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1301 95 fafa1971 
        );
1302 
*/
1303 
wire ldbyp3_data_clk;
1304 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1305 
`else
1306 
clken_buf ldbyp3_data_clkbuf (
1307 
                .rclk   (clk),
1308 
                .enb_l  (~lmq_byp_data_en_w2[3]),
1309 
                .tmb_l  (~se),
1310 
                .clk    (ldbyp3_data_clk)
1311 
                ) ;
1312 
`endif
1313 95 fafa1971 
 
1314 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1315 
dffe_s  #(64) ldbyp3_data_ff (
1316 95 fafa1971 
        .din    (lmq3_bypass_data_in[63:0]),
1317 
        .q      (lmq3_bypass_data[63:0]),
1318 
        .en (~(~lmq_byp_data_en_w2[3])), .clk(clk),
1319 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1320 95 fafa1971 
        );
1321 113 albert.wat 
`else
1322 
dff_s  #(64) ldbyp3_data_ff (
1323 
        .din    (lmq3_bypass_data_in[63:0]),
1324 
        .q      (lmq3_bypass_data[63:0]),
1325 
        .clk    (ldbyp3_data_clk),
1326 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1327 
        );
1328 
`endif
1329 95 fafa1971 
 
1330 113 albert.wat 
`endif
1331 95 fafa1971 
 
1332 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
1333 
  assign cas_pkt2_data[63:0] = lmq0_bypass_data[63:0];
1334 
  assign tlb_st_data[63:0] = lmq0_bypass_data[63:0];
1335 
`else
1336 95 fafa1971 
// This can be merged with above mux !!!!
1337 
mux4ds  #(64) ld_byp_cas_mx (
1338 
  .in0  (lmq0_bypass_data[63:0]),
1339 
  .in1  (lmq1_bypass_data[63:0]),
1340 
  .in2  (lmq2_bypass_data[63:0]),
1341 
  .in3  (lmq3_bypass_data[63:0]),
1342 
  .sel0 (ld_pcx_rq_sel[0]),
1343 
  .sel1   (ld_pcx_rq_sel[1]),
1344 
  .sel2 (ld_pcx_rq_sel[2]),
1345 
  .sel3   (ld_pcx_rq_sel[3]),
1346 
  .dout (cas_pkt2_data[63:0])
1347 
);
1348 
 
1349 
// Can this be merged with above muxes ?
1350 
mux4ds  #(64) tlb_st_mx (
1351 
  .in0  (lmq0_bypass_data[63:0]),
1352 
  .in1  (lmq1_bypass_data[63:0]),
1353 
  .in2  (lmq2_bypass_data[63:0]),
1354 
  .in3  (lmq3_bypass_data[63:0]),
1355 
  .sel0 (lsu_tlb_st_sel_m[0]),
1356 
  .sel1   (lsu_tlb_st_sel_m[1]),
1357 
  .sel2 (lsu_tlb_st_sel_m[2]),
1358 
  .sel3   (lsu_tlb_st_sel_m[3]),
1359 
  .dout (tlb_st_data[63:0])
1360 
);
1361 113 albert.wat 
`endif
1362 95 fafa1971 
 
1363 
/*mux4ds  #(64) tlb_st_mx (
1364 
  .in0  (lmq0_bypass_data[63:0]),
1365 
  .in1  (lmq1_bypass_data[63:0]),
1366 
  .in2  (lmq2_bypass_data[63:0]),
1367 
  .in3  (lmq3_bypass_data[63:0]),
1368 
  .sel0 (lsu_tlb_st_sel_g[0]),
1369 
  .sel1   (lsu_tlb_st_sel_g[1]),
1370 
  .sel2 (lsu_tlb_st_sel_g[2]),
1371 
  .sel3   (lsu_tlb_st_sel_g[3]),
1372 
  .dout (tlb_st_data[63:0])
1373 
);*/
1374 
 
1375 
wire    [63:0] tlb_st_data_d1 ;
1376 113 albert.wat 
dff_s  #(64) std_d1 (
1377 95 fafa1971 
        .din    (tlb_st_data[63:0]),
1378 
        .q      (tlb_st_data_d1[63:0]),
1379 
        .clk    (clk),
1380 113 albert.wat 
        .se     (1'b0),     `SIMPLY_RISC_SCANIN,          .so ()
1381 95 fafa1971 
        );
1382 
 
1383 
// Begin - Bug3487.
1384 
 
1385 
 
1386 
wire asi_data_clk;
1387 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1388 
`else
1389 
clken_buf asid_clkbuf (
1390 
                .rclk   (clk),
1391 
                .enb_l  (lsu_ifu_asi_data_en_l),
1392 
                .tmb_l  (~se),
1393 
                .clk    (asi_data_clk)
1394 
                ) ;
1395 
`endif
1396 95 fafa1971 
 
1397 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1398 
dffe_s  #(48) ifu_std_d1 (
1399 95 fafa1971 
        .din    (tlb_st_data[47:0]),
1400 
        .q      (lsu_ifu_stxa_data[47:0]),
1401 
        .en (~(lsu_ifu_asi_data_en_l)), .clk(clk),
1402 113 albert.wat 
        .se     (1'b0),     `SIMPLY_RISC_SCANIN,          .so ()
1403 95 fafa1971 
        );
1404 113 albert.wat 
`else
1405 
dff_s  #(48) ifu_std_d1 (
1406 
        .din    (tlb_st_data[47:0]),
1407 
        .q      (lsu_ifu_stxa_data[47:0]),
1408 
        .clk    (asi_data_clk),
1409 
        .se     (1'b0),     `SIMPLY_RISC_SCANIN,          .so ()
1410 
        );
1411 
`endif
1412 95 fafa1971 
 
1413 
// select is now a stage earlier, which should be
1414 
// fine as selects stay constant.
1415 
//assign  lsu_ifu_stxa_data[47:0] = tlb_st_data_d1[47:0] ;
1416 
 
1417 
// End - Bug3487.
1418 
 
1419 
 
1420 
//wire    [3:0]   lsu_diag_access_sel_d1 ;
1421 
 
1422 
//dff #(4)  diagsel_stgd1 (
1423 
//        .din    (lsu_diag_access_sel[3:0]),
1424 
//        .q      (lsu_diag_access_sel_d1[3:0]),
1425 
//        .clk    (clk),
1426 113 albert.wat 
//        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1427 95 fafa1971 
//        );
1428 
 
1429 
//mux4ds  #(64) diag_st_mx (
1430 
//  .in0  (lmq0_bypass_data[63:0]),
1431 
//  .in1  (lmq1_bypass_data[63:0]),
1432 
//  .in2  (lmq2_bypass_data[63:0]),
1433 
//  .in3  (lmq3_bypass_data[63:0]),
1434 
//  .sel0 (lsu_diag_access_sel_d1[0]),
1435 
//  .sel1 (lsu_diag_access_sel_d1[1]),
1436 
//  .sel2 (lsu_diag_access_sel_d1[2]),
1437 
//  .sel3 (lsu_diag_access_sel_d1[3]),
1438 
//  .dout (lsu_diagnstc_wr_data_e[63:0])
1439 
//);
1440 
 
1441 
// 1-hot fix: 8/1/03 - can be multihot during scan
1442 
// grape mapper convert the 1 of the inverter used for the select to the logic below
1443 
wire  [3:0]  lsu_diagnstc_data_sel_1hot ;
1444 
assign  lsu_diagnstc_data_sel_1hot[0]  =  lsu_diagnstc_data_sel[0] & ~rst_tri_en;
1445 
assign  lsu_diagnstc_data_sel_1hot[1]  =  lsu_diagnstc_data_sel[1] & ~rst_tri_en;
1446 
assign  lsu_diagnstc_data_sel_1hot[2]  =  lsu_diagnstc_data_sel[2] & ~rst_tri_en;
1447 
assign  lsu_diagnstc_data_sel_1hot[3]  =  lsu_diagnstc_data_sel[3] |  rst_tri_en;
1448 
 
1449 
 
1450 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
1451 
  assign lsu_diagnstc_wr_data_e[63:0] = lmq0_bypass_data[63:0];
1452 
`else
1453 95 fafa1971 
mux4ds  #(64) diag_st_mx (
1454 
  .in0  (lmq0_bypass_data[63:0]),
1455 
  .in1  (lmq1_bypass_data[63:0]),
1456 
  .in2  (lmq2_bypass_data[63:0]),
1457 
  .in3  (lmq3_bypass_data[63:0]),
1458 
  .sel0 (lsu_diagnstc_data_sel_1hot[0]),
1459 
  .sel1 (lsu_diagnstc_data_sel_1hot[1]),
1460 
  .sel2 (lsu_diagnstc_data_sel_1hot[2]),
1461 
  .sel3 (lsu_diagnstc_data_sel_1hot[3]),
1462 
  .dout (lsu_diagnstc_wr_data_e[63:0])
1463 
);
1464 113 albert.wat 
`endif
1465 95 fafa1971 
 
1466 
// Remove flops
1467 
/*dff  #(64) dgndt_d1 (
1468 
        .din    (tlb_st_data[63:0]),
1469 
        .q      (lsu_diagnstc_wr_data_e[63:0]),
1470 
        .clk    (clk),
1471 113 albert.wat 
        .se     (1'b0),     `SIMPLY_RISC_SCANIN,          .so ()
1472 95 fafa1971 
        ); */
1473 
 
1474 
assign lsu_diagnstc_wr_data_b0 = lsu_diagnstc_wr_data_e[0] ;
1475 
 
1476 
// Move tte format and parity calc to tlbdp
1477 
 
1478 
//assign lsu_tlu_st_rs3_data_g[63:0] = tlb_st_data_d1[63:0];
1479 
assign lsu_tlu_st_rs3_data_g[47:3] = tlb_st_data_d1[47:3];
1480 
assign lsu_mmu_rs3_data_g[63:0] = tlb_st_data_d1[63:0];
1481 
assign lsu_tlu_rs3_data_g[63:0] = tlb_st_data_d1[63:0];
1482 
 
1483 
// Removed Fast bypass as penalty is negligible.
1484 
 
1485 
//=================================================================================================
1486 
//    STQ PKT2 DATA
1487 
//=================================================================================================
1488 
 
1489 
//** stquad support removed **
1490 
 
1491 
//=================================================================================================
1492 
//    IMISS/SPU DP
1493 
//=================================================================================================
1494 
 
1495 
// Format of IFU pcx packet (50b) :
1496 
//  b49 - valid
1497 
//  b48:44 - req type
1498 
//  b43:42 - rep way (for "eviction" - maintains directory consistency )
1499 
//  b41:40 - mil id
1500 
//  b39:0  - imiss address
1501 
 
1502 
 
1503 
// Align ifu pkt with ldst pkt - temporary !
1504 
// Does this need to be enabled ?!!!! No.
1505 
assign  ifu_pcx_pkt_e[51:0] = ifu_pcx_pkt[51:0] ;
1506 
 
1507 
// Form pcx-wide ifu request packet.
1508 113 albert.wat 
assign  ifu_full_pcx_pkt_e[`PCX_VLD] = ifu_pcx_pkt_e[51] ;
1509 
assign  ifu_full_pcx_pkt_e[`PCX_RQ_HI:`PCX_RQ_LO] = ifu_pcx_pkt_e[48:44];
1510 
assign  ifu_full_pcx_pkt_e[`PCX_NC] = ifu_pcx_pkt_e[49] ;
1511 
assign  ifu_full_pcx_pkt_e[`PCX_CP_HI:`PCX_CP_LO] = const_cpuid[2:0] ;
1512 95 fafa1971 
// thread-id unused - use mil id instead.
1513 113 albert.wat 
assign  ifu_full_pcx_pkt_e[`PCX_TH_HI:`PCX_TH_LO] = ifu_pcx_pkt_e[41:40] ;
1514 
assign  ifu_full_pcx_pkt_e[`PCX_BF_HI] =  ifu_pcx_pkt_e[50] ;
1515 
assign  ifu_full_pcx_pkt_e[`PCX_BF_HI-1:`PCX_BF_LO] =  2'b00;
1516 
assign  ifu_full_pcx_pkt_e[`PCX_WY_HI:`PCX_WY_LO] =  ifu_pcx_pkt_e[43:42] ;
1517 95 fafa1971 
// unused - always infer 32b
1518 113 albert.wat 
assign  ifu_full_pcx_pkt_e[`PCX_SZ_HI:`PCX_SZ_LO] =  3'b000 ;
1519 
assign  ifu_full_pcx_pkt_e[`PCX_AD_HI:`PCX_AD_LO] =  ifu_pcx_pkt_e[39:0] ;
1520 95 fafa1971 
// no data
1521 113 albert.wat 
assign  ifu_full_pcx_pkt_e[`PCX_DA_HI:`PCX_DA_LO] =  64'd0 ;
1522 95 fafa1971 
 
1523 
// Form pcx-wide interrupt request packet.
1524 113 albert.wat 
assign  intrpt_full_pcxpkt[`PCX_VLD] = tlu_lsu_pcxpkt[25] ;
1525 
assign  intrpt_full_pcxpkt[`PCX_RQ_HI:`PCX_RQ_LO] = tlu_lsu_pcxpkt[24:20];
1526 
assign  intrpt_full_pcxpkt[`PCX_NC] = 1'b0 ;
1527 95 fafa1971 
 
1528 
//tlu_lsu_pcxpkt[12:8] is the 5 bit interrupt destination thread id,
1529 
//so [12:10] is the cpu id, and [9:8] is the thread id.
1530 113 albert.wat 
assign  intrpt_full_pcxpkt[`PCX_CP_HI:`PCX_CP_LO] = tlu_lsu_pcxpkt[12:10];
1531 95 fafa1971 
 
1532 
// or should thread-id be 19:18 ?
1533 113 albert.wat 
assign  intrpt_full_pcxpkt[`PCX_TH_HI:`PCX_TH_LO] = tlu_lsu_pcxpkt[19:18] ;
1534 95 fafa1971 
// May actually make undriven fields x.
1535 113 albert.wat 
assign  intrpt_full_pcxpkt[`PCX_BF_HI:`PCX_BF_LO] =  3'b000;
1536 
assign  intrpt_full_pcxpkt[`PCX_WY_HI:`PCX_WY_LO] =  2'b00 ;
1537 
assign  intrpt_full_pcxpkt[`PCX_SZ_HI:`PCX_SZ_LO] =  3'b000 ;
1538 
assign  intrpt_full_pcxpkt[`PCX_AD_HI:`PCX_AD_LO] =  40'd0 ;
1539 
assign  intrpt_full_pcxpkt[`PCX_DA_HI:`PCX_DA_LO] =  {46'd0,tlu_lsu_pcxpkt[17:0]} ;
1540 95 fafa1971 
 
1541 
// Format fpop_full_pcxpkt.
1542 
 
1543 113 albert.wat 
assign  fpop_full_pcxpkt[`PCX_VLD] = ffu_lsu_data[80] ;
1544 
assign  fpop_full_pcxpkt[`PCX_RQ_HI:`PCX_RQ_LO] = {4'b0101,ffu_lsu_data[78]} ;
1545 
assign  fpop_full_pcxpkt[`PCX_NC] = 1'b0 ;
1546 
assign  fpop_full_pcxpkt[`PCX_CP_HI:`PCX_CP_LO] = const_cpuid[2:0] ;
1547 
assign  fpop_full_pcxpkt[`PCX_TH_HI:`PCX_TH_LO] = ffu_lsu_data[77:76] ;
1548 
assign  fpop_full_pcxpkt[`PCX_BF_HI:`PCX_SZ_LO] = 8'd0 ;
1549 
assign  fpop_full_pcxpkt[`PCX_AD_HI:`PCX_AD_LO+16] = 24'd0 ;
1550 
assign  fpop_full_pcxpkt[`PCX_AD_LO+15:`PCX_AD_LO+8] = ffu_lsu_data[75:68]; // 79:72
1551 
assign  fpop_full_pcxpkt[`PCX_AD_LO+7:`PCX_AD_LO+4] = 4'b0000;      // 71:68
1552 
assign  fpop_full_pcxpkt[`PCX_AD_LO+3:`PCX_AD_LO] = ffu_lsu_data[67:64] ; // 67:64
1553 
assign  fpop_full_pcxpkt[`PCX_DA_HI:`PCX_DA_LO] = ffu_lsu_data[63:0] ;
1554 95 fafa1971 
 
1555 
 
1556 
// RAMTest Data Merging.
1557 
wire cacherd_clk;
1558 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1559 
`else
1560 
clken_buf cacherd_clkbuf (
1561 
                .rclk   (clk),
1562 
                .enb_l  (~lsu_ramtest_rd_w),
1563 
                .tmb_l  (~se),
1564 
                .clk    (cacherd_clk)
1565 
                ) ;
1566 
`endif
1567 95 fafa1971 
 
1568 
wire  [63:0]  cache_rdata_w,cache_rdata_w2 ;
1569 
 
1570 
mux2ds  #(64) cacherd_sel (
1571 
  .in0  (ifu_lsu_ldxa_data_w2[63:0]),
1572 
  .in1  (lsu_dcache_rdata_w[63:0]),
1573 
  .sel0 (~lsu_dcache_iob_rd_w),
1574 
  .sel1 (lsu_dcache_iob_rd_w),
1575 
  .dout (cache_rdata_w[63:0])
1576 
);
1577 
 
1578 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1579 
dffe_s  #(64) cachedata (
1580 95 fafa1971 
        .din    (cache_rdata_w[63:0]),
1581 
        .q      (cache_rdata_w2[63:0]), // references dcache rd staging
1582 
        .en (~(~lsu_ramtest_rd_w)), .clk(clk),
1583 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1584 95 fafa1971 
        );
1585 113 albert.wat 
`else
1586 
dff_s  #(64) cachedata (
1587 
        .din    (cache_rdata_w[63:0]),
1588 
        .q      (cache_rdata_w2[63:0]), // references dcache rd staging
1589 
        .clk    (cacherd_clk),
1590 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1591 
        );
1592 
`endif
1593 95 fafa1971 
 
1594 113 albert.wat 
assign  fwd_full_pcxpkt[`PCX_VLD] = 1'b1 ;
1595 
assign  fwd_full_pcxpkt[`PCX_RQ_HI:`PCX_RQ_LO] = {3'b011,lsu_pcx_fwd_reply,~lsu_pcx_fwd_reply} ;
1596 
assign  fwd_full_pcxpkt[`PCX_NC] = lsu_pcx_fwd_pkt[107] ;
1597 
assign  fwd_full_pcxpkt[`PCX_CP_HI:`PCX_CP_LO] = lsu_pcx_fwd_pkt[106:104] ;
1598 
assign  fwd_full_pcxpkt[`PCX_TH_HI:`PCX_TH_LO] = 2'b00 ;
1599 
assign  fwd_full_pcxpkt[`PCX_BF_HI:`PCX_SZ_LO] =
1600 95 fafa1971 
                        {6'b000000,lsu_fwd_rply_sz1_unc,1'b1} ;
1601 
// All address bits should not be required !!!
1602 113 albert.wat 
assign  fwd_full_pcxpkt[`PCX_AD_HI:`PCX_AD_LO] = lsu_pcx_fwd_pkt[103:64] ;
1603 95 fafa1971 
 
1604 
//  Mux sources of TAP request data - margin,pc,defeature/debug/bist.
1605 
// Be careful about pc - could be a critical path.
1606 
// ** Assume read-data stays constant at output latches of dcache **
1607 
//assign  fwd_full_pcxpkt[`PCX_DA_HI:`PCX_DA_LO] =
1608 
//lsu_iobrdge_rply_data_sel[0] ?  {20'd0,lsu_iobrdge_rd_data[43:0]} :
1609 
//      lsu_iobrdge_rply_data_sel[1] ?  cache_rdata_w2[63:0] :
1610 
//                      lsu_iobrdge_rply_data_sel[2] ?  lsu_pcx_fwd_pkt[63:0] :
1611 
//                                                      64'hxxxx_xxxx_xxxx_xxxx ;
1612 
 
1613 
mux3ds #(64) mx_fwd_full_pcxpkt (
1614 
    .in0 ({20'd0,lsu_iobrdge_rd_data[43:0]}),
1615 
    .in1 (cache_rdata_w2[63:0]),
1616 
    .in2 (lsu_pcx_fwd_pkt[63:0]),
1617 
    .sel0(lsu_iobrdge_rply_data_sel[0]),
1618 
    .sel1(lsu_iobrdge_rply_data_sel[1]),
1619 
    .sel2(lsu_iobrdge_rply_data_sel[2]),
1620 113 albert.wat 
    .dout(fwd_full_pcxpkt[`PCX_DA_HI:`PCX_DA_LO]));
1621 95 fafa1971 
 
1622 
 
1623 113 albert.wat 
wire  [`PCX_WIDTH-1:0]  spu_lsu_ldst_pckt_d1 ;
1624 
dff_s  #(`PCX_WIDTH) ff_spu_lsu_ldst_pckt_d1 (
1625 
        .din  (spu_lsu_ldst_pckt[`PCX_WIDTH-1:0]),
1626 
        .q    (spu_lsu_ldst_pckt_d1[`PCX_WIDTH-1:0]),
1627 95 fafa1971 
        .clk  (clk),
1628 113 albert.wat 
        .se   (1'b0),     `SIMPLY_RISC_SCANIN,          .so ()
1629 95 fafa1971 
        );
1630 
 
1631 113 albert.wat 
assign  imiss_strm_pcx_pkt[`PCX_WIDTH-1:0] = imiss_pcx_mx_sel ?
1632 
          ifu_full_pcx_pkt_e[`PCX_WIDTH-1:0] : spu_lsu_ldst_pckt_d1[`PCX_WIDTH-1:0] ;
1633 95 fafa1971 
 
1634 113 albert.wat 
wire  [`PCX_WIDTH-1:0]  fwd_int_fp_pcx_pkt ;
1635 
mux3ds #(`PCX_WIDTH) mux_fwd_int_fp_pcx_pkt (
1636 
     .in0  (fwd_full_pcxpkt[`PCX_WIDTH-1:0]),
1637 
     .in1  (intrpt_full_pcxpkt[`PCX_WIDTH-1:0]),
1638 
     .in2  (fpop_full_pcxpkt[`PCX_WIDTH-1:0]),
1639 95 fafa1971 
     .sel0 (fwd_int_fp_pcx_mx_sel[0]),
1640 
     .sel1 (fwd_int_fp_pcx_mx_sel[1]),
1641 
     .sel2 (fwd_int_fp_pcx_mx_sel[2]),
1642 113 albert.wat 
     .dout (fwd_int_fp_pcx_pkt [`PCX_WIDTH-1:0])
1643 95 fafa1971 
);
1644 
 
1645 
//=================================================================================================
1646 
//    PCX PKT SELECTION
1647 
//=================================================================================================
1648 
 
1649 113 albert.wat 
assign stb_pcx_pkt[`STB_PCX_VLD] = lsu_stb_pcx_rvld_d1 ;                // Valid
1650 95 fafa1971 
// Support stores for now.
1651 113 albert.wat 
assign stb_pcx_pkt[`STB_PCX_RQ_HI:`STB_PCX_RQ_LO] = stb_rdata_ramd[74:72] ;     // Rq-type
1652 
assign stb_pcx_pkt[`STB_PCX_NC] =
1653 95 fafa1971 
        // Mina the OR gate has been extended to a 3 input gate
1654 
        stb_rdata_ramd[74] | stb_rdata_ramd[73] |       // atomics
1655 
        stb_rdata_ramd[71] ;                            // flush inst
1656 
// cpu-id will be inserted on way out of core.
1657 113 albert.wat 
assign  stb_pcx_pkt[`STB_PCX_TH_HI:`STB_PCX_TH_LO] = lsu_stb_rd_tid[1:0] ;    // TID
1658 95 fafa1971 
// bf-id is not required.
1659 
// mux will have to be placed elsewhere. (grape)
1660 113 albert.wat 
assign  stb_pcx_pkt[`STB_PCX_FLSH] = stb_rdata_ramd[71] ;       // flush
1661 
assign  stb_pcx_pkt[`STB_PCX_FLSH-1] = 1'b0 ;
1662 95 fafa1971 
//assign  stb_pcx_pkt[`STB_PCX_WY_HI:`STB_PCX_WY_LO] = 2'b00 ;
1663 
 
1664 
//bug 2511
1665 113 albert.wat 
assign  stb_pcx_pkt[`STB_PCX_SZ_HI:`STB_PCX_SZ_LO] =
1666 95 fafa1971 
                        stb_rdata_ramd[69:68];                          // Size
1667 
 
1668 
//assign  stb_pcx_pkt[`STB_PCX_AD_HI:`STB_PCX_AD_LO] = stb_pcx_pkt[`STB_PCX_FLSH] ? 40'b0 :
1669 
//                        {stb_rdata_ramc[44:9],stb_rdata_ramd[67:64]} ;// Addr
1670 
 
1671 113 albert.wat 
assign  stb_pcx_pkt[`STB_PCX_AD_HI:`STB_PCX_AD_LO] =
1672 95 fafa1971 
                        {stb_rdata_ramc[44:9],stb_rdata_ramd[67:64]} ;// Addr
1673 
 
1674 
 
1675 113 albert.wat 
assign  stb_pcx_pkt[`STB_PCX_DA_HI:`STB_PCX_DA_LO] =
1676 95 fafa1971 
                        stb_rdata_ramd[63:0];                           // Data
1677 
 
1678 113 albert.wat 
assign  store_pcx_pkt[`STB_PCX_WIDTH-1:0] = stb_pcx_pkt[`STB_PCX_WIDTH-1:0] ;
1679 95 fafa1971 
 
1680 
// bld addr select.
1681 
wire [1:0] bld_addr_b54 ;
1682 
assign  bld_addr_b54[1:0] =
1683 113 albert.wat 
        lsu_bld_pcx_rq ? lsu_bld_rq_addr[1:0] : load_pcx_pkt[`LMQ_AD_LO+5:`LMQ_AD_LO+4] ;
1684 95 fafa1971 
 
1685 
// Select between load and store outbound pkt.
1686 
// *** cpu-id currently hardwired in pkt
1687 
// *** Thrd id currently hardwired.
1688 
mux4ds  #(124) pcx_pkt_src (
1689 113 albert.wat 
  .in0  ({load_pcx_pkt[`LMQ_VLD],2'b00,
1690 
    load_pcx_pkt[`LMQ_RQ_HI: `LMQ_RQ_LO],
1691 
    load_pcx_pkt[`LMQ_NC],const_cpuid[2:0],
1692 95 fafa1971 
    ld_pcx_thrd[1:0],lsu_pcx_ld_dtag_perror_w2,
1693 113 albert.wat 
    load_pcx_pkt[`LMQ_PREF],load_pcx_pkt[`LMQ_DFLUSH],
1694 
    load_pcx_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lsu_pcx_rq_sz_b3,
1695 95 fafa1971 
    //load_pcx_pkt[`LMQ_WY_HI:`LMQ_WY_LO],1'b0,
1696 
    //load_pcx_pkt[`LMQ_SZ_HI:0],cas_pkt2_data[63:0]}), // load
1697 113 albert.wat 
    load_pcx_pkt[`LMQ_SZ_HI:`LMQ_AD_LO+6], bld_addr_b54[1:0],
1698 
    load_pcx_pkt[`LMQ_AD_LO+3:`LMQ_AD_LO],cas_pkt2_data[63:0]}), // load
1699 
  .in1  ({store_pcx_pkt[`STB_PCX_VLD],1'b0,
1700 
  store_pcx_pkt[`STB_PCX_FLSH], // turn into interrupt request.
1701 
    store_pcx_pkt[`STB_PCX_RQ_HI:`STB_PCX_RQ_LO],
1702 
    store_pcx_pkt[`STB_PCX_NC], const_cpuid[2:0],
1703 
    store_pcx_pkt[`STB_PCX_TH_HI:`STB_PCX_TH_LO],
1704 95 fafa1971 
    1'b0,
1705 
    stb_rdata_ramd[70], // blk-st : Bug 3395
1706 
    stb_rdata_ramd[75],
1707 
    2'b00,
1708 
    //store_pcx_pkt[`STB_PCX_WY_HI:`STB_PCX_WY_LO],
1709 113 albert.wat 
    1'b0,store_pcx_pkt[`STB_PCX_SZ_HI:0]}),     // store
1710 
  .in2  (imiss_strm_pcx_pkt[`PCX_WIDTH-1:0]),   // alt src : imiss,stream.
1711 
  .in3  (fwd_int_fp_pcx_pkt[`PCX_WIDTH-1:0]),   // fwd, interrupt, fpop
1712 95 fafa1971 
  .sel0 (pcx_pkt_src_sel[0]),
1713 
  .sel1 (pcx_pkt_src_sel[1]),
1714 
  .sel2 (pcx_pkt_src_sel[2]),
1715 
  .sel3 (pcx_pkt_src_sel[3]),
1716 113 albert.wat 
  .dout (pcx_pkt_data[`PCX_WIDTH-1:0])
1717 95 fafa1971 
);
1718 
 
1719 113 albert.wat 
dff_s  #(124) pcx_xmit_ff (
1720 
        .din  (pcx_pkt_data[`PCX_WIDTH-1:0]),
1721 
        .q    (spc_pcx_data_pa[`PCX_WIDTH-1:0]),
1722 95 fafa1971 
        .clk  (clk),
1723 113 albert.wat 
        .se     (1'b0),     `SIMPLY_RISC_SCANIN,          .so ()
1724 95 fafa1971 
        );
1725 
 
1726 
//  Stage to avoid critical path
1727 
/*assign  lsu_ifu_ld_icache_index[11:5] = pcx_pkt_data[`PCX_AD_LO+11:`PCX_AD_LO+5] ;
1728 
assign  lsu_ifu_ld_pcxpkt_tid[1:0] = pcx_pkt_data[`PCX_TH_HI:`PCX_TH_LO] ;*/
1729 
 
1730 113 albert.wat 
dff_s  #(9) stg_icindx (
1731 
        .din  ({pcx_pkt_data[`PCX_AD_LO+11:`PCX_AD_LO+5],pcx_pkt_data[`PCX_TH_HI:`PCX_TH_LO]}),
1732 95 fafa1971 
        .q    ({lsu_ifu_ld_icache_index[11:5],lsu_ifu_ld_pcxpkt_tid[1:0]}),
1733 
        .clk  (clk),
1734 113 albert.wat 
        .se     (1'b0),     `SIMPLY_RISC_SCANIN,          .so ()
1735 95 fafa1971 
        );
1736 
 
1737 
//=========================================================================================
1738 
//  VA Watchpt Reg per thread
1739 
//=========================================================================================
1740 
 
1741 
//VA_watchpoint_thread0
1742 
   wire        va_wtchpt0_clk ;
1743 
   wire [47:3] va_wtchpt0_addr;
1744 
 
1745 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1746 
`else
1747 
clken_buf clkbf_va_wtchpt0 (
1748 
                .rclk   (clk),
1749 
                .enb_l  (lsu_va_wtchpt0_wr_en_l),
1750 
                .tmb_l  (~se),
1751 
                .clk    (va_wtchpt0_clk)
1752 
                ) ;
1753 
`endif
1754 95 fafa1971 
 
1755 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1756 
dffe_s #(45) va_wtchpt0_ff (
1757 95 fafa1971 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1758 
        .q      (va_wtchpt0_addr[47:3]),
1759 
        .en (~(lsu_va_wtchpt0_wr_en_l)), .clk(clk),
1760 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1761 95 fafa1971 
        );
1762 113 albert.wat 
`else
1763 
dff_s #(45) va_wtchpt0_ff (
1764 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1765 
        .q      (va_wtchpt0_addr[47:3]),
1766 
        .clk    (va_wtchpt0_clk),
1767 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1768 
        );
1769 
`endif
1770 95 fafa1971 
 
1771 
//VA_watchpoint_thread1
1772 
   wire        va_wtchpt1_clk ;
1773 
   wire [47:3] va_wtchpt1_addr;
1774 
 
1775 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1776 
`else
1777 
clken_buf clkbf_va_wtchpt1 (
1778 
                .rclk   (clk),
1779 
                .enb_l  (lsu_va_wtchpt1_wr_en_l),
1780 
                .tmb_l  (~se),
1781 
                .clk    (va_wtchpt1_clk)
1782 
                ) ;
1783 
`endif
1784 95 fafa1971 
 
1785 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1786 
dffe_s #(45) va_wtchpt1_ff (
1787 95 fafa1971 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1788 
        .q      (va_wtchpt1_addr[47:3]),
1789 
        .en (~(lsu_va_wtchpt1_wr_en_l)), .clk(clk),
1790 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1791 95 fafa1971 
        );
1792 113 albert.wat 
`else
1793 
dff_s #(45) va_wtchpt1_ff (
1794 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1795 
        .q      (va_wtchpt1_addr[47:3]),
1796 
        .clk    (va_wtchpt1_clk),
1797 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1798 
        );
1799 
`endif
1800 95 fafa1971 
 
1801 
//VA_watchpoint_thread2
1802 
   wire        va_wtchpt2_clk ;
1803 
   wire [47:3] va_wtchpt2_addr;
1804 
 
1805 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1806 
`else
1807 
clken_buf clkbf_va_wtchpt2 (
1808 
                .rclk   (clk),
1809 
                .enb_l  (lsu_va_wtchpt2_wr_en_l),
1810 
                .tmb_l  (~se),
1811 
                .clk    (va_wtchpt2_clk)
1812 
                ) ;
1813 
`endif
1814 95 fafa1971 
 
1815 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1816 
dffe_s #(45) va_wtchpt2_ff (
1817 95 fafa1971 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1818 
        .q      (va_wtchpt2_addr[47:3]),
1819 
        .en (~(lsu_va_wtchpt2_wr_en_l)), .clk(clk),
1820 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1821 95 fafa1971 
        );
1822 113 albert.wat 
`else
1823 
dff_s #(45) va_wtchpt2_ff (
1824 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1825 
        .q      (va_wtchpt2_addr[47:3]),
1826 
        .clk    (va_wtchpt2_clk),
1827 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1828 
        );
1829 
`endif
1830 95 fafa1971 
 
1831 
//VA_watchpoint_thread3
1832 
   wire        va_wtchpt3_clk ;
1833 
   wire [47:3] va_wtchpt3_addr;
1834 
 
1835 113 albert.wat 
`ifdef FPGA_SYN_CLK_EN
1836 
`else
1837 
clken_buf clkbf_va_wtchpt3 (
1838 
                .rclk   (clk),
1839 
                .enb_l  (lsu_va_wtchpt3_wr_en_l),
1840 
                .tmb_l  (~se),
1841 
                .clk    (va_wtchpt3_clk)
1842 
                ) ;
1843 
`endif
1844 95 fafa1971 
 
1845 113 albert.wat 
`ifdef FPGA_SYN_CLK_DFF
1846 
dffe_s #(45) va_wtchpt3_ff (
1847 95 fafa1971 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1848 
        .q      (va_wtchpt3_addr[47:3]),
1849 
        .en (~(lsu_va_wtchpt3_wr_en_l)), .clk(clk),
1850 113 albert.wat 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1851 95 fafa1971 
        );
1852 113 albert.wat 
`else
1853 
dff_s #(45) va_wtchpt3_ff (
1854 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1855 
        .q      (va_wtchpt3_addr[47:3]),
1856 
        .clk    (va_wtchpt3_clk),
1857 
        .se     (1'b0),       `SIMPLY_RISC_SCANIN,          .so ()
1858 
        );
1859 
`endif
1860 95 fafa1971 
 
1861 
   wire [47:3] va_wtchpt_addr;
1862 
 
1863 
mux4ds #(45)     va_wtchpt_mx_m (
1864 
        .in0    (va_wtchpt0_addr[47:3]),
1865 
        .in1    (va_wtchpt1_addr[47:3]),
1866 
        .in2    (va_wtchpt2_addr[47:3]),
1867 
        .in3    (va_wtchpt3_addr[47:3]),
1868 
        .sel0   (thread0_m),
1869 
        .sel1   (thread1_m),
1870 
        .sel2   (thread2_m),
1871 
        .sel3   (thread3_m),
1872 
        .dout   (va_wtchpt_addr[47:3])
1873 
        );
1874 
 
1875 
mux4ds #(45)     va_wtchpt_mx_g (
1876 
        .in0    (va_wtchpt0_addr[47:3]),
1877 
        .in1    (va_wtchpt1_addr[47:3]),
1878 
        .in2    (va_wtchpt2_addr[47:3]),
1879 
        .in3    (va_wtchpt3_addr[47:3]),
1880 
        .sel0   (thread0_g),
1881 
        .sel1   (thread1_g),
1882 
        .sel2   (thread2_g),
1883 
        .sel3   (thread3_g),
1884 
        .dout   (lsu_va_wtchpt_addr[47:3])
1885 
        );
1886 
 
1887 
//VA wtchpt comparison at M stage
1888 
//assign lsu_va_match_m = (lsu_ldst_va_m[47:3] == va_wtchpt_addr[47:3]);
1889 
//bug6480/eco6623
1890 
assign lsu_va_match_b47_b32_m = (lsu_ldst_va_m[47:32] == va_wtchpt_addr[47:32]);
1891 
assign lsu_va_match_b31_b3_m =  (lsu_ldst_va_m[31:3 ] == va_wtchpt_addr[31:3 ]);
1892 
 
1893 
//====================================================================
1894 
//dc_fill CP
1895 
   wire [63:0] l2fill_data_m;
1896 
 
1897 
//dff #(64) stgm_l2fd (
1898 
//        .din    (lsu_l2fill_data[63:0]),
1899 
//        .q      (l2fill_data_m[63:0]),
1900 
//        .clk    (clk),
1901 113 albert.wat 
//        .se     (se),       `SIMPLY_RISC_SCANIN,          .so ()
1902 95 fafa1971 
//        );
1903 
   assign      l2fill_data_m[63:0] = lsu_l2fill_data[63:0];
1904 
 
1905 
 
1906 
   wire [63:0] ld_byp_data_m;
1907 
 
1908 113 albert.wat 
`ifdef FPGA_SYN_1THREAD
1909 
  assign ld_byp_data_m[63:0] = lmq0_bypass_data[63:0];
1910 
`else
1911 95 fafa1971 
mux4ds  #(64) ld_byp_mx (
1912 
  .in0  (lmq0_bypass_data[63:0]),
1913 
  .in1  (lmq1_bypass_data[63:0]),
1914 
  .in2  (lmq2_bypass_data[63:0]),
1915 
  .in3  (lmq3_bypass_data[63:0]),
1916 
  .sel0 (ld_thrd_byp_sel_m[0]),
1917 
  .sel1 (ld_thrd_byp_sel_m[1]),
1918 
  .sel2 (ld_thrd_byp_sel_m[2]),
1919 
  .sel3 (ld_thrd_byp_sel_m[3]),
1920 
  .dout (ld_byp_data_m[63:0])
1921 
);
1922 113 albert.wat 
`endif
1923 95 fafa1971 
 
1924 
assign dcache_alt_data_w0_m[63:0] =
1925 
       l2fill_vld_m ? l2fill_data_m[63:0] :
1926 
                      ld_byp_data_m[63:0];
1927 
 
1928 
//assign        lsu_l2fill_or_byp_msb_m[7:0]
1929 
//      = {lsu_l2fill_or_byp_data_m[63],
1930 
//     lsu_l2fill_or_byp_data_m[55],
1931 
//     lsu_l2fill_or_byp_data_m[47],
1932 
//     lsu_l2fill_or_byp_data_m[39],
1933 
//         lsu_l2fill_or_byp_data_m[31],
1934 
//     lsu_l2fill_or_byp_data_m[23],
1935 
//     lsu_l2fill_or_byp_data_m[15],
1936 
//     lsu_l2fill_or_byp_data_m[07]} ;
1937 
//====================================================================
1938 
 
1939 
endmodule

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