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// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T1 Processor File: lsu_stb_ctldp.v
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================
`ifdef SIMPLY_RISC_TWEAKS
`define SIMPLY_RISC_SCANIN .si(0)
`else
`define SIMPLY_RISC_SCANIN .si()
`endif
//FPGA_SYN enables all FPGA related modifications
`ifdef FPGA_SYN
`define FPGA_SYN_CLK_EN
`define FPGA_SYN_CLK_DFF
`endif
 
module lsu_stb_ctldp (/*AUTOARG*/
   // Outputs
   so, stb_state_si_0, stb_state_si_1, stb_state_si_2,
   stb_state_si_3, stb_state_si_4, stb_state_si_5, stb_state_si_6,
   stb_state_si_7, stb_state_rtype_0, stb_state_rtype_1,
   stb_state_rtype_2, stb_state_rtype_3, stb_state_rtype_4,
   stb_state_rtype_5, stb_state_rtype_6, stb_state_rtype_7,
   stb_state_rmo,
   // Inputs
   rclk, si, se, stb_clk_en_l, lsu_stb_va_m, lsu_st_rq_type_m,
   lsu_st_rmo_m
   );
 
   input rclk;
   input si;
   input se;
//   input tmb_l;
 
   output so;
 
   input [7:0] stb_clk_en_l;
 
   input [7:6] lsu_stb_va_m;
   input [2:1] lsu_st_rq_type_m;
   input       lsu_st_rmo_m;
 
   output [3:2] stb_state_si_0;
   output [3:2] stb_state_si_1;
   output [3:2] stb_state_si_2;
   output [3:2] stb_state_si_3;
   output [3:2] stb_state_si_4;
   output [3:2] stb_state_si_5;
   output [3:2] stb_state_si_6;
   output [3:2] stb_state_si_7;
 
   output [2:1] stb_state_rtype_0;
   output [2:1] stb_state_rtype_1;
   output [2:1] stb_state_rtype_2;
   output [2:1] stb_state_rtype_3;
   output [2:1] stb_state_rtype_4;
   output [2:1] stb_state_rtype_5;
   output [2:1] stb_state_rtype_6;
   output [2:1] stb_state_rtype_7;
 
   output [7:0] stb_state_rmo;
 
 
   wire [7:0] stb_clk;
 
   wire       clk;
   assign     clk = rclk;
 
`ifdef FPGA_SYN_CLK_EN
`else
   clken_buf stb0_clkbuf (
                .rclk   (clk),
                .enb_l  (stb_clk_en_l[0]),
                .tmb_l  (~se),
                .clk    (stb_clk[0])
                ) ;
`endif
 
`ifdef FPGA_SYN_CLK_EN
`else
   clken_buf stb1_clkbuf (
                .rclk   (clk),
                .enb_l  (stb_clk_en_l[1]),
                .tmb_l  (~se),
                .clk    (stb_clk[1])
                ) ;
`endif
 
`ifdef FPGA_SYN_CLK_EN
`else
   clken_buf stb2_clkbuf (
                .rclk   (clk),
                .enb_l  (stb_clk_en_l[2]),
                .tmb_l  (~se),
                .clk    (stb_clk[2])
                ) ;
`endif
 
`ifdef FPGA_SYN_CLK_EN
`else
   clken_buf stb3_clkbuf (
                .rclk   (clk),
                .enb_l  (stb_clk_en_l[3]),
                .tmb_l  (~se),
                .clk    (stb_clk[3])
                ) ;
`endif
 
`ifdef FPGA_SYN_CLK_EN
`else
   clken_buf stb4_clkbuf (
                .rclk   (clk),
                .enb_l  (stb_clk_en_l[4]),
                .tmb_l  (~se),
                .clk    (stb_clk[4])
                ) ;
`endif
 
`ifdef FPGA_SYN_CLK_EN
`else
   clken_buf stb5_clkbuf (
                .rclk   (clk),
                .enb_l  (stb_clk_en_l[5]),
                .tmb_l  (~se),
                .clk    (stb_clk[5])
                ) ;
`endif
 
`ifdef FPGA_SYN_CLK_EN
`else
   clken_buf stb6_clkbuf (
                .rclk   (clk),
                .enb_l  (stb_clk_en_l[6]),
                .tmb_l  (~se),
                .clk    (stb_clk[6])
                ) ;
`endif
 
`ifdef FPGA_SYN_CLK_EN
`else
   clken_buf stb7_clkbuf (
                .rclk   (clk),
                .enb_l  (stb_clk_en_l[7]),
                .tmb_l  (~se),
                .clk    (stb_clk[7])
                ) ;
`endif
 
 
 
`ifdef FPGA_SYN_CLK_DFF
  dffe_s #(5)  ff_spec_write_0         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                      lsu_st_rmo_m}),
        .q      ({stb_state_si_0[3:2], stb_state_rtype_0[2:1],
                                       stb_state_rmo[0]}    ),
        .en (~(stb_clk_en_l[0])), .clk(clk),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`else
  dff_s #(5)  ff_spec_write_0         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                      lsu_st_rmo_m}),
        .q      ({stb_state_si_0[3:2], stb_state_rtype_0[2:1],
                                       stb_state_rmo[0]}    ),
        .clk    (stb_clk[0]),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`endif
 
`ifdef FPGA_SYN_CLK_DFF
  dffe_s #(5)  ff_spec_write_1         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                      lsu_st_rmo_m}),
        .q      ({stb_state_si_1[3:2], stb_state_rtype_1[2:1],
                                   stb_state_rmo[1]}    ),
        .en (~(stb_clk_en_l[1])), .clk(clk),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`else
  dff_s #(5)  ff_spec_write_1         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                      lsu_st_rmo_m}),
        .q      ({stb_state_si_1[3:2], stb_state_rtype_1[2:1],
                                   stb_state_rmo[1]}    ),
        .clk    (stb_clk[1]),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`endif
 
`ifdef FPGA_SYN_CLK_DFF
  dffe_s #(5)  ff_spec_write_2         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                    lsu_st_rmo_m}),
        .q      ({stb_state_si_2[3:2], stb_state_rtype_2[2:1],
                                   stb_state_rmo[2]}    ),
        .en (~(stb_clk_en_l[2])), .clk(clk),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`else
  dff_s #(5)  ff_spec_write_2         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                    lsu_st_rmo_m}),
        .q      ({stb_state_si_2[3:2], stb_state_rtype_2[2:1],
                                   stb_state_rmo[2]}    ),
        .clk    (stb_clk[2]),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`endif
`ifdef FPGA_SYN_CLK_DFF
  dffe_s #(5)  ff_spec_write_3         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                    lsu_st_rmo_m}),
        .q      ({stb_state_si_3[3:2], stb_state_rtype_3[2:1],
                                   stb_state_rmo[3]}    ),
        .en (~(stb_clk_en_l[3])), .clk(clk),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`else
  dff_s #(5)  ff_spec_write_3         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                    lsu_st_rmo_m}),
        .q      ({stb_state_si_3[3:2], stb_state_rtype_3[2:1],
                                   stb_state_rmo[3]}    ),
        .clk    (stb_clk[3]),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`endif
`ifdef FPGA_SYN_CLK_DFF
  dffe_s #(5)  ff_spec_write_4         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                    lsu_st_rmo_m}),
        .q      ({stb_state_si_4[3:2], stb_state_rtype_4[2:1],
                                   stb_state_rmo[4]}    ),
        .en (~(stb_clk_en_l[4])), .clk(clk),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`else
  dff_s #(5)  ff_spec_write_4         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                    lsu_st_rmo_m}),
        .q      ({stb_state_si_4[3:2], stb_state_rtype_4[2:1],
                                   stb_state_rmo[4]}    ),
        .clk    (stb_clk[4]),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`endif
`ifdef FPGA_SYN_CLK_DFF
  dffe_s #(5)  ff_spec_write_5         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                    lsu_st_rmo_m}),
        .q      ({stb_state_si_5[3:2], stb_state_rtype_5[2:1],
                                   stb_state_rmo[5]}    ),
        .en (~(stb_clk_en_l[5])), .clk(clk),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`else
  dff_s #(5)  ff_spec_write_5         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                    lsu_st_rmo_m}),
        .q      ({stb_state_si_5[3:2], stb_state_rtype_5[2:1],
                                   stb_state_rmo[5]}    ),
        .clk    (stb_clk[5]),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`endif
`ifdef FPGA_SYN_CLK_DFF
  dffe_s #(5)  ff_spec_write_6         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                    lsu_st_rmo_m}),
        .q      ({stb_state_si_6[3:2], stb_state_rtype_6[2:1],
                                   stb_state_rmo[6]}    ),
        .en (~(stb_clk_en_l[6])), .clk(clk),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`else
  dff_s #(5)  ff_spec_write_6         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                    lsu_st_rmo_m}),
        .q      ({stb_state_si_6[3:2], stb_state_rtype_6[2:1],
                                   stb_state_rmo[6]}    ),
        .clk    (stb_clk[6]),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`endif
 
`ifdef FPGA_SYN_CLK_DFF
  dffe_s #(5)  ff_spec_write_7         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                    lsu_st_rmo_m}),
        .q      ({stb_state_si_7[3:2], stb_state_rtype_7[2:1],
                             stb_state_rmo[7]}    ),
        .en (~(stb_clk_en_l[7])), .clk(clk),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`else
  dff_s #(5)  ff_spec_write_7         (
        .din    ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],
                                    lsu_st_rmo_m}),
        .q      ({stb_state_si_7[3:2], stb_state_rtype_7[2:1],
                             stb_state_rmo[7]}    ),
        .clk    (stb_clk[7]),
        .se     (se), `SIMPLY_RISC_SCANIN, .so ()
        );
`endif
 
 
endmodule // lsu_stb_ctldp

Line No.	Rev	Author	Line
1	95	fafa1971	`// ========== Copyright Header Begin ==========================================`
2			`//`
3			`// OpenSPARC T1 Processor File: lsu_stb_ctldp.v`
4			`// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.`
5			`// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.`
6			`//`
7			`// The above named program is free software; you can redistribute it and/or`
8			`// modify it under the terms of the GNU General Public`
9			`// License version 2 as published by the Free Software Foundation.`
10			`//`
11			`// The above named program is distributed in the hope that it will be`
12			`// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
14			`// General Public License for more details.`
15			`//`
16			`// You should have received a copy of the GNU General Public`
17			`// License along with this work; if not, write to the Free Software`
18			`// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.`
19			`//`
20			`// ========== Copyright Header End ============================================`
21	113	albert.wat	`ifdef SIMPLY_RISC_TWEAKS
22			`define SIMPLY_RISC_SCANIN .si(0)
23			`else
24			`define SIMPLY_RISC_SCANIN .si()
25			`endif
26	95	fafa1971	`//FPGA_SYN enables all FPGA related modifications`
27	113	albert.wat	`ifdef FPGA_SYN
28			`define FPGA_SYN_CLK_EN
29			`define FPGA_SYN_CLK_DFF
30			`endif
31	95	fafa1971
32			`module lsu_stb_ctldp (/AUTOARG/`
33			`// Outputs`
34			`so, stb_state_si_0, stb_state_si_1, stb_state_si_2,`
35			`stb_state_si_3, stb_state_si_4, stb_state_si_5, stb_state_si_6,`
36			`stb_state_si_7, stb_state_rtype_0, stb_state_rtype_1,`
37			`stb_state_rtype_2, stb_state_rtype_3, stb_state_rtype_4,`
38			`stb_state_rtype_5, stb_state_rtype_6, stb_state_rtype_7,`
39			`stb_state_rmo,`
40			`// Inputs`
41			`rclk, si, se, stb_clk_en_l, lsu_stb_va_m, lsu_st_rq_type_m,`
42			`lsu_st_rmo_m`
43			`);`
44
45			`input rclk;`
46			`input si;`
47			`input se;`
48			`// input tmb_l;`
49
50			`output so;`
51
52			`input [7:0] stb_clk_en_l;`
53
54			`input [7:6] lsu_stb_va_m;`
55			`input [2:1] lsu_st_rq_type_m;`
56			`input lsu_st_rmo_m;`
57
58			`output [3:2] stb_state_si_0;`
59			`output [3:2] stb_state_si_1;`
60			`output [3:2] stb_state_si_2;`
61			`output [3:2] stb_state_si_3;`
62			`output [3:2] stb_state_si_4;`
63			`output [3:2] stb_state_si_5;`
64			`output [3:2] stb_state_si_6;`
65			`output [3:2] stb_state_si_7;`
66
67			`output [2:1] stb_state_rtype_0;`
68			`output [2:1] stb_state_rtype_1;`
69			`output [2:1] stb_state_rtype_2;`
70			`output [2:1] stb_state_rtype_3;`
71			`output [2:1] stb_state_rtype_4;`
72			`output [2:1] stb_state_rtype_5;`
73			`output [2:1] stb_state_rtype_6;`
74			`output [2:1] stb_state_rtype_7;`
75
76			`output [7:0] stb_state_rmo;`
77
78
79			`wire [7:0] stb_clk;`
80
81			`wire clk;`
82			`assign clk = rclk;`
83
84	113	albert.wat	`ifdef FPGA_SYN_CLK_EN
85			`else
86			`clken_buf stb0_clkbuf (`
87			`.rclk (clk),`
88			`.enb_l (stb_clk_en_l[0]),`
89			`.tmb_l (~se),`
90			`.clk (stb_clk[0])`
91			`) ;`
92			`endif
93	95	fafa1971
94	113	albert.wat	`ifdef FPGA_SYN_CLK_EN
95			`else
96			`clken_buf stb1_clkbuf (`
97			`.rclk (clk),`
98			`.enb_l (stb_clk_en_l[1]),`
99			`.tmb_l (~se),`
100			`.clk (stb_clk[1])`
101			`) ;`
102			`endif
103	95	fafa1971
104	113	albert.wat	`ifdef FPGA_SYN_CLK_EN
105			`else
106			`clken_buf stb2_clkbuf (`
107			`.rclk (clk),`
108			`.enb_l (stb_clk_en_l[2]),`
109			`.tmb_l (~se),`
110			`.clk (stb_clk[2])`
111			`) ;`
112			`endif
113	95	fafa1971
114	113	albert.wat	`ifdef FPGA_SYN_CLK_EN
115			`else
116			`clken_buf stb3_clkbuf (`
117			`.rclk (clk),`
118			`.enb_l (stb_clk_en_l[3]),`
119			`.tmb_l (~se),`
120			`.clk (stb_clk[3])`
121			`) ;`
122			`endif
123	95	fafa1971
124	113	albert.wat	`ifdef FPGA_SYN_CLK_EN
125			`else
126			`clken_buf stb4_clkbuf (`
127			`.rclk (clk),`
128			`.enb_l (stb_clk_en_l[4]),`
129			`.tmb_l (~se),`
130			`.clk (stb_clk[4])`
131			`) ;`
132			`endif
133	95	fafa1971
134	113	albert.wat	`ifdef FPGA_SYN_CLK_EN
135			`else
136			`clken_buf stb5_clkbuf (`
137			`.rclk (clk),`
138			`.enb_l (stb_clk_en_l[5]),`
139			`.tmb_l (~se),`
140			`.clk (stb_clk[5])`
141			`) ;`
142			`endif
143	95	fafa1971
144	113	albert.wat	`ifdef FPGA_SYN_CLK_EN
145			`else
146			`clken_buf stb6_clkbuf (`
147			`.rclk (clk),`
148			`.enb_l (stb_clk_en_l[6]),`
149			`.tmb_l (~se),`
150			`.clk (stb_clk[6])`
151			`) ;`
152			`endif
153	95	fafa1971
154	113	albert.wat	`ifdef FPGA_SYN_CLK_EN
155			`else
156			`clken_buf stb7_clkbuf (`
157			`.rclk (clk),`
158			`.enb_l (stb_clk_en_l[7]),`
159			`.tmb_l (~se),`
160			`.clk (stb_clk[7])`
161			`) ;`
162			`endif
163	95	fafa1971
164
165
166	113	albert.wat	`ifdef FPGA_SYN_CLK_DFF
167			`dffe_s #(5) ff_spec_write_0 (`
168	95	fafa1971	`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
169			`lsu_st_rmo_m}),`
170			`.q ({stb_state_si_0[3:2], stb_state_rtype_0[2:1],`
171			`stb_state_rmo[0]} ),`
172			`.en (~(stb_clk_en_l[0])), .clk(clk),`
173	113	albert.wat	.se (se), `SIMPLY_RISC_SCANIN, .so ()
174	95	fafa1971	`);`
175	113	albert.wat	`else
176			`dff_s #(5) ff_spec_write_0 (`
177			`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
178			`lsu_st_rmo_m}),`
179			`.q ({stb_state_si_0[3:2], stb_state_rtype_0[2:1],`
180			`stb_state_rmo[0]} ),`
181			`.clk (stb_clk[0]),`
182			.se (se), `SIMPLY_RISC_SCANIN, .so ()
183			`);`
184			`endif
185	95	fafa1971
186	113	albert.wat	`ifdef FPGA_SYN_CLK_DFF
187			`dffe_s #(5) ff_spec_write_1 (`
188	95	fafa1971	`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
189			`lsu_st_rmo_m}),`
190			`.q ({stb_state_si_1[3:2], stb_state_rtype_1[2:1],`
191			`stb_state_rmo[1]} ),`
192			`.en (~(stb_clk_en_l[1])), .clk(clk),`
193	113	albert.wat	.se (se), `SIMPLY_RISC_SCANIN, .so ()
194	95	fafa1971	`);`
195	113	albert.wat	`else
196			`dff_s #(5) ff_spec_write_1 (`
197			`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
198			`lsu_st_rmo_m}),`
199			`.q ({stb_state_si_1[3:2], stb_state_rtype_1[2:1],`
200			`stb_state_rmo[1]} ),`
201			`.clk (stb_clk[1]),`
202			.se (se), `SIMPLY_RISC_SCANIN, .so ()
203			`);`
204			`endif
205	95	fafa1971
206	113	albert.wat	`ifdef FPGA_SYN_CLK_DFF
207			`dffe_s #(5) ff_spec_write_2 (`
208	95	fafa1971	`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
209			`lsu_st_rmo_m}),`
210			`.q ({stb_state_si_2[3:2], stb_state_rtype_2[2:1],`
211			`stb_state_rmo[2]} ),`
212			`.en (~(stb_clk_en_l[2])), .clk(clk),`
213	113	albert.wat	.se (se), `SIMPLY_RISC_SCANIN, .so ()
214	95	fafa1971	`);`
215	113	albert.wat	`else
216			`dff_s #(5) ff_spec_write_2 (`
217	95	fafa1971	`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
218			`lsu_st_rmo_m}),`
219	113	albert.wat	`.q ({stb_state_si_2[3:2], stb_state_rtype_2[2:1],`
220			`stb_state_rmo[2]} ),`
221			`.clk (stb_clk[2]),`
222			.se (se), `SIMPLY_RISC_SCANIN, .so ()
223			`);`
224			`endif
225			`ifdef FPGA_SYN_CLK_DFF
226			`dffe_s #(5) ff_spec_write_3 (`
227			`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
228			`lsu_st_rmo_m}),`
229	95	fafa1971	`.q ({stb_state_si_3[3:2], stb_state_rtype_3[2:1],`
230			`stb_state_rmo[3]} ),`
231			`.en (~(stb_clk_en_l[3])), .clk(clk),`
232	113	albert.wat	.se (se), `SIMPLY_RISC_SCANIN, .so ()
233	95	fafa1971	`);`
234	113	albert.wat	`else
235			`dff_s #(5) ff_spec_write_3 (`
236	95	fafa1971	`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
237			`lsu_st_rmo_m}),`
238	113	albert.wat	`.q ({stb_state_si_3[3:2], stb_state_rtype_3[2:1],`
239			`stb_state_rmo[3]} ),`
240			`.clk (stb_clk[3]),`
241			.se (se), `SIMPLY_RISC_SCANIN, .so ()
242			`);`
243			`endif
244			`ifdef FPGA_SYN_CLK_DFF
245			`dffe_s #(5) ff_spec_write_4 (`
246			`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
247			`lsu_st_rmo_m}),`
248	95	fafa1971	`.q ({stb_state_si_4[3:2], stb_state_rtype_4[2:1],`
249			`stb_state_rmo[4]} ),`
250			`.en (~(stb_clk_en_l[4])), .clk(clk),`
251	113	albert.wat	.se (se), `SIMPLY_RISC_SCANIN, .so ()
252	95	fafa1971	`);`
253	113	albert.wat	`else
254			`dff_s #(5) ff_spec_write_4 (`
255	95	fafa1971	`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
256			`lsu_st_rmo_m}),`
257	113	albert.wat	`.q ({stb_state_si_4[3:2], stb_state_rtype_4[2:1],`
258			`stb_state_rmo[4]} ),`
259			`.clk (stb_clk[4]),`
260			.se (se), `SIMPLY_RISC_SCANIN, .so ()
261			`);`
262			`endif
263			`ifdef FPGA_SYN_CLK_DFF
264			`dffe_s #(5) ff_spec_write_5 (`
265			`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
266			`lsu_st_rmo_m}),`
267	95	fafa1971	`.q ({stb_state_si_5[3:2], stb_state_rtype_5[2:1],`
268			`stb_state_rmo[5]} ),`
269			`.en (~(stb_clk_en_l[5])), .clk(clk),`
270	113	albert.wat	.se (se), `SIMPLY_RISC_SCANIN, .so ()
271	95	fafa1971	`);`
272	113	albert.wat	`else
273			`dff_s #(5) ff_spec_write_5 (`
274	95	fafa1971	`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
275			`lsu_st_rmo_m}),`
276	113	albert.wat	`.q ({stb_state_si_5[3:2], stb_state_rtype_5[2:1],`
277			`stb_state_rmo[5]} ),`
278			`.clk (stb_clk[5]),`
279			.se (se), `SIMPLY_RISC_SCANIN, .so ()
280			`);`
281			`endif
282			`ifdef FPGA_SYN_CLK_DFF
283			`dffe_s #(5) ff_spec_write_6 (`
284			`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
285			`lsu_st_rmo_m}),`
286	95	fafa1971	`.q ({stb_state_si_6[3:2], stb_state_rtype_6[2:1],`
287			`stb_state_rmo[6]} ),`
288			`.en (~(stb_clk_en_l[6])), .clk(clk),`
289	113	albert.wat	.se (se), `SIMPLY_RISC_SCANIN, .so ()
290	95	fafa1971	`);`
291	113	albert.wat	`else
292			`dff_s #(5) ff_spec_write_6 (`
293			`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
294			`lsu_st_rmo_m}),`
295			`.q ({stb_state_si_6[3:2], stb_state_rtype_6[2:1],`
296			`stb_state_rmo[6]} ),`
297			`.clk (stb_clk[6]),`
298			.se (se), `SIMPLY_RISC_SCANIN, .so ()
299			`);`
300			`endif
301	95	fafa1971
302	113	albert.wat	`ifdef FPGA_SYN_CLK_DFF
303			`dffe_s #(5) ff_spec_write_7 (`
304	95	fafa1971	`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
305			`lsu_st_rmo_m}),`
306			`.q ({stb_state_si_7[3:2], stb_state_rtype_7[2:1],`
307			`stb_state_rmo[7]} ),`
308			`.en (~(stb_clk_en_l[7])), .clk(clk),`
309	113	albert.wat	.se (se), `SIMPLY_RISC_SCANIN, .so ()
310	95	fafa1971	`);`
311	113	albert.wat	`else
312			`dff_s #(5) ff_spec_write_7 (`
313			`.din ({lsu_stb_va_m[7:6], lsu_st_rq_type_m[2:1],`
314			`lsu_st_rmo_m}),`
315			`.q ({stb_state_si_7[3:2], stb_state_rtype_7[2:1],`
316			`stb_state_rmo[7]} ),`
317			`.clk (stb_clk[7]),`
318			.se (se), `SIMPLY_RISC_SCANIN, .so ()
319			`);`
320			`endif
321	95	fafa1971
322
323			`endmodule // lsu_stb_ctldp`

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