Subversion Repositories s1_core

// ========== Copyright Header Begin ==========================================

// 

// OpenSPARC T1 Processor File: mul64.v

// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

// 

// The above named program is free software; you can redistribute it and/or

// modify it under the terms of the GNU General Public

// License version 2 as published by the Free Software Foundation.

// 

// The above named program is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

// General Public License for more details.

// 

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// ========== Copyright Header End ============================================

/*//////////////////////////////////////////////////////////////////////

//

//  Module Name: mul64

//  Description:        *This block implements the multiplier used in the modular multiplier

//                       unit (MUL) and be shared by sparc EXU and the streaming unit (SPU).

//                       It is also used as the 54x54 multiplier in the FPU.

//                      *It takes two 64-bit unsign data and accumulated operand and do the

//                       64x64 MAC operation at two cycle thruput and 5 cycle latency.

//                      *The mul_valid signal indicate the beginning of a new operation.

//                       It MUST be dis-asserted at the next cycle to have the proper 2-cycle

//                       latency operation in the csa array. If there are two back-to-back

//                       cycle operation, the first operation result will be incorrect.

//                      *Results are avaliable on the 5th cycle of the mul_valid as shows

//

//                      *Following inputs should tie to "0" when used as a 64x64 multiplier

//                       - areg

//                       - accreg

//                       - x2

//

//                         Cycle-0  | Cycle-1 | Cycle-2 | Cycle-3 | Cycle-4 | Cycle-5

//                       1st        *         |         |         |         |

//                       rs1, rs2   ^         |         |         |         | 1st results

//                       valid=1    | valid=0 |         *         |         | avaliable

//                                1st         | 2nd OP  ^         |         |

//                                setup       | valid=1 |         |         |

//                                            |        2nd        |         |

//                                            |       setup       |         |

//

*/

//FPGA_SYN enables all FPGA related modifications

`ifdef FPGA_SYN

`define FPGA_SYN_MUL

`endif

`ifdef FPGA_SYN_MUL

module mul64(rs1_l, rs2, valid, areg, accreg, x2, out, rclk, si, so, se,

        mul_rst_l, mul_step);

        input   [63:0]           rs1_l;

        input   [63:0]           rs2;

        input                   valid;

        input   [96:0]           areg;

        input   [135:129]       accreg;

        input                   x2;

        input                   rclk;

        input                   si;

        input                   se;

        input                   mul_rst_l;

        input                   mul_step;

        output                  so;

        output  [135:0]          out;

reg [135:0] myout, myout_a1, myout_a2, myout_a3;

reg [63:0] rs1_ff;

reg [64:0] rs2_ff;

reg [63:0] par1, par2;

reg [64:0] par3, par4;

reg [5:0] state;

always @(posedge rclk)

  state <= {valid,state[5:1]};

always @(posedge rclk) begin

  if(mul_step) begin

    if(valid) begin

      rs1_ff <= ~rs1_l;

      rs2_ff <= x2 ? {rs2,1'b0} : {1'b0,rs2};

    end else begin

      rs1_ff <= {32'b0, rs1_ff[63:32]};

    end

    par1 <= (rs1_ff[31:0] * rs2_ff[31:0]);

    par3 <= rs1_ff[31:0] * rs2_ff[64:32];

    myout_a1 <= ({32'b0, myout_a1[135:32]} & {136{state[3]}}) + par1 + {par3, 32'b0} + areg;

    myout <= {(myout_a1[103:97]+accreg),myout_a1[96:0],myout[63:32]};

  end

end

assign out = myout;

assign so = 1'b0;

endmodule

`else

module mul64 (rs1_l, rs2, valid, areg, accreg, x2, out, rclk, si, so, se, mul_rst_l, mul_step);

input  [63:0]    rs1_l;                  // op1

input  [63:0]    rs2;                    // op2

input           valid;                  // begin of the MUL operation

input  [96:0]    areg;                   // accumulated input for ACCUM

input  [135:129] accreg;                // direct input from ACCUM [135:129]

input           x2;                     // for op1*op2*2

input           rclk, si, se, mul_rst_l, mul_step;

output          so;

output [135:0]   out;

wire            cyc1, cyc2, cyc3;       // cycle stage of MUL

wire [2:0]       b0, b1, b2,  b3,  b4,  b5,  b6,  b7;

wire [2:0]       b8, b9, b10, b11, b12, b13, b14, b15;

wire            b16;

wire [63:0]      op1_l, op1;

wire [81:0]      a0sum, a1sum, a0s, a1s;

wire [81:4]     a0cout, a1cout, a0c, a1c;

wire            pcoutx2, psumx2;

wire            x2_c1, x2_c2, x2_c3, x2_c2c3;

wire [98:0]      psum, pcout;

wire [98:30]    pcout_in, pc;

wire [98:31]    psum_in, ps;

wire [96:0]      ary2_cout, addin_cout;

wire [97:0]      ary2_sum,  addin_sum ;

wire            add_cin, addin_cin, add_co31, add_co96;

wire [103:0]     addout;

wire            clk_enb0, clk_enb1;

wire            rst;

wire            clk;

wire            tm_l;

  assign clk = rclk;

  assign rst = ~mul_rst_l;

  assign tm_l = ~se;

  clken_buf     ckbuf_0(.clk(clk_enb0), .rclk(clk), .enb_l(~mul_step), .tmb_l(tm_l));

  /////////////////////////////////////////////////////////////////////

  //    States count

  /////////////////////////////////////////////////////////////////////

  dffr_s  cyc1_dff(.din(valid), .clk(clk_enb0), .q(cyc1), .rst(rst), .se(se), .si(), .so());

  dffr_s  cyc2_dff(.din(cyc1),  .clk(clk_enb0), .q(cyc2), .rst(rst), .se(se), .si(), .so());

  dffr_s  cyc3_dff(.din(cyc2),  .clk(clk_enb0), .q(cyc3), .rst(rst), .se(se), .si(), .so());

  dffr_s  x2c1_dff(.din(x2),    .clk(clk_enb0), .q(x2_c1), .rst(rst), .se(se), .si(), .so());

  dffr_s  x2c2_dff(.din(x2_c1), .clk(clk_enb0), .q(x2_c2), .rst(rst), .se(se), .si(), .so());

  dffr_s  x2c3_dff(.din(x2_c2), .clk(clk_enb0), .q(x2_c3), .rst(rst), .se(se), .si(), .so());

  assign x2_c2c3 =  x2_c2 | x2_c3 ;

  /////////////////////////////////////////////////////////////////////

  //    Enable flops for op1

  /////////////////////////////////////////////////////////////////////

  clken_buf     ckbuf_1(.clk(clk_enb1), .rclk(clk), .enb_l(~(valid & mul_step)), .tmb_l(tm_l));

  dff_s #(64)   ffrs1  (.din(rs1_l[63:0]), .clk(clk_enb1), .q(op1_l[63:0]),

                        .se(se), .si(), .so());

  assign op1[63:0] = ~op1_l[63:0];

  mul_booth      booth (.head (valid),

                        .b_in (rs2),

                        .b0   (b0),

                        .b1   (b1),

                        .b2   (b2),

                        .b3   (b3),

                        .b4   (b4),

                        .b5   (b5),

                        .b6   (b6),

                        .b7   (b7),

                        .b8   (b8),

                        .b9   (b9),

                        .b10  (b10),

                        .b11  (b11),

                        .b12  (b12),

                        .b13  (b13),

                        .b14  (b14),

                        .b15  (b15),

                        .b16  (b16),

                        .clk  (clk), .se(se), .si(), .so(), .mul_step(mul_step), .tm_l(tm_l));

  /////////////////////////////////////////////////////////////////////

  //    Two Array1 inst ary1_a0 & ary1_a1 with the ouput flops 

  /////////////////////////////////////////////////////////////////////

  mul_array1    ary1_a0(.cout (a0cout[81:4]),

                        .sum  (a0sum[81:0]),

                        .a    (op1),

                        .b0   (b0),

                        .b1   (b1),

                        .b2   (b2),

                        .b3   (b3),

                        .b4   (b4),

                        .b5   (b5),

                        .b6   (b6),

                        .b7   (b7),

                        .b8   (3'b000),

                        .head (cyc1),

                        .bot  (1'b0)); //array a is never at the bottom of 33-pp rows

  dff_s #(78)  a0cot_dff (.din(a0cout[81:4]), .clk(clk_enb0), .q(a0c[81:4]),

                        .se(se), .si(), .so());

  dff_s #(82)  a0sum_dff (.din(a0sum[81:0]), .clk(clk_enb0), .q(a0s[81:0]),

                        .se(se), .si(), .so());

  mul_array1    ary1_a1(.cout (a1cout[81:4]),

                        .sum  (a1sum[81:0]),

                        .a    (op1),

                        .b0   (b8),

                        .b1   (b9),

                        .b2   (b10),

                        .b3   (b11),

                        .b4   (b12),

                        .b5   (b13),

                        .b6   (b14),

                        .b7   (b15),

                        .b8   ({1'b0,b16,1'b0}),

                        .head (1'b0),   //array b is never at the head of 33-pp rows

                        .bot  (cyc2));

  dff_s #(78)  a1cot_dff (.din(a1cout[81:4]), .clk(clk_enb0), .q(a1c[81:4]),

                        .se(se), .si(), .so());

  dff_s #(82)  a1sum_dff (.din(a1sum[81:0]), .clk(clk_enb0), .q(a1s[81:0]),

                        .se(se), .si(), .so());

  /////////////////////////////////////////////////////////////////////

  //    Array2 with the reorder output mux-flops

  /////////////////////////////////////////////////////////////////////

  mul_array2     array2(.pcoutx2 (pcoutx2),

                        .psumx2  (psumx2),

                        .pcout   (pcout[98:0]),

                        .psum    (psum[98:0]),

                        .a0c     (a0c[81:4]),

                        .a0s     (a0s[81:0]),

                        .a1c     (a1c[81:4]),

                        .a1s     (a1s[81:0]),

                        .pc      (pc[98:30]),

                        .ps      (ps[98:31]),

                        .areg    (areg[96:0]),

                        .bot     (cyc3),

                        .x2      (x2_c2c3));

  //// Outpput re-order muxes and flops ////

  dp_mux2es #(97)  ary2_cmux (.dout(ary2_cout[96:0]),

                              .in0(pcout[96:0]),

                              .in1({pcout[95:0],pcoutx2}),

                              .sel(x2_c2c3));

  dff_s #(97)  a2cot_dff (.din(ary2_cout[96:0]), .clk(clk_enb0), .q(addin_cout[96:0]),

                        .se(se), .si(), .so());

  dp_mux2es #(98) ary2_smux (.dout(ary2_sum[97:0]),

                             .in0(psum[97:0]),

                             .in1({psum[96:0],psumx2}),

                             .sel(x2_c2c3));

  dff_s #(98)  a2sum_dff (.din(ary2_sum[97:0]), .clk(clk_enb0), .q(addin_sum[97:0]),

                        .se(se), .si(), .so());

  //// Pseudo sum & cout logic and flops ////

  assign psum_in[98:32]  = psum[98:32] & {67{cyc2}} ;

  assign psum_in[31]     = psum[31] & x2_c2 ;

  assign pcout_in[98:31] = pcout[98:31] & {68{cyc2}} ;

  assign pcout_in[30]    = pcout[30] & x2_c2 ;

  dff_s #(68)  psum_dff  (.din(psum_in[98:31]), .clk(clk_enb0), .q(ps[98:31]),

                        .se(se), .si(), .so());

  dff_s #(69)  pcout_dff (.din(pcout_in[98:30]), .clk(clk_enb0), .q(pc[98:30]),

                        .se(se), .si(), .so());

  /////////////////////////////////////////////////////////////////////

  //    Adder (104-bit) 

  /////////////////////////////////////////////////////////////////////

  assign        add_cin = add_co31 & cyc3 ;

  assign {add_co31,addout[31:0]} =   {{1'b0},addin_sum[31:0]}

                                   + {{1'b0},addin_cout[30:0],addin_cin} ;

  assign {add_co96,addout[96:32]} =  addin_sum[97:32]

                                  + addin_cout[96:31]

                                  + {{65'b0},add_co31} ;

  assign        addout[103:97] =  accreg[135:129] + {{6'b0},add_co96} ;

  /////////////////////////////////////////////////////////////////////

  //    Pipe adder outputs  

  /////////////////////////////////////////////////////////////////////

  dff_s               co31_dff (.din(add_cin), .clk(clk_enb0), .q(addin_cin),

                        .se(se), .si(), .so());

  dff_s #(104)   out_dff (.din(addout[103:0]), .clk(clk_enb0), .q(out[135:32]),

                        .se(se), .si(), .so());

  dff_s #(32)    pip_dff (.din(out[63:32]), .clk(clk_enb0), .q(out[31:0]),

                        .se(se), .si(), .so());

endmodule // mul64

////////////////////////////////////////////////////////////////////////

//      Sub-moudle for mul64

////////////////////////////////////////////////////////////////////////

module mul_array1 ( cout, sum, a, b0, b1, b2, b3, b4, b5, b6, b7, b8,

     bot, head );

input  bot, head;

output [81:4]  cout;

output [81:0]  sum;

input [2:0]  b6;

input [2:0]  b3;

input [2:0]  b8;

input [2:0]  b2;

input [2:0]  b1;

input [2:0]  b7;

input [63:0]  a;

input [2:0]  b0;

input [2:0]  b4;

input [2:0]  b5;

// Buses in the design

wire  [1:0]  b5n;

wire  [1:0]  b2n;

wire  [68:1]  c0;

wire  [69:0]  s1;

wire  [68:1]  c1;

wire  [69:0]  s2;

wire  [68:1]  c2;

wire  [70:4]  s_1;

wire  [69:2]  s0;

wire  [76:10]  s_2;

wire  [70:2]  c_1;

wire  [76:10]  c_2;

wire  [75:11]  co;

mul_negen p1n ( .b(b5[2:0]), .n1(b5n[1]), .n0(b5n[0]));

mul_negen p0n ( .b(b2[2:0]), .n1(b2n[1]), .n0(b2n[0]));

mul_csa42  sc3_71_ ( .c(s_2[71]), .cin(co[70]), .a(c_1[70]),

     .b(c_2[70]), .cout(co[71]), .sum(sum[71]), .d(s1[65]),

     .carry(cout[71]));

mul_csa42  sc3_75_ ( .c(s_2[75]), .cin(co[74]), .a(1'b0),

     .b(c_2[74]), .cout(co[75]), .sum(sum[75]), .d(s1[69]),

     .carry(cout[75]));

mul_csa42  sc3_74_ ( .c(s_2[74]), .cin(co[73]), .a(1'b0),

     .b(c_2[73]), .cout(co[74]), .sum(sum[74]), .d(s1[68]),

     .carry(cout[74]));

mul_csa42  sc3_73_ ( .c(s_2[73]), .cin(co[72]), .a(1'b0),

     .b(c_2[72]), .cout(co[73]), .sum(sum[73]), .d(s1[67]),

     .carry(cout[73]));

mul_csa42  sc3_72_ ( .c(s_2[72]), .cin(co[71]), .a(1'b0),

     .b(c_2[71]), .cout(co[72]), .sum(sum[72]), .d(s1[66]),

     .carry(cout[72]));

mul_csa42  sc3_76_ ( .c(s_2[76]), .cin(co[75]), .a(1'b0),

     .b(c_2[75]), .cout(), .sum(sum[76]), .d(1'b0),

     .carry(cout[76]));

mul_csa42  sc3_70_ ( .c(s_2[70]), .cin(co[69]), .a(c_1[69]),

     .b(c_2[69]), .cout(co[70]), .sum(sum[70]), .d(s_1[70]),

     .carry(cout[70]));

mul_csa42  sc3_69_ ( .c(s_2[69]), .cin(co[68]), .a(c_1[68]),

     .b(c_2[68]), .cout(co[69]), .sum(sum[69]), .d(s_1[69]),

     .carry(cout[69]));

mul_csa42  sc3_68_ ( .c(s_2[68]), .cin(co[67]), .a(c_1[67]),

     .b(c_2[67]), .cout(co[68]), .sum(sum[68]), .d(s_1[68]),

     .carry(cout[68]));

mul_csa42  sc3_67_ ( .c(s_2[67]), .cin(co[66]), .a(c_1[66]),

     .b(c_2[66]), .cout(co[67]), .sum(sum[67]), .d(s_1[67]),

     .carry(cout[67]));

mul_csa42  sc3_66_ ( .c(s_2[66]), .cin(co[65]), .a(c_1[65]),

     .b(c_2[65]), .cout(co[66]), .sum(sum[66]), .d(s_1[66]),

     .carry(cout[66]));

mul_csa42  sc3_65_ ( .c(s_2[65]), .cin(co[64]), .a(c_1[64]),

     .b(c_2[64]), .cout(co[65]), .sum(sum[65]), .d(s_1[65]),

     .carry(cout[65]));

mul_csa42  sc3_64_ ( .c(s_2[64]), .cin(co[63]), .a(c_1[63]),

     .b(c_2[63]), .cout(co[64]), .sum(sum[64]), .d(s_1[64]),

     .carry(cout[64]));

mul_csa42  sc3_63_ ( .c(s_2[63]), .cin(co[62]), .a(c_1[62]),

     .b(c_2[62]), .cout(co[63]), .sum(sum[63]), .d(s_1[63]),

     .carry(cout[63]));

mul_csa42  sc3_62_ ( .c(s_2[62]), .cin(co[61]), .a(c_1[61]),

     .b(c_2[61]), .cout(co[62]), .sum(sum[62]), .d(s_1[62]),

     .carry(cout[62]));

mul_csa42  sc3_61_ ( .c(s_2[61]), .cin(co[60]), .a(c_1[60]),

     .b(c_2[60]), .cout(co[61]), .sum(sum[61]), .d(s_1[61]),

     .carry(cout[61]));

mul_csa42  sc3_60_ ( .c(s_2[60]), .cin(co[59]), .a(c_1[59]),

     .b(c_2[59]), .cout(co[60]), .sum(sum[60]), .d(s_1[60]),

     .carry(cout[60]));

mul_csa42  sc3_59_ ( .c(s_2[59]), .cin(co[58]), .a(c_1[58]),

     .b(c_2[58]), .cout(co[59]), .sum(sum[59]), .d(s_1[59]),

     .carry(cout[59]));

mul_csa42  sc3_58_ ( .c(s_2[58]), .cin(co[57]), .a(c_1[57]),

     .b(c_2[57]), .cout(co[58]), .sum(sum[58]), .d(s_1[58]),

     .carry(cout[58]));

mul_csa42  sc3_57_ ( .c(s_2[57]), .cin(co[56]), .a(c_1[56]),

     .b(c_2[56]), .cout(co[57]), .sum(sum[57]), .d(s_1[57]),

     .carry(cout[57]));

mul_csa42  sc3_56_ ( .c(s_2[56]), .cin(co[55]), .a(c_1[55]),

     .b(c_2[55]), .cout(co[56]), .sum(sum[56]), .d(s_1[56]),

     .carry(cout[56]));

mul_csa42  sc3_55_ ( .c(s_2[55]), .cin(co[54]), .a(c_1[54]),

     .b(c_2[54]), .cout(co[55]), .sum(sum[55]), .d(s_1[55]),

     .carry(cout[55]));

mul_csa42  sc3_54_ ( .c(s_2[54]), .cin(co[53]), .a(c_1[53]),

     .b(c_2[53]), .cout(co[54]), .sum(sum[54]), .d(s_1[54]),

     .carry(cout[54]));

mul_csa42  sc3_53_ ( .c(s_2[53]), .cin(co[52]), .a(c_1[52]),

     .b(c_2[52]), .cout(co[53]), .sum(sum[53]), .d(s_1[53]),

     .carry(cout[53]));

mul_csa42  sc3_52_ ( .c(s_2[52]), .cin(co[51]), .a(c_1[51]),

     .b(c_2[51]), .cout(co[52]), .sum(sum[52]), .d(s_1[52]),

     .carry(cout[52]));

mul_csa42  sc3_51_ ( .c(s_2[51]), .cin(co[50]), .a(c_1[50]),

     .b(c_2[50]), .cout(co[51]), .sum(sum[51]), .d(s_1[51]),

     .carry(cout[51]));

mul_csa42  sc3_50_ ( .c(s_2[50]), .cin(co[49]), .a(c_1[49]),

     .b(c_2[49]), .cout(co[50]), .sum(sum[50]), .d(s_1[50]),

     .carry(cout[50]));

mul_csa42  sc3_49_ ( .c(s_2[49]), .cin(co[48]), .a(c_1[48]),

     .b(c_2[48]), .cout(co[49]), .sum(sum[49]), .d(s_1[49]),

     .carry(cout[49]));

mul_csa42  sc3_48_ ( .c(s_2[48]), .cin(co[47]), .a(c_1[47]),

     .b(c_2[47]), .cout(co[48]), .sum(sum[48]), .d(s_1[48]),

     .carry(cout[48]));

mul_csa42  sc3_47_ ( .c(s_2[47]), .cin(co[46]), .a(c_1[46]),

     .b(c_2[46]), .cout(co[47]), .sum(sum[47]), .d(s_1[47]),

     .carry(cout[47]));

mul_csa42  sc3_46_ ( .c(s_2[46]), .cin(co[45]), .a(c_1[45]),