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// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: sparc_exu.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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/*
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// Module Name: sparc_exu
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// Description: Execution unit containing register file(IRF),
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// execution control (ECL), ALU, shifting (SHFT).
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*/
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module sparc_exu (/*AUTOARG*/
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// Outputs
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exu_tlu_wsr_data_m, exu_tlu_va_oor_m, exu_tlu_va_oor_jl_ret_m,
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exu_tlu_ue_trap_m, exu_tlu_ttype_vld_m, exu_tlu_ttype_m,
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exu_tlu_spill_wtype, exu_tlu_spill_tid, exu_tlu_spill_other,
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exu_tlu_spill, exu_tlu_misalign_addr_jmpl_rtn_m,
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exu_tlu_cwp_retry, exu_tlu_cwp_cmplt_tid, exu_tlu_cwp_cmplt,
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exu_tlu_cwp3_w, exu_tlu_cwp2_w, exu_tlu_cwp1_w, exu_tlu_cwp0_w,
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exu_tlu_ccr3_w, exu_tlu_ccr2_w, exu_tlu_ccr1_w, exu_tlu_ccr0_w,
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exu_spu_rs3_data_e, exu_mul_rs2_data, exu_mul_rs1_data,
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exu_mul_input_vld, exu_mmu_early_va_e, exu_lsu_rs3_data_e,
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exu_lsu_rs2_data_e, exu_lsu_priority_trap_m, exu_lsu_ldst_va_e,
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exu_lsu_early_va_e, exu_ifu_va_oor_m, exu_ifu_spill_e,
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exu_ifu_regz_e, exu_ifu_regn_e, exu_ifu_oddwin_s,
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exu_ifu_longop_done_g, exu_ifu_inj_ack, exu_ifu_err_reg_m,
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exu_ifu_ecc_ue_m, exu_ifu_ecc_ce_m, exu_ifu_cc_d, exu_ifu_brpc_e,
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exu_ffu_wsr_inst_e, short_so0, short_so1, so0, exu_ifu_err_synd_m,
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// Inputs
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tlu_exu_rsr_data_m, tlu_exu_priv_trap_m, tlu_exu_pic_twobelow_m,
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tlu_exu_pic_onebelow_m, tlu_exu_cwpccr_update_m,
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tlu_exu_cwp_retry_m, tlu_exu_cwp_m, tlu_exu_ccr_m,
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tlu_exu_agp_tid, tlu_exu_agp_swap, tlu_exu_agp, sehold, se, rclk,
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mul_exu_data_g, mul_exu_ack, lsu_exu_thr_m,
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lsu_exu_st_dtlb_perr_g, lsu_exu_rd_m, lsu_exu_ldxa_m,
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lsu_exu_ldxa_data_g, lsu_exu_ldst_miss_g2, lsu_exu_flush_pipe_w,
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lsu_exu_dfill_vld_g, lsu_exu_dfill_data_g, ifu_tlu_wsr_inst_d,
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ifu_tlu_sraddr_d, ifu_tlu_flush_m, ifu_exu_wen_d,
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ifu_exu_useimm_d, ifu_exu_usecin_d, ifu_exu_use_rsr_e_l,
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ifu_exu_tv_d, ifu_exu_ttype_vld_m, ifu_exu_tid_s2, ifu_exu_tcc_e,
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ifu_exu_tagop_d, ifu_exu_shiftop_d, ifu_exu_sethi_inst_d,
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ifu_exu_setcc_d, ifu_exu_saved_e, ifu_exu_save_d,
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ifu_exu_rs3o_vld_d, ifu_exu_rs3e_vld_d, ifu_exu_rs3_s,
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ifu_exu_rs2_vld_d, ifu_exu_rs2_s, ifu_exu_rs1_vld_d,
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ifu_exu_rs1_s, ifu_exu_return_d, ifu_exu_restored_e,
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ifu_exu_restore_d, ifu_exu_ren3_s, ifu_exu_ren2_s, ifu_exu_ren1_s,
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ifu_exu_rd_ifusr_e, ifu_exu_rd_ffusr_e, ifu_exu_rd_exusr_e,
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ifu_exu_rd_d, ifu_exu_range_check_other_d,
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ifu_exu_range_check_jlret_d, ifu_exu_pcver_e, ifu_exu_pc_d,
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ifu_exu_nceen_e, ifu_exu_muls_d, ifu_exu_muldivop_d,
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ifu_exu_kill_e, ifu_exu_invert_d, ifu_exu_inst_vld_w,
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ifu_exu_inst_vld_e, ifu_exu_inj_irferr, ifu_exu_imm_data_d,
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ifu_exu_ialign_d, ifu_exu_flushw_e, ifu_exu_enshift_d,
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ifu_exu_ecc_mask, ifu_exu_dontmv_regz1_e, ifu_exu_dontmv_regz0_e,
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ifu_exu_disable_ce_e, ifu_exu_dbrinst_d, ifu_exu_casa_d,
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ifu_exu_aluop_d, ifu_exu_addr_mask_d, grst_l, ffu_exu_rsr_data_m,
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arst_l, mux_drive_disable, mem_write_disable, short_si0,
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short_si1, si0
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) ;
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input mux_drive_disable;
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input mem_write_disable;
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input short_si0;
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input short_si1;
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input si0;
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output short_so0;
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output short_so1;
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output so0;
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input arst_l; // To ecl of sparc_exu_ecl.v, ...
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input [63:0] ffu_exu_rsr_data_m; // To bypass of sparc_exu_byp.v
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input grst_l; // To ecl of sparc_exu_ecl.v, ...
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input ifu_exu_addr_mask_d; // To ecl of sparc_exu_ecl.v
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input [2:0] ifu_exu_aluop_d; // To ecl of sparc_exu_ecl.v
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input ifu_exu_casa_d; // To ecl of sparc_exu_ecl.v
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input ifu_exu_dbrinst_d; // To ecl of sparc_exu_ecl.v
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input ifu_exu_disable_ce_e; // To ecl of sparc_exu_ecl.v
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input ifu_exu_dontmv_regz0_e; // To ecl of sparc_exu_ecl.v
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input ifu_exu_dontmv_regz1_e; // To ecl of sparc_exu_ecl.v
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input [7:0] ifu_exu_ecc_mask; // To ecl of sparc_exu_ecl.v
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input ifu_exu_enshift_d; // To ecl of sparc_exu_ecl.v
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input ifu_exu_flushw_e; // To rml of sparc_exu_rml.v
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input ifu_exu_ialign_d; // To ecl of sparc_exu_ecl.v
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input [31:0] ifu_exu_imm_data_d; // To bypass of sparc_exu_byp.v
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input ifu_exu_inj_irferr; // To ecl of sparc_exu_ecl.v
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input ifu_exu_inst_vld_e; // To ecl of sparc_exu_ecl.v
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input ifu_exu_inst_vld_w; // To ecl of sparc_exu_ecl.v
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input ifu_exu_invert_d; // To ecl of sparc_exu_ecl.v, ...
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input ifu_exu_kill_e; // To ecl of sparc_exu_ecl.v
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input [4:0] ifu_exu_muldivop_d; // To ecl of sparc_exu_ecl.v
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input ifu_exu_muls_d; // To ecl of sparc_exu_ecl.v
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input ifu_exu_nceen_e; // To ecl of sparc_exu_ecl.v
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input [47:0] ifu_exu_pc_d; // To bypass of sparc_exu_byp.v
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input [63:0] ifu_exu_pcver_e; // To bypass of sparc_exu_byp.v
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input ifu_exu_range_check_jlret_d;// To ecl of sparc_exu_ecl.v
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input ifu_exu_range_check_other_d;// To ecl of sparc_exu_ecl.v
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input [4:0] ifu_exu_rd_d; // To ecl of sparc_exu_ecl.v
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input ifu_exu_rd_exusr_e; // To ecl of sparc_exu_ecl.v
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input ifu_exu_rd_ffusr_e; // To ecl of sparc_exu_ecl.v
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input ifu_exu_rd_ifusr_e; // To ecl of sparc_exu_ecl.v
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input ifu_exu_ren1_s; // To irf of bw_r_irf.v
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input ifu_exu_ren2_s; // To irf of bw_r_irf.v
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input ifu_exu_ren3_s; // To irf of bw_r_irf.v
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input ifu_exu_restore_d; // To ecl of sparc_exu_ecl.v, ...
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input ifu_exu_restored_e; // To rml of sparc_exu_rml.v
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input ifu_exu_return_d; // To ecl of sparc_exu_ecl.v
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input [4:0] ifu_exu_rs1_s; // To irf of bw_r_irf.v, ...
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input ifu_exu_rs1_vld_d; // To ecl of sparc_exu_ecl.v
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input [4:0] ifu_exu_rs2_s; // To irf of bw_r_irf.v, ...
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input ifu_exu_rs2_vld_d; // To ecl of sparc_exu_ecl.v
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input [4:0] ifu_exu_rs3_s; // To irf of bw_r_irf.v, ...
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input ifu_exu_rs3e_vld_d; // To ecl of sparc_exu_ecl.v
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input ifu_exu_rs3o_vld_d; // To ecl of sparc_exu_ecl.v
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input ifu_exu_save_d; // To ecl of sparc_exu_ecl.v, ...
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input ifu_exu_saved_e; // To rml of sparc_exu_rml.v
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input ifu_exu_setcc_d; // To ecl of sparc_exu_ecl.v
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input ifu_exu_sethi_inst_d; // To ecl of sparc_exu_ecl.v
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input [2:0] ifu_exu_shiftop_d; // To ecl of sparc_exu_ecl.v
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input ifu_exu_tagop_d; // To ecl of sparc_exu_ecl.v
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input ifu_exu_tcc_e; // To ecl of sparc_exu_ecl.v
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input [1:0] ifu_exu_tid_s2; // To irf of bw_r_irf.v, ...
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input ifu_exu_ttype_vld_m; // To ecl of sparc_exu_ecl.v
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input ifu_exu_tv_d; // To ecl of sparc_exu_ecl.v
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input ifu_exu_use_rsr_e_l; // To ecl of sparc_exu_ecl.v
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input ifu_exu_usecin_d; // To ecl of sparc_exu_ecl.v
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input ifu_exu_useimm_d; // To ecl of sparc_exu_ecl.v
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input ifu_exu_wen_d; // To ecl of sparc_exu_ecl.v
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input ifu_tlu_flush_m; // To ecl of sparc_exu_ecl.v
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input [6:0] ifu_tlu_sraddr_d; // To ecl of sparc_exu_ecl.v
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input ifu_tlu_wsr_inst_d; // To ecl of sparc_exu_ecl.v
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input [63:0] lsu_exu_dfill_data_g; // To bypass of sparc_exu_byp.v
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input lsu_exu_dfill_vld_g; // To ecl of sparc_exu_ecl.v
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input lsu_exu_flush_pipe_w; // To ecl of sparc_exu_ecl.v
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input lsu_exu_ldst_miss_g2; // To ecl of sparc_exu_ecl.v
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input [63:0] lsu_exu_ldxa_data_g; // To bypass of sparc_exu_byp.v
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input lsu_exu_ldxa_m; // To ecl of sparc_exu_ecl.v
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input [4:0] lsu_exu_rd_m; // To ecl of sparc_exu_ecl.v
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input lsu_exu_st_dtlb_perr_g; // To ecl of sparc_exu_ecl.v
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input [1:0] lsu_exu_thr_m; // To ecl of sparc_exu_ecl.v
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input mul_exu_ack; // To ecl of sparc_exu_ecl.v
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input [63:0] mul_exu_data_g; // To div of sparc_exu_div.v
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input rclk; // To irf of bw_r_irf.v, ...
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input se; // To irf of bw_r_irf.v, ...
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input sehold; // To irf of bw_r_irf.v, ...
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input [1:0] tlu_exu_agp; // To rml of sparc_exu_rml.v
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input tlu_exu_agp_swap; // To rml of sparc_exu_rml.v
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input [1:0] tlu_exu_agp_tid; // To rml of sparc_exu_rml.v
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input [7:0] tlu_exu_ccr_m; // To ecl of sparc_exu_ecl.v
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input [2:0] tlu_exu_cwp_m; // To rml of sparc_exu_rml.v
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input tlu_exu_cwp_retry_m; // To rml of sparc_exu_rml.v
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input tlu_exu_cwpccr_update_m;// To ecl of sparc_exu_ecl.v, ...
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input tlu_exu_pic_onebelow_m; // To ecl of sparc_exu_ecl.v
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input tlu_exu_pic_twobelow_m; // To ecl of sparc_exu_ecl.v
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input tlu_exu_priv_trap_m; // To ecl of sparc_exu_ecl.v
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input [63:0] tlu_exu_rsr_data_m; // To bypass of sparc_exu_byp.v
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output exu_ffu_wsr_inst_e; // From ecl of sparc_exu_ecl.v
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output [47:0] exu_ifu_brpc_e; // From alu of sparc_exu_alu.v
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output [7:0] exu_ifu_cc_d; // From ecl of sparc_exu_ecl.v
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output exu_ifu_ecc_ce_m; // From ecl of sparc_exu_ecl.v
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output exu_ifu_ecc_ue_m; // From ecl of sparc_exu_ecl.v
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output [7:0] exu_ifu_err_reg_m; // From ecl of sparc_exu_ecl.v
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output exu_ifu_inj_ack; // From ecl of sparc_exu_ecl.v
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output [3:0] exu_ifu_longop_done_g; // From ecl of sparc_exu_ecl.v
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output [3:0] exu_ifu_oddwin_s; // From rml of sparc_exu_rml.v
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output exu_ifu_regn_e; // From alu of sparc_exu_alu.v
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output exu_ifu_regz_e; // From alu of sparc_exu_alu.v
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output exu_ifu_spill_e; // From rml of sparc_exu_rml.v
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output exu_ifu_va_oor_m; // From ecl of sparc_exu_ecl.v
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output [10:3] exu_lsu_early_va_e; // From alu of sparc_exu_alu.v
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output [47:0] exu_lsu_ldst_va_e; // From alu of sparc_exu_alu.v
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output exu_lsu_priority_trap_m;// From ecl of sparc_exu_ecl.v
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output [63:0] exu_lsu_rs2_data_e; // From bypass of sparc_exu_byp.v
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output [63:0] exu_lsu_rs3_data_e; // From bypass of sparc_exu_byp.v
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output [7:0] exu_mmu_early_va_e; // From alu of sparc_exu_alu.v
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output exu_mul_input_vld; // From ecl of sparc_exu_ecl.v
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output [63:0] exu_mul_rs1_data; // From div of sparc_exu_div.v
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output [63:0] exu_mul_rs2_data; // From div of sparc_exu_div.v
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output [63:0] exu_spu_rs3_data_e; // From bypass of sparc_exu_byp.v
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output [7:0] exu_tlu_ccr0_w; // From ecl of sparc_exu_ecl.v
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output [7:0] exu_tlu_ccr1_w; // From ecl of sparc_exu_ecl.v
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output [7:0] exu_tlu_ccr2_w; // From ecl of sparc_exu_ecl.v
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output [7:0] exu_tlu_ccr3_w; // From ecl of sparc_exu_ecl.v
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output [2:0] exu_tlu_cwp0_w; // From rml of sparc_exu_rml.v
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output [2:0] exu_tlu_cwp1_w; // From rml of sparc_exu_rml.v
|
204 |
|
|
output [2:0] exu_tlu_cwp2_w; // From rml of sparc_exu_rml.v
|
205 |
|
|
output [2:0] exu_tlu_cwp3_w; // From rml of sparc_exu_rml.v
|
206 |
|
|
output exu_tlu_cwp_cmplt; // From rml of sparc_exu_rml.v
|
207 |
|
|
output [1:0] exu_tlu_cwp_cmplt_tid; // From rml of sparc_exu_rml.v
|
208 |
|
|
output exu_tlu_cwp_retry; // From rml of sparc_exu_rml.v
|
209 |
|
|
output exu_tlu_misalign_addr_jmpl_rtn_m;// From ecl of sparc_exu_ecl.v
|
210 |
|
|
output exu_tlu_spill; // From rml of sparc_exu_rml.v
|
211 |
|
|
output exu_tlu_spill_other; // From rml of sparc_exu_rml.v
|
212 |
|
|
output [1:0] exu_tlu_spill_tid; // From rml of sparc_exu_rml.v
|
213 |
|
|
output [2:0] exu_tlu_spill_wtype; // From rml of sparc_exu_rml.v
|
214 |
|
|
output [8:0] exu_tlu_ttype_m; // From ecl of sparc_exu_ecl.v
|
215 |
|
|
output exu_tlu_ttype_vld_m; // From ecl of sparc_exu_ecl.v
|
216 |
|
|
output exu_tlu_ue_trap_m; // From ecl of sparc_exu_ecl.v
|
217 |
|
|
output exu_tlu_va_oor_jl_ret_m;// From ecl of sparc_exu_ecl.v
|
218 |
|
|
output exu_tlu_va_oor_m; // From ecl of sparc_exu_ecl.v
|
219 |
|
|
output [63:0] exu_tlu_wsr_data_m; // From bypass of sparc_exu_byp.v
|
220 |
|
|
// End of automatics
|
221 |
|
|
/*AUTOWIRE*/
|
222 |
|
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
223 |
|
|
wire [63:0] alu_byp_rd_data_e; // From alu of sparc_exu_alu.v
|
224 |
|
|
wire alu_ecl_add_n32_e; // From alu of sparc_exu_alu.v
|
225 |
|
|
wire alu_ecl_add_n64_e; // From alu of sparc_exu_alu.v
|
226 |
|
|
wire alu_ecl_adder_out_63_e; // From alu of sparc_exu_alu.v
|
227 |
|
|
wire alu_ecl_adderin2_31_e; // From alu of sparc_exu_alu.v
|
228 |
|
|
wire alu_ecl_adderin2_63_e; // From alu of sparc_exu_alu.v
|
229 |
|
|
wire alu_ecl_cout32_e; // From alu of sparc_exu_alu.v
|
230 |
|
|
wire alu_ecl_cout64_e_l; // From alu of sparc_exu_alu.v
|
231 |
|
|
wire alu_ecl_log_n32_e; // From alu of sparc_exu_alu.v
|
232 |
|
|
wire alu_ecl_log_n64_e; // From alu of sparc_exu_alu.v
|
233 |
|
|
wire alu_ecl_mem_addr_invalid_e_l;// From alu of sparc_exu_alu.v
|
234 |
|
|
wire alu_ecl_zhigh_e; // From alu of sparc_exu_alu.v
|
235 |
|
|
wire alu_ecl_zlow_e; // From alu of sparc_exu_alu.v
|
236 |
|
|
wire [63:0] byp_alu_rcc_data_e; // From bypass of sparc_exu_byp.v
|
237 |
|
|
wire [63:0] byp_alu_rs1_data_e; // From bypass of sparc_exu_byp.v
|
238 |
|
|
wire [63:0] byp_alu_rs2_data_e_l; // From bypass of sparc_exu_byp.v
|
239 |
|
|
wire [63:0] byp_ecc_rcc_data_e; // From bypass of sparc_exu_byp.v
|
240 |
|
|
wire [7:0] byp_ecc_rs1_synd_d; // From bypass of sparc_exu_byp.v
|
241 |
|
|
wire [7:0] byp_ecc_rs2_synd_d; // From bypass of sparc_exu_byp.v
|
242 |
|
|
wire [63:0] byp_ecc_rs3_data_e; // From bypass of sparc_exu_byp.v
|
243 |
|
|
wire [7:0] byp_ecc_rs3_synd_d; // From bypass of sparc_exu_byp.v
|
244 |
|
|
wire [2:0] byp_ecl_rs1_2_0_e; // From bypass of sparc_exu_byp.v
|
245 |
|
|
wire byp_ecl_rs1_31_e; // From bypass of sparc_exu_byp.v
|
246 |
|
|
wire byp_ecl_rs1_63_e; // From bypass of sparc_exu_byp.v
|
247 |
|
|
wire byp_ecl_rs2_31_e; // From bypass of sparc_exu_byp.v
|
248 |
|
|
wire [3:0] byp_ecl_rs2_3_0_e; // From bypass of sparc_exu_byp.v
|
249 |
|
|
wire [71:0] byp_irf_rd_data_w; // From bypass of sparc_exu_byp.v
|
250 |
|
|
wire [71:0] byp_irf_rd_data_w2; // From bypass of sparc_exu_byp.v
|
251 |
|
|
wire [63:0] div_byp_muldivout_g; // From div of sparc_exu_div.v
|
252 |
|
|
wire [31:0] div_byp_yreg_e; // From div of sparc_exu_div.v
|
253 |
|
|
wire div_ecl_adder_out_31; // From div of sparc_exu_div.v
|
254 |
|
|
wire div_ecl_cout32; // From div of sparc_exu_div.v
|
255 |
|
|
wire div_ecl_cout64; // From div of sparc_exu_div.v
|
256 |
|
|
wire div_ecl_d_62; // From div of sparc_exu_div.v
|
257 |
|
|
wire div_ecl_d_msb; // From div of sparc_exu_div.v
|
258 |
|
|
wire div_ecl_detect_zero_high;// From div of sparc_exu_div.v
|
259 |
|
|
wire div_ecl_detect_zero_low;// From div of sparc_exu_div.v
|
260 |
|
|
wire div_ecl_dividend_msb; // From div of sparc_exu_div.v
|
261 |
|
|
wire div_ecl_gencc_in_31; // From div of sparc_exu_div.v
|
262 |
|
|
wire div_ecl_gencc_in_msb_l; // From div of sparc_exu_div.v
|
263 |
|
|
wire div_ecl_low32_nonzero; // From div of sparc_exu_div.v
|
264 |
|
|
wire div_ecl_upper32_equal; // From div of sparc_exu_div.v
|
265 |
|
|
wire div_ecl_x_msb; // From div of sparc_exu_div.v
|
266 |
|
|
wire div_ecl_xin_msb_l; // From div of sparc_exu_div.v
|
267 |
|
|
wire [3:0] div_ecl_yreg_0_l; // From div of sparc_exu_div.v
|
268 |
|
|
wire [63:0] ecc_byp_ecc_result_m; // From ecc of sparc_exu_ecc.v
|
269 |
|
|
wire ecc_ecl_rs1_ce; // From ecc of sparc_exu_ecc.v
|
270 |
|
|
wire ecc_ecl_rs1_ue; // From ecc of sparc_exu_ecc.v
|
271 |
|
|
wire ecc_ecl_rs2_ce; // From ecc of sparc_exu_ecc.v
|
272 |
|
|
wire ecc_ecl_rs2_ue; // From ecc of sparc_exu_ecc.v
|
273 |
|
|
wire ecc_ecl_rs3_ce; // From ecc of sparc_exu_ecc.v
|
274 |
|
|
wire ecc_ecl_rs3_ue; // From ecc of sparc_exu_ecc.v
|
275 |
|
|
wire ecl_alu_cin_e; // From ecl of sparc_exu_ecl.v
|
276 |
|
|
wire ecl_alu_log_sel_and_e; // From ecl of sparc_exu_ecl.v
|
277 |
|
|
wire ecl_alu_log_sel_move_e; // From ecl of sparc_exu_ecl.v
|
278 |
|
|
wire ecl_alu_log_sel_or_e; // From ecl of sparc_exu_ecl.v
|
279 |
|
|
wire ecl_alu_log_sel_xor_e; // From ecl of sparc_exu_ecl.v
|
280 |
|
|
wire ecl_alu_out_sel_logic_e_l;// From ecl of sparc_exu_ecl.v
|
281 |
|
|
wire ecl_alu_out_sel_rs3_e_l;// From ecl of sparc_exu_ecl.v
|
282 |
|
|
wire ecl_alu_out_sel_shift_e_l;// From ecl of sparc_exu_ecl.v
|
283 |
|
|
wire ecl_alu_out_sel_sum_e_l;// From ecl of sparc_exu_ecl.v
|
284 |
|
|
wire ecl_alu_sethi_inst_e; // From ecl of sparc_exu_ecl.v
|
285 |
|
|
wire [2:0] ecl_byp_3lsb_m; // From ecl of sparc_exu_ecl.v
|
286 |
|
|
wire [7:0] ecl_byp_ecc_mask_m_l; // From ecl of sparc_exu_ecl.v
|
287 |
|
|
wire [7:0] ecl_byp_eclpr_e; // From ecl of sparc_exu_ecl.v
|
288 |
|
|
wire ecl_byp_ldxa_g; // From ecl of sparc_exu_ecl.v
|
289 |
|
|
wire ecl_byp_rcc_mux1_sel_m; // From ecl of sparc_exu_ecl.v
|
290 |
|
|
wire ecl_byp_rcc_mux1_sel_other;// From ecl of sparc_exu_ecl.v
|
291 |
|
|
wire ecl_byp_rcc_mux1_sel_w; // From ecl of sparc_exu_ecl.v
|
292 |
|
|
wire ecl_byp_rcc_mux1_sel_w2;// From ecl of sparc_exu_ecl.v
|
293 |
|
|
wire ecl_byp_rcc_mux2_sel_e; // From ecl of sparc_exu_ecl.v
|
294 |
|
|
wire ecl_byp_rcc_mux2_sel_ld;// From ecl of sparc_exu_ecl.v
|
295 |
|
|
wire ecl_byp_rcc_mux2_sel_rf;// From ecl of sparc_exu_ecl.v
|
296 |
|
|
wire ecl_byp_rcc_mux2_sel_usemux1;// From ecl of sparc_exu_ecl.v
|
297 |
|
|
wire ecl_byp_restore_m; // From ecl of sparc_exu_ecl.v
|
298 |
|
|
wire ecl_byp_rs1_longmux_sel_g2;// From ecl of sparc_exu_ecl.v
|
299 |
|
|
wire ecl_byp_rs1_longmux_sel_ldxa;// From ecl of sparc_exu_ecl.v
|
300 |
|
|
wire ecl_byp_rs1_longmux_sel_w2;// From ecl of sparc_exu_ecl.v
|
301 |
|
|
wire ecl_byp_rs1_mux1_sel_m; // From ecl of sparc_exu_ecl.v
|
302 |
|
|
wire ecl_byp_rs1_mux1_sel_other;// From ecl of sparc_exu_ecl.v
|
303 |
|
|
wire ecl_byp_rs1_mux1_sel_w; // From ecl of sparc_exu_ecl.v
|
304 |
|
|
wire ecl_byp_rs1_mux1_sel_w2;// From ecl of sparc_exu_ecl.v
|
305 |
|
|
wire ecl_byp_rs1_mux2_sel_e; // From ecl of sparc_exu_ecl.v
|
306 |
|
|
wire ecl_byp_rs1_mux2_sel_ld;// From ecl of sparc_exu_ecl.v
|
307 |
|
|
wire ecl_byp_rs1_mux2_sel_rf;// From ecl of sparc_exu_ecl.v
|
308 |
|
|
wire ecl_byp_rs1_mux2_sel_usemux1;// From ecl of sparc_exu_ecl.v
|
309 |
|
|
wire ecl_byp_rs2_longmux_sel_g2;// From ecl of sparc_exu_ecl.v
|
310 |
|
|
wire ecl_byp_rs2_longmux_sel_ldxa;// From ecl of sparc_exu_ecl.v
|
311 |
|
|
wire ecl_byp_rs2_longmux_sel_w2;// From ecl of sparc_exu_ecl.v
|
312 |
|
|
wire ecl_byp_rs2_mux1_sel_m; // From ecl of sparc_exu_ecl.v
|
313 |
|
|
wire ecl_byp_rs2_mux1_sel_other;// From ecl of sparc_exu_ecl.v
|
314 |
|
|
wire ecl_byp_rs2_mux1_sel_w; // From ecl of sparc_exu_ecl.v
|
315 |
|
|
wire ecl_byp_rs2_mux1_sel_w2;// From ecl of sparc_exu_ecl.v
|
316 |
|
|
wire ecl_byp_rs2_mux2_sel_e; // From ecl of sparc_exu_ecl.v
|
317 |
|
|
wire ecl_byp_rs2_mux2_sel_ld;// From ecl of sparc_exu_ecl.v
|
318 |
|
|
wire ecl_byp_rs2_mux2_sel_rf;// From ecl of sparc_exu_ecl.v
|
319 |
|
|
wire ecl_byp_rs2_mux2_sel_usemux1;// From ecl of sparc_exu_ecl.v
|
320 |
|
|
wire ecl_byp_rs3_longmux_sel_g2;// From ecl of sparc_exu_ecl.v
|
321 |
|
|
wire ecl_byp_rs3_longmux_sel_ldxa;// From ecl of sparc_exu_ecl.v
|
322 |
|
|
wire ecl_byp_rs3_longmux_sel_w2;// From ecl of sparc_exu_ecl.v
|
323 |
|
|
wire ecl_byp_rs3_mux1_sel_m; // From ecl of sparc_exu_ecl.v
|
324 |
|
|
wire ecl_byp_rs3_mux1_sel_other;// From ecl of sparc_exu_ecl.v
|
325 |
|
|
wire ecl_byp_rs3_mux1_sel_w; // From ecl of sparc_exu_ecl.v
|
326 |
|
|
wire ecl_byp_rs3_mux1_sel_w2;// From ecl of sparc_exu_ecl.v
|
327 |
|
|
wire ecl_byp_rs3_mux2_sel_e; // From ecl of sparc_exu_ecl.v
|
328 |
|
|
wire ecl_byp_rs3_mux2_sel_ld;// From ecl of sparc_exu_ecl.v
|
329 |
|
|
wire ecl_byp_rs3_mux2_sel_rf;// From ecl of sparc_exu_ecl.v
|
330 |
|
|
wire ecl_byp_rs3_mux2_sel_usemux1;// From ecl of sparc_exu_ecl.v
|
331 |
|
|
wire ecl_byp_rs3h_longmux_sel_g2;// From ecl of sparc_exu_ecl.v
|
332 |
|
|
wire ecl_byp_rs3h_longmux_sel_ldxa;// From ecl of sparc_exu_ecl.v
|
333 |
|
|
wire ecl_byp_rs3h_longmux_sel_w2;// From ecl of sparc_exu_ecl.v
|
334 |
|
|
wire ecl_byp_rs3h_mux1_sel_m;// From ecl of sparc_exu_ecl.v
|
335 |
|
|
wire ecl_byp_rs3h_mux1_sel_other;// From ecl of sparc_exu_ecl.v
|
336 |
|
|
wire ecl_byp_rs3h_mux1_sel_w;// From ecl of sparc_exu_ecl.v
|
337 |
|
|
wire ecl_byp_rs3h_mux1_sel_w2;// From ecl of sparc_exu_ecl.v
|
338 |
|
|
wire ecl_byp_rs3h_mux2_sel_e;// From ecl of sparc_exu_ecl.v
|
339 |
|
|
wire ecl_byp_rs3h_mux2_sel_ld;// From ecl of sparc_exu_ecl.v
|
340 |
|
|
wire ecl_byp_rs3h_mux2_sel_rf;// From ecl of sparc_exu_ecl.v
|
341 |
|
|
wire ecl_byp_rs3h_mux2_sel_usemux1;// From ecl of sparc_exu_ecl.v
|
342 |
|
|
wire ecl_byp_sel_alu_e; // From ecl of sparc_exu_ecl.v
|
343 |
|
|
wire ecl_byp_sel_ecc_m; // From ecl of sparc_exu_ecl.v
|
344 |
|
|
wire ecl_byp_sel_eclpr_e; // From ecl of sparc_exu_ecl.v
|
345 |
|
|
wire ecl_byp_sel_ffusr_m; // From ecl of sparc_exu_ecl.v
|
346 |
|
|
wire ecl_byp_sel_ifex_m; // From ecl of sparc_exu_ecl.v
|
347 |
|
|
wire ecl_byp_sel_ifusr_e; // From ecl of sparc_exu_ecl.v
|
348 |
|
|
wire ecl_byp_sel_load_g; // From ecl of sparc_exu_ecl.v
|
349 |
|
|
wire ecl_byp_sel_load_m; // From ecl of sparc_exu_ecl.v
|
350 |
|
|
wire ecl_byp_sel_muldiv_g; // From ecl of sparc_exu_ecl.v
|
351 |
|
|
wire ecl_byp_sel_pipe_m; // From ecl of sparc_exu_ecl.v
|
352 |
|
|
wire ecl_byp_sel_restore_g; // From ecl of sparc_exu_ecl.v
|
353 |
|
|
wire ecl_byp_sel_restore_m; // From ecl of sparc_exu_ecl.v
|
354 |
|
|
wire ecl_byp_sel_tlusr_m; // From ecl of sparc_exu_ecl.v
|
355 |
|
|
wire ecl_byp_sel_yreg_e; // From ecl of sparc_exu_ecl.v
|
356 |
|
|
wire ecl_byp_std_e_l; // From ecl of sparc_exu_ecl.v
|
357 |
|
|
wire ecl_div_almostlast_cycle;// From ecl of sparc_exu_ecl.v
|
358 |
|
|
wire ecl_div_cin; // From ecl of sparc_exu_ecl.v
|
359 |
|
|
wire ecl_div_div64; // From ecl of sparc_exu_ecl.v
|
360 |
|
|
wire ecl_div_dividend_sign; // From ecl of sparc_exu_ecl.v
|
361 |
|
|
wire ecl_div_keep_d; // From ecl of sparc_exu_ecl.v
|
362 |
|
|
wire ecl_div_keepx; // From ecl of sparc_exu_ecl.v
|
363 |
|
|
wire ecl_div_last_cycle; // From ecl of sparc_exu_ecl.v
|
364 |
|
|
wire ecl_div_ld_inputs; // From ecl of sparc_exu_ecl.v
|
365 |
|
|
wire ecl_div_mul_get_32bit_data;// From ecl of sparc_exu_ecl.v
|
366 |
|
|
wire ecl_div_mul_get_new_data;// From ecl of sparc_exu_ecl.v
|
367 |
|
|
wire ecl_div_mul_keep_data; // From ecl of sparc_exu_ecl.v
|
368 |
|
|
wire ecl_div_mul_sext_rs1_e; // From ecl of sparc_exu_ecl.v
|
369 |
|
|
wire ecl_div_mul_sext_rs2_e; // From ecl of sparc_exu_ecl.v
|
370 |
|
|
wire ecl_div_mul_wen; // From ecl of sparc_exu_ecl.v
|
371 |
|
|
wire ecl_div_muls; // From ecl of sparc_exu_ecl.v
|
372 |
|
|
wire ecl_div_muls_rs1_31_e_l;// From ecl of sparc_exu_ecl.v
|
373 |
|
|
wire ecl_div_newq; // From ecl of sparc_exu_ecl.v
|
374 |
|
|
wire ecl_div_sel_64b; // From ecl of sparc_exu_ecl.v
|
375 |
|
|
wire ecl_div_sel_adder; // From ecl of sparc_exu_ecl.v
|
376 |
|
|
wire ecl_div_sel_div; // From ecl of sparc_exu_ecl.v
|
377 |
|
|
wire ecl_div_sel_neg32; // From ecl of sparc_exu_ecl.v
|
378 |
|
|
wire ecl_div_sel_pos32; // From ecl of sparc_exu_ecl.v
|
379 |
|
|
wire ecl_div_sel_u32; // From ecl of sparc_exu_ecl.v
|
380 |
|
|
wire ecl_div_subtract_l; // From ecl of sparc_exu_ecl.v
|
381 |
|
|
wire [3:0] ecl_div_thr_e; // From ecl of sparc_exu_ecl.v
|
382 |
|
|
wire ecl_div_upper32_zero; // From ecl of sparc_exu_ecl.v
|
383 |
|
|
wire ecl_div_upper33_one; // From ecl of sparc_exu_ecl.v
|
384 |
|
|
wire ecl_div_upper33_zero; // From ecl of sparc_exu_ecl.v
|
385 |
|
|
wire ecl_div_xinmask; // From ecl of sparc_exu_ecl.v
|
386 |
|
|
wire ecl_div_yreg_data_31_g; // From ecl of sparc_exu_ecl.v
|
387 |
|
|
wire [3:0] ecl_div_yreg_shift_g; // From ecl of sparc_exu_ecl.v
|
388 |
|
|
wire [3:0] ecl_div_yreg_wen_g; // From ecl of sparc_exu_ecl.v
|
389 |
|
|
wire [3:0] ecl_div_yreg_wen_l; // From ecl of sparc_exu_ecl.v
|
390 |
|
|
wire [3:0] ecl_div_yreg_wen_w; // From ecl of sparc_exu_ecl.v
|
391 |
|
|
wire ecl_div_zero_rs2_e; // From ecl of sparc_exu_ecl.v
|
392 |
|
|
wire ecl_ecc_log_rs1_m; // From ecl of sparc_exu_ecl.v
|
393 |
|
|
wire ecl_ecc_log_rs2_m; // From ecl of sparc_exu_ecl.v
|
394 |
|
|
wire ecl_ecc_log_rs3_m; // From ecl of sparc_exu_ecl.v
|
395 |
|
|
wire ecl_ecc_rs1_use_rf_e; // From ecl of sparc_exu_ecl.v
|
396 |
|
|
wire ecl_ecc_rs2_use_rf_e; // From ecl of sparc_exu_ecl.v
|
397 |
|
|
wire ecl_ecc_rs3_use_rf_e; // From ecl of sparc_exu_ecl.v
|
398 |
|
|
wire ecl_ecc_sel_rs1_m_l; // From ecl of sparc_exu_ecl.v
|
399 |
|
|
wire ecl_ecc_sel_rs2_m_l; // From ecl of sparc_exu_ecl.v
|
400 |
|
|
wire ecl_ecc_sel_rs3_m_l; // From ecl of sparc_exu_ecl.v
|
401 |
|
|
wire [4:0] ecl_irf_rd_g; // From ecl of sparc_exu_ecl.v
|
402 |
|
|
wire [4:0] ecl_irf_rd_m; // From ecl of sparc_exu_ecl.v
|
403 |
|
|
wire [1:0] ecl_irf_tid_g; // From ecl of sparc_exu_ecl.v
|
404 |
|
|
wire [1:0] ecl_irf_tid_m; // From ecl of sparc_exu_ecl.v
|
405 |
|
|
wire ecl_irf_wen_w; // From ecl of sparc_exu_ecl.v
|
406 |
|
|
wire ecl_irf_wen_w2; // From ecl of sparc_exu_ecl.v
|
407 |
|
|
wire ecl_rml_canrestore_wen_w;// From ecl of sparc_exu_ecl.v
|
408 |
|
|
wire ecl_rml_cansave_wen_w; // From ecl of sparc_exu_ecl.v
|
409 |
|
|
wire ecl_rml_cleanwin_wen_w; // From ecl of sparc_exu_ecl.v
|
410 |
|
|
wire ecl_rml_cwp_wen_e; // From ecl of sparc_exu_ecl.v
|
411 |
|
|
wire ecl_rml_early_flush_w; // From ecl of sparc_exu_ecl.v
|
412 |
|
|
wire ecl_rml_inst_vld_w; // From ecl of sparc_exu_ecl.v
|
413 |
|
|
wire ecl_rml_kill_e; // From ecl of sparc_exu_ecl.v
|
414 |
|
|
wire ecl_rml_kill_w; // From ecl of sparc_exu_ecl.v
|
415 |
|
|
wire ecl_rml_otherwin_wen_w; // From ecl of sparc_exu_ecl.v
|
416 |
|
|
wire [3:0] ecl_rml_thr_m; // From ecl of sparc_exu_ecl.v
|
417 |
|
|
wire [3:0] ecl_rml_thr_w; // From ecl of sparc_exu_ecl.v
|
418 |
|
|
wire ecl_rml_wstate_wen_w; // From ecl of sparc_exu_ecl.v
|
419 |
|
|
wire [2:0] ecl_rml_xor_data_e; // From ecl of sparc_exu_ecl.v
|
420 |
|
|
wire ecl_shft_enshift_e_l; // From ecl of sparc_exu_ecl.v
|
421 |
|
|
wire ecl_shft_extend32bit_e_l;// From ecl of sparc_exu_ecl.v
|
422 |
|
|
wire ecl_shft_extendbit_e; // From ecl of sparc_exu_ecl.v
|
423 |
|
|
wire ecl_shft_lshift_e_l; // From ecl of sparc_exu_ecl.v
|
424 |
|
|
wire ecl_shft_op32_e; // From ecl of sparc_exu_ecl.v
|
425 |
|
|
wire [3:0] ecl_shft_shift1_e; // From ecl of sparc_exu_ecl.v
|
426 |
|
|
wire [3:0] ecl_shft_shift4_e; // From ecl of sparc_exu_ecl.v
|
427 |
|
|
wire [71:0] irf_byp_rs1_data_d_l; // From irf of bw_r_irf.v
|
428 |
|
|
wire [71:0] irf_byp_rs2_data_d_l; // From irf of bw_r_irf.v
|
429 |
|
|
wire [71:0] irf_byp_rs3_data_d_l; // From irf of bw_r_irf.v
|
430 |
|
|
wire [31:0] irf_byp_rs3h_data_d_l; // From irf of bw_r_irf.v
|
431 |
|
|
wire [2:0] rml_ecl_canrestore_d; // From rml of sparc_exu_rml.v
|
432 |
|
|
wire [2:0] rml_ecl_cansave_d; // From rml of sparc_exu_rml.v
|
433 |
|
|
wire rml_ecl_clean_window_e; // From rml of sparc_exu_rml.v
|
434 |
|
|
wire [2:0] rml_ecl_cleanwin_d; // From rml of sparc_exu_rml.v
|
435 |
|
|
wire [2:0] rml_ecl_cwp_d; // From rml of sparc_exu_rml.v
|
436 |
|
|
wire rml_ecl_fill_e; // From rml of sparc_exu_rml.v
|
437 |
|
|
wire [1:0] rml_ecl_gl_e; // From rml of sparc_exu_rml.v
|
438 |
|
|
wire rml_ecl_kill_m; // From rml of sparc_exu_rml.v
|
439 |
|
|
wire rml_ecl_other_e; // From rml of sparc_exu_rml.v
|
440 |
|
|
wire [2:0] rml_ecl_otherwin_d; // From rml of sparc_exu_rml.v
|
441 |
|
|
wire rml_ecl_rmlop_done_e; // From rml of sparc_exu_rml.v
|
442 |
|
|
wire [3:0] rml_ecl_swap_done; // From rml of sparc_exu_rml.v
|
443 |
|
|
wire [5:0] rml_ecl_wstate_d; // From rml of sparc_exu_rml.v
|
444 |
|
|
wire [2:0] rml_ecl_wtype_e; // From rml of sparc_exu_rml.v
|
445 |
|
|
wire [1:0] rml_irf_cwpswap_tid_e; // From rml of sparc_exu_rml.v
|
446 |
|
|
wire [1:0] rml_irf_global_tid; // From rml of sparc_exu_rml.v
|
447 |
|
|
wire rml_irf_kill_restore_w; // From rml of sparc_exu_rml.v
|
448 |
|
|
wire [1:0] rml_irf_new_agp; // From rml of sparc_exu_rml.v
|
449 |
|
|
wire [2:0] rml_irf_new_lo_cwp_e; // From rml of sparc_exu_rml.v
|
450 |
|
|
wire [1:0] rml_irf_old_agp; // From rml of sparc_exu_rml.v
|
451 |
|
|
wire [2:0] rml_irf_old_lo_cwp_e; // From rml of sparc_exu_rml.v
|
452 |
|
|
wire rml_irf_swap_even_e; // From rml of sparc_exu_rml.v
|
453 |
|
|
wire rml_irf_swap_global; // From rml of sparc_exu_rml.v
|
454 |
|
|
wire rml_irf_swap_local_e; // From rml of sparc_exu_rml.v
|
455 |
|
|
wire rml_irf_swap_odd_e; // From rml of sparc_exu_rml.v
|
456 |
|
|
wire [63:0] shft_alu_shift_out_e; // From shft of sparc_exu_shft.v
|
457 |
|
|
// End of automatics
|
458 |
|
|
wire short_scan0_1;
|
459 |
|
|
wire scan0_1,scan0_2,scan0_3;
|
460 |
|
|
|
461 |
|
|
wire ecl_alu_casa_e;
|
462 |
|
|
wire [63:0] byp_alu_rs2_data_e;
|
463 |
|
|
output [7:0] exu_ifu_err_synd_m;
|
464 |
|
|
wire [1:0] rml_irf_old_e_cwp_e;
|
465 |
|
|
wire [1:0] rml_irf_new_e_cwp_e;
|
466 |
|
|
|
467 |
|
|
bw_r_irf irf(
|
468 |
|
|
.so (short_scan0_1),
|
469 |
|
|
.si (short_si0),
|
470 |
|
|
.reset_l (arst_l),
|
471 |
|
|
.rst_tri_en (mem_write_disable),
|
472 |
|
|
.rml_irf_old_e_cwp_e (rml_irf_old_e_cwp_e[1:0]),
|
473 |
|
|
.rml_irf_new_e_cwp_e (rml_irf_new_e_cwp_e[1:0]),
|
474 |
|
|
/*AUTOINST*/
|
475 |
|
|
// Outputs
|
476 |
|
|
.irf_byp_rs1_data_d_l (irf_byp_rs1_data_d_l[71:0]),
|
477 |
|
|
.irf_byp_rs2_data_d_l (irf_byp_rs2_data_d_l[71:0]),
|
478 |
|
|
.irf_byp_rs3_data_d_l (irf_byp_rs3_data_d_l[71:0]),
|
479 |
|
|
.irf_byp_rs3h_data_d_l (irf_byp_rs3h_data_d_l[31:0]),
|
480 |
|
|
// Inputs
|
481 |
|
|
.rclk (rclk),
|
482 |
|
|
.se (se),
|
483 |
|
|
.sehold (sehold),
|
484 |
|
|
.ifu_exu_tid_s2 (ifu_exu_tid_s2[1:0]),
|
485 |
|
|
.ifu_exu_rs1_s (ifu_exu_rs1_s[4:0]),
|
486 |
|
|
.ifu_exu_rs2_s (ifu_exu_rs2_s[4:0]),
|
487 |
|
|
.ifu_exu_rs3_s (ifu_exu_rs3_s[4:0]),
|
488 |
|
|
.ifu_exu_ren1_s (ifu_exu_ren1_s),
|
489 |
|
|
.ifu_exu_ren2_s (ifu_exu_ren2_s),
|
490 |
|
|
.ifu_exu_ren3_s (ifu_exu_ren3_s),
|
491 |
|
|
.ecl_irf_wen_w (ecl_irf_wen_w),
|
492 |
|
|
.ecl_irf_wen_w2 (ecl_irf_wen_w2),
|
493 |
|
|
.ecl_irf_rd_m (ecl_irf_rd_m[4:0]),
|
494 |
|
|
.ecl_irf_rd_g (ecl_irf_rd_g[4:0]),
|
495 |
|
|
.byp_irf_rd_data_w (byp_irf_rd_data_w[71:0]),
|
496 |
|
|
.byp_irf_rd_data_w2 (byp_irf_rd_data_w2[71:0]),
|
497 |
|
|
.ecl_irf_tid_m (ecl_irf_tid_m[1:0]),
|
498 |
|
|
.ecl_irf_tid_g (ecl_irf_tid_g[1:0]),
|
499 |
|
|
.rml_irf_old_lo_cwp_e (rml_irf_old_lo_cwp_e[2:0]),
|
500 |
|
|
.rml_irf_new_lo_cwp_e (rml_irf_new_lo_cwp_e[2:0]),
|
501 |
|
|
.rml_irf_swap_even_e (rml_irf_swap_even_e),
|
502 |
|
|
.rml_irf_swap_odd_e (rml_irf_swap_odd_e),
|
503 |
|
|
.rml_irf_swap_local_e (rml_irf_swap_local_e),
|
504 |
|
|
.rml_irf_kill_restore_w (rml_irf_kill_restore_w),
|
505 |
|
|
.rml_irf_cwpswap_tid_e (rml_irf_cwpswap_tid_e[1:0]),
|
506 |
|
|
.rml_irf_old_agp (rml_irf_old_agp[1:0]),
|
507 |
|
|
.rml_irf_new_agp (rml_irf_new_agp[1:0]),
|
508 |
|
|
.rml_irf_swap_global (rml_irf_swap_global),
|
509 |
|
|
.rml_irf_global_tid (rml_irf_global_tid[1:0]));
|
510 |
|
|
|
511 |
|
|
sparc_exu_byp bypass(
|
512 |
|
|
.so (short_so1),
|
513 |
|
|
.si (short_si1),
|
514 |
|
|
.byp_alu_rs2_data_e(byp_alu_rs2_data_e[63:0]),
|
515 |
|
|
/*AUTOINST*/
|
516 |
|
|
// Outputs
|
517 |
|
|
.byp_alu_rs1_data_e(byp_alu_rs1_data_e[63:0]),
|
518 |
|
|
.byp_alu_rs2_data_e_l(byp_alu_rs2_data_e_l[63:0]),
|
519 |
|
|
.exu_lsu_rs3_data_e(exu_lsu_rs3_data_e[63:0]),
|
520 |
|
|
.exu_spu_rs3_data_e(exu_spu_rs3_data_e[63:0]),
|
521 |
|
|
.exu_lsu_rs2_data_e(exu_lsu_rs2_data_e[63:0]),
|
522 |
|
|
.byp_alu_rcc_data_e(byp_alu_rcc_data_e[63:0]),
|
523 |
|
|
.byp_irf_rd_data_w(byp_irf_rd_data_w[71:0]),
|
524 |
|
|
.exu_tlu_wsr_data_m(exu_tlu_wsr_data_m[63:0]),
|
525 |
|
|
.byp_irf_rd_data_w2(byp_irf_rd_data_w2[71:0]),
|
526 |
|
|
.byp_ecc_rs3_data_e(byp_ecc_rs3_data_e[63:0]),
|
527 |
|
|
.byp_ecc_rcc_data_e(byp_ecc_rcc_data_e[63:0]),
|
528 |
|
|
.byp_ecl_rs2_31_e(byp_ecl_rs2_31_e),
|
529 |
|
|
.byp_ecl_rs1_31_e(byp_ecl_rs1_31_e),
|
530 |
|
|
.byp_ecl_rs1_63_e(byp_ecl_rs1_63_e),
|
531 |
|
|
.byp_ecl_rs1_2_0_e(byp_ecl_rs1_2_0_e[2:0]),
|
532 |
|
|
.byp_ecl_rs2_3_0_e(byp_ecl_rs2_3_0_e[3:0]),
|
533 |
|
|
.byp_ecc_rs1_synd_d(byp_ecc_rs1_synd_d[7:0]),
|
534 |
|
|
.byp_ecc_rs2_synd_d(byp_ecc_rs2_synd_d[7:0]),
|
535 |
|
|
.byp_ecc_rs3_synd_d(byp_ecc_rs3_synd_d[7:0]),
|
536 |
|
|
// Inputs
|
537 |
|
|
.rclk (rclk),
|
538 |
|
|
.se (se),
|
539 |
|
|
.sehold (sehold),
|
540 |
|
|
.ecl_byp_rs1_mux2_sel_e(ecl_byp_rs1_mux2_sel_e),
|
541 |
|
|
.ecl_byp_rs1_mux2_sel_rf(ecl_byp_rs1_mux2_sel_rf),
|
542 |
|
|
.ecl_byp_rs1_mux2_sel_ld(ecl_byp_rs1_mux2_sel_ld),
|
543 |
|
|
.ecl_byp_rs1_mux2_sel_usemux1(ecl_byp_rs1_mux2_sel_usemux1),
|
544 |
|
|
.ecl_byp_rs1_mux1_sel_m(ecl_byp_rs1_mux1_sel_m),
|
545 |
|
|
.ecl_byp_rs1_mux1_sel_w(ecl_byp_rs1_mux1_sel_w),
|
546 |
|
|
.ecl_byp_rs1_mux1_sel_w2(ecl_byp_rs1_mux1_sel_w2),
|
547 |
|
|
.ecl_byp_rs1_mux1_sel_other(ecl_byp_rs1_mux1_sel_other),
|
548 |
|
|
.ecl_byp_rcc_mux2_sel_e(ecl_byp_rcc_mux2_sel_e),
|
549 |
|
|
.ecl_byp_rcc_mux2_sel_rf(ecl_byp_rcc_mux2_sel_rf),
|
550 |
|
|
.ecl_byp_rcc_mux2_sel_ld(ecl_byp_rcc_mux2_sel_ld),
|
551 |
|
|
.ecl_byp_rcc_mux2_sel_usemux1(ecl_byp_rcc_mux2_sel_usemux1),
|
552 |
|
|
.ecl_byp_rcc_mux1_sel_m(ecl_byp_rcc_mux1_sel_m),
|
553 |
|
|
.ecl_byp_rcc_mux1_sel_w(ecl_byp_rcc_mux1_sel_w),
|
554 |
|
|
.ecl_byp_rcc_mux1_sel_w2(ecl_byp_rcc_mux1_sel_w2),
|
555 |
|
|
.ecl_byp_rcc_mux1_sel_other(ecl_byp_rcc_mux1_sel_other),
|
556 |
|
|
.ecl_byp_rs2_mux2_sel_e(ecl_byp_rs2_mux2_sel_e),
|
557 |
|
|
.ecl_byp_rs2_mux2_sel_rf(ecl_byp_rs2_mux2_sel_rf),
|
558 |
|
|
.ecl_byp_rs2_mux2_sel_ld(ecl_byp_rs2_mux2_sel_ld),
|
559 |
|
|
.ecl_byp_rs2_mux2_sel_usemux1(ecl_byp_rs2_mux2_sel_usemux1),
|
560 |
|
|
.ecl_byp_rs2_mux1_sel_m(ecl_byp_rs2_mux1_sel_m),
|
561 |
|
|
.ecl_byp_rs2_mux1_sel_w(ecl_byp_rs2_mux1_sel_w),
|
562 |
|
|
.ecl_byp_rs2_mux1_sel_w2(ecl_byp_rs2_mux1_sel_w2),
|
563 |
|
|
.ecl_byp_rs2_mux1_sel_other(ecl_byp_rs2_mux1_sel_other),
|
564 |
|
|
.ecl_byp_rs3_mux2_sel_e(ecl_byp_rs3_mux2_sel_e),
|
565 |
|
|
.ecl_byp_rs3_mux2_sel_rf(ecl_byp_rs3_mux2_sel_rf),
|
566 |
|
|
.ecl_byp_rs3_mux2_sel_ld(ecl_byp_rs3_mux2_sel_ld),
|
567 |
|
|
.ecl_byp_rs3_mux2_sel_usemux1(ecl_byp_rs3_mux2_sel_usemux1),
|
568 |
|
|
.ecl_byp_rs3_mux1_sel_m(ecl_byp_rs3_mux1_sel_m),
|
569 |
|
|
.ecl_byp_rs3_mux1_sel_w(ecl_byp_rs3_mux1_sel_w),
|
570 |
|
|
.ecl_byp_rs3_mux1_sel_w2(ecl_byp_rs3_mux1_sel_w2),
|
571 |
|
|
.ecl_byp_rs3_mux1_sel_other(ecl_byp_rs3_mux1_sel_other),
|
572 |
|
|
.ecl_byp_rs3h_mux2_sel_e(ecl_byp_rs3h_mux2_sel_e),
|
573 |
|
|
.ecl_byp_rs3h_mux2_sel_rf(ecl_byp_rs3h_mux2_sel_rf),
|
574 |
|
|
.ecl_byp_rs3h_mux2_sel_ld(ecl_byp_rs3h_mux2_sel_ld),
|
575 |
|
|
.ecl_byp_rs3h_mux2_sel_usemux1(ecl_byp_rs3h_mux2_sel_usemux1),
|
576 |
|
|
.ecl_byp_rs3h_mux1_sel_m(ecl_byp_rs3h_mux1_sel_m),
|
577 |
|
|
.ecl_byp_rs3h_mux1_sel_w(ecl_byp_rs3h_mux1_sel_w),
|
578 |
|
|
.ecl_byp_rs3h_mux1_sel_w2(ecl_byp_rs3h_mux1_sel_w2),
|
579 |
|
|
.ecl_byp_rs3h_mux1_sel_other(ecl_byp_rs3h_mux1_sel_other),
|
580 |
|
|
.ecl_byp_rs1_longmux_sel_g2(ecl_byp_rs1_longmux_sel_g2),
|
581 |
|
|
.ecl_byp_rs1_longmux_sel_w2(ecl_byp_rs1_longmux_sel_w2),
|
582 |
|
|
.ecl_byp_rs1_longmux_sel_ldxa(ecl_byp_rs1_longmux_sel_ldxa),
|
583 |
|
|
.ecl_byp_rs2_longmux_sel_g2(ecl_byp_rs2_longmux_sel_g2),
|
584 |
|
|
.ecl_byp_rs2_longmux_sel_w2(ecl_byp_rs2_longmux_sel_w2),
|
585 |
|
|
.ecl_byp_rs2_longmux_sel_ldxa(ecl_byp_rs2_longmux_sel_ldxa),
|
586 |
|
|
.ecl_byp_rs3_longmux_sel_g2(ecl_byp_rs3_longmux_sel_g2),
|
587 |
|
|
.ecl_byp_rs3_longmux_sel_w2(ecl_byp_rs3_longmux_sel_w2),
|
588 |
|
|
.ecl_byp_rs3_longmux_sel_ldxa(ecl_byp_rs3_longmux_sel_ldxa),
|
589 |
|
|
.ecl_byp_rs3h_longmux_sel_g2(ecl_byp_rs3h_longmux_sel_g2),
|
590 |
|
|
.ecl_byp_rs3h_longmux_sel_w2(ecl_byp_rs3h_longmux_sel_w2),
|
591 |
|
|
.ecl_byp_rs3h_longmux_sel_ldxa(ecl_byp_rs3h_longmux_sel_ldxa),
|
592 |
|
|
.ecl_byp_sel_load_m(ecl_byp_sel_load_m),
|
593 |
|
|
.ecl_byp_sel_pipe_m(ecl_byp_sel_pipe_m),
|
594 |
|
|
.ecl_byp_sel_ecc_m(ecl_byp_sel_ecc_m),
|
595 |
|
|
.ecl_byp_sel_muldiv_g(ecl_byp_sel_muldiv_g),
|
596 |
|
|
.ecl_byp_sel_load_g(ecl_byp_sel_load_g),
|
597 |
|
|
.ecl_byp_sel_restore_g(ecl_byp_sel_restore_g),
|
598 |
|
|
.ecl_byp_std_e_l(ecl_byp_std_e_l),
|
599 |
|
|
.ecl_byp_ldxa_g (ecl_byp_ldxa_g),
|
600 |
|
|
.alu_byp_rd_data_e(alu_byp_rd_data_e[63:0]),
|
601 |
|
|
.ifu_exu_imm_data_d(ifu_exu_imm_data_d[31:0]),
|
602 |
|
|
.irf_byp_rs1_data_d_l(irf_byp_rs1_data_d_l[71:0]),
|
603 |
|
|
.irf_byp_rs2_data_d_l(irf_byp_rs2_data_d_l[71:0]),
|
604 |
|
|
.irf_byp_rs3_data_d_l(irf_byp_rs3_data_d_l[71:0]),
|
605 |
|
|
.irf_byp_rs3h_data_d_l(irf_byp_rs3h_data_d_l[31:0]),
|
606 |
|
|
.lsu_exu_dfill_data_g(lsu_exu_dfill_data_g[63:0]),
|
607 |
|
|
.lsu_exu_ldxa_data_g(lsu_exu_ldxa_data_g[63:0]),
|
608 |
|
|
.div_byp_muldivout_g(div_byp_muldivout_g[63:0]),
|
609 |
|
|
.ecc_byp_ecc_result_m(ecc_byp_ecc_result_m[63:0]),
|
610 |
|
|
.ecl_byp_ecc_mask_m_l(ecl_byp_ecc_mask_m_l[7:0]),
|
611 |
|
|
.ifu_exu_pc_d (ifu_exu_pc_d[47:0]),
|
612 |
|
|
.ecl_byp_3lsb_m (ecl_byp_3lsb_m[2:0]),
|
613 |
|
|
.ecl_byp_restore_m(ecl_byp_restore_m),
|
614 |
|
|
.ecl_byp_sel_restore_m(ecl_byp_sel_restore_m),
|
615 |
|
|
.ecl_byp_eclpr_e(ecl_byp_eclpr_e[7:0]),
|
616 |
|
|
.div_byp_yreg_e (div_byp_yreg_e[31:0]),
|
617 |
|
|
.ifu_exu_pcver_e(ifu_exu_pcver_e[63:0]),
|
618 |
|
|
.tlu_exu_rsr_data_m(tlu_exu_rsr_data_m[63:0]),
|
619 |
|
|
.ffu_exu_rsr_data_m(ffu_exu_rsr_data_m[63:0]),
|
620 |
|
|
.ecl_byp_sel_yreg_e(ecl_byp_sel_yreg_e),
|
621 |
|
|
.ecl_byp_sel_eclpr_e(ecl_byp_sel_eclpr_e),
|
622 |
|
|
.ecl_byp_sel_ifusr_e(ecl_byp_sel_ifusr_e),
|
623 |
|
|
.ecl_byp_sel_alu_e(ecl_byp_sel_alu_e),
|
624 |
|
|
.ecl_byp_sel_ifex_m(ecl_byp_sel_ifex_m),
|
625 |
|
|
.ecl_byp_sel_ffusr_m(ecl_byp_sel_ffusr_m),
|
626 |
|
|
.ecl_byp_sel_tlusr_m(ecl_byp_sel_tlusr_m));
|
627 |
|
|
|
628 |
|
|
sparc_exu_ecc ecc(
|
629 |
|
|
.so (scan0_1),
|
630 |
|
|
.si (si0),
|
631 |
|
|
.byp_alu_rs2_data_e(byp_alu_rs2_data_e[63:0]),
|
632 |
|
|
/*AUTOINST*/
|
633 |
|
|
// Outputs
|
634 |
|
|
.ecc_ecl_rs1_ce (ecc_ecl_rs1_ce),
|
635 |
|
|
.ecc_ecl_rs1_ue (ecc_ecl_rs1_ue),
|
636 |
|
|
.ecc_ecl_rs2_ce (ecc_ecl_rs2_ce),
|
637 |
|
|
.ecc_ecl_rs2_ue (ecc_ecl_rs2_ue),
|
638 |
|
|
.ecc_ecl_rs3_ce (ecc_ecl_rs3_ce),
|
639 |
|
|
.ecc_ecl_rs3_ue (ecc_ecl_rs3_ue),
|
640 |
|
|
.ecc_byp_ecc_result_m(ecc_byp_ecc_result_m[63:0]),
|
641 |
|
|
.exu_ifu_err_synd_m(exu_ifu_err_synd_m[6:0]),
|
642 |
|
|
// Inputs
|
643 |
|
|
.rclk (rclk),
|
644 |
|
|
.se (se),
|
645 |
|
|
.byp_ecc_rcc_data_e(byp_ecc_rcc_data_e[63:0]),
|
646 |
|
|
.ecl_ecc_rs1_use_rf_e(ecl_ecc_rs1_use_rf_e),
|
647 |
|
|
.byp_ecc_rs1_synd_d(byp_ecc_rs1_synd_d[7:0]),
|
648 |
|
|
.ecl_ecc_rs2_use_rf_e(ecl_ecc_rs2_use_rf_e),
|
649 |
|
|
.byp_ecc_rs2_synd_d(byp_ecc_rs2_synd_d[7:0]),
|
650 |
|
|
.byp_ecc_rs3_data_e(byp_ecc_rs3_data_e[63:0]),
|
651 |
|
|
.ecl_ecc_rs3_use_rf_e(ecl_ecc_rs3_use_rf_e),
|
652 |
|
|
.byp_ecc_rs3_synd_d(byp_ecc_rs3_synd_d[7:0]),
|
653 |
|
|
.ecl_ecc_sel_rs1_m_l(ecl_ecc_sel_rs1_m_l),
|
654 |
|
|
.ecl_ecc_sel_rs2_m_l(ecl_ecc_sel_rs2_m_l),
|
655 |
|
|
.ecl_ecc_sel_rs3_m_l(ecl_ecc_sel_rs3_m_l),
|
656 |
|
|
.ecl_ecc_log_rs1_m (ecl_ecc_log_rs1_m),
|
657 |
|
|
.ecl_ecc_log_rs2_m (ecl_ecc_log_rs2_m),
|
658 |
|
|
.ecl_ecc_log_rs3_m (ecl_ecc_log_rs3_m));
|
659 |
|
|
|
660 |
|
|
sparc_exu_ecl ecl(
|
661 |
|
|
.so (short_so0),
|
662 |
|
|
.si (short_scan0_1),
|
663 |
|
|
.rst_tri_en (mux_drive_disable),
|
664 |
|
|
.byp_ecl_wrccr_data_w(byp_irf_rd_data_w[7:0]),
|
665 |
|
|
.alu_ecl_adder_out_31_e(exu_ifu_brpc_e[31]),
|
666 |
|
|
.byp_ecl_rd_data_3lsb_m(exu_tlu_wsr_data_m[2:0]),
|
667 |
|
|
.alu_ecl_adder_out_7_0_e(exu_ifu_brpc_e[7:0]),
|
668 |
|
|
.exu_ifu_regz_e (exu_ifu_regz_e),
|
669 |
|
|
.ecl_alu_casa_e (ecl_alu_casa_e),
|
670 |
|
|
.exu_ifu_err_synd_7_m (exu_ifu_err_synd_m[7]),
|
671 |
|
|
/*AUTOINST*/
|
672 |
|
|
// Outputs
|
673 |
|
|
.ecl_byp_ecc_mask_m_l(ecl_byp_ecc_mask_m_l[7:0]),
|
674 |
|
|
.ecl_byp_eclpr_e (ecl_byp_eclpr_e[7:0]),
|
675 |
|
|
.ecl_byp_sel_load_g(ecl_byp_sel_load_g),
|
676 |
|
|
.ecl_byp_sel_load_m(ecl_byp_sel_load_m),
|
677 |
|
|
.ecl_byp_sel_muldiv_g(ecl_byp_sel_muldiv_g),
|
678 |
|
|
.ecl_byp_sel_pipe_m(ecl_byp_sel_pipe_m),
|
679 |
|
|
.ecl_byp_sel_restore_g(ecl_byp_sel_restore_g),
|
680 |
|
|
.ecl_byp_sel_restore_m(ecl_byp_sel_restore_m),
|
681 |
|
|
.ecl_div_almostlast_cycle(ecl_div_almostlast_cycle),
|
682 |
|
|
.ecl_div_cin (ecl_div_cin),
|
683 |
|
|
.ecl_div_dividend_sign(ecl_div_dividend_sign),
|
684 |
|
|
.ecl_div_keep_d (ecl_div_keep_d),
|
685 |
|
|
.ecl_div_keepx (ecl_div_keepx),
|
686 |
|
|
.ecl_div_last_cycle(ecl_div_last_cycle),
|
687 |
|
|
.ecl_div_mul_get_32bit_data(ecl_div_mul_get_32bit_data),
|
688 |
|
|
.ecl_div_mul_get_new_data(ecl_div_mul_get_new_data),
|
689 |
|
|
.ecl_div_mul_keep_data(ecl_div_mul_keep_data),
|
690 |
|
|
.ecl_div_mul_sext_rs1_e(ecl_div_mul_sext_rs1_e),
|
691 |
|
|
.ecl_div_mul_sext_rs2_e(ecl_div_mul_sext_rs2_e),
|
692 |
|
|
.ecl_div_newq (ecl_div_newq),
|
693 |
|
|
.ecl_div_sel_64b (ecl_div_sel_64b),
|
694 |
|
|
.ecl_div_sel_adder (ecl_div_sel_adder),
|
695 |
|
|
.ecl_div_sel_neg32 (ecl_div_sel_neg32),
|
696 |
|
|
.ecl_div_sel_pos32 (ecl_div_sel_pos32),
|
697 |
|
|
.ecl_div_sel_u32 (ecl_div_sel_u32),
|
698 |
|
|
.ecl_div_subtract_l(ecl_div_subtract_l),
|
699 |
|
|
.ecl_div_upper32_zero(ecl_div_upper32_zero),
|
700 |
|
|
.ecl_div_upper33_one(ecl_div_upper33_one),
|
701 |
|
|
.ecl_div_upper33_zero(ecl_div_upper33_zero),
|
702 |
|
|
.ecl_div_xinmask (ecl_div_xinmask),
|
703 |
|
|
.ecl_div_yreg_shift_g(ecl_div_yreg_shift_g[3:0]),
|
704 |
|
|
.ecl_div_yreg_wen_g(ecl_div_yreg_wen_g[3:0]),
|
705 |
|
|
.ecl_div_yreg_wen_l(ecl_div_yreg_wen_l[3:0]),
|
706 |
|
|
.ecl_div_yreg_wen_w(ecl_div_yreg_wen_w[3:0]),
|
707 |
|
|
.ecl_ecc_log_rs1_m (ecl_ecc_log_rs1_m),
|
708 |
|
|
.ecl_ecc_log_rs2_m (ecl_ecc_log_rs2_m),
|
709 |
|
|
.ecl_ecc_log_rs3_m (ecl_ecc_log_rs3_m),
|
710 |
|
|
.ecl_ecc_sel_rs1_m_l(ecl_ecc_sel_rs1_m_l),
|
711 |
|
|
.ecl_ecc_sel_rs2_m_l(ecl_ecc_sel_rs2_m_l),
|
712 |
|
|
.ecl_ecc_sel_rs3_m_l(ecl_ecc_sel_rs3_m_l),
|
713 |
|
|
.ecl_rml_canrestore_wen_w(ecl_rml_canrestore_wen_w),
|
714 |
|
|
.ecl_rml_cansave_wen_w(ecl_rml_cansave_wen_w),
|
715 |
|
|
.ecl_rml_cleanwin_wen_w(ecl_rml_cleanwin_wen_w),
|
716 |
|
|
.ecl_rml_cwp_wen_e (ecl_rml_cwp_wen_e),
|
717 |
|
|
.ecl_rml_otherwin_wen_w(ecl_rml_otherwin_wen_w),
|
718 |
|
|
.ecl_rml_wstate_wen_w(ecl_rml_wstate_wen_w),
|
719 |
|
|
.exu_ffu_wsr_inst_e(exu_ffu_wsr_inst_e),
|
720 |
|
|
.exu_ifu_ecc_ce_m (exu_ifu_ecc_ce_m),
|
721 |
|
|
.exu_ifu_ecc_ue_m (exu_ifu_ecc_ue_m),
|
722 |
|
|
.exu_ifu_err_reg_m (exu_ifu_err_reg_m[7:0]),
|
723 |
|
|
.exu_ifu_inj_ack (exu_ifu_inj_ack),
|
724 |
|
|
.exu_ifu_longop_done_g(exu_ifu_longop_done_g[3:0]),
|
725 |
|
|
.exu_mul_input_vld (exu_mul_input_vld),
|
726 |
|
|
.exu_tlu_ccr0_w (exu_tlu_ccr0_w[7:0]),
|
727 |
|
|
.exu_tlu_ccr1_w (exu_tlu_ccr1_w[7:0]),
|
728 |
|
|
.exu_tlu_ccr2_w (exu_tlu_ccr2_w[7:0]),
|
729 |
|
|
.exu_tlu_ccr3_w (exu_tlu_ccr3_w[7:0]),
|
730 |
|
|
.ecl_byp_sel_alu_e (ecl_byp_sel_alu_e),
|
731 |
|
|
.ecl_byp_sel_eclpr_e(ecl_byp_sel_eclpr_e),
|
732 |
|
|
.ecl_byp_sel_yreg_e(ecl_byp_sel_yreg_e),
|
733 |
|
|
.ecl_byp_sel_ifusr_e(ecl_byp_sel_ifusr_e),
|
734 |
|
|
.ecl_byp_sel_ffusr_m(ecl_byp_sel_ffusr_m),
|
735 |
|
|
.ecl_byp_sel_ifex_m(ecl_byp_sel_ifex_m),
|
736 |
|
|
.ecl_byp_sel_tlusr_m(ecl_byp_sel_tlusr_m),
|
737 |
|
|
.exu_ifu_va_oor_m (exu_ifu_va_oor_m),
|
738 |
|
|
.ecl_alu_out_sel_sum_e_l(ecl_alu_out_sel_sum_e_l),
|
739 |
|
|
.ecl_alu_out_sel_rs3_e_l(ecl_alu_out_sel_rs3_e_l),
|
740 |
|
|
.ecl_alu_out_sel_shift_e_l(ecl_alu_out_sel_shift_e_l),
|
741 |
|
|
.ecl_alu_out_sel_logic_e_l(ecl_alu_out_sel_logic_e_l),
|
742 |
|
|
.ecl_alu_log_sel_and_e(ecl_alu_log_sel_and_e),
|
743 |
|
|
.ecl_alu_log_sel_or_e(ecl_alu_log_sel_or_e),
|
744 |
|
|
.ecl_alu_log_sel_xor_e(ecl_alu_log_sel_xor_e),
|
745 |
|
|
.ecl_alu_log_sel_move_e(ecl_alu_log_sel_move_e),
|
746 |
|
|
.ecl_alu_sethi_inst_e(ecl_alu_sethi_inst_e),
|
747 |
|
|
.ecl_alu_cin_e (ecl_alu_cin_e),
|
748 |
|
|
.ecl_shft_lshift_e_l(ecl_shft_lshift_e_l),
|
749 |
|
|
.ecl_shft_op32_e (ecl_shft_op32_e),
|
750 |
|
|
.ecl_shft_shift4_e (ecl_shft_shift4_e[3:0]),
|
751 |
|
|
.ecl_shft_shift1_e (ecl_shft_shift1_e[3:0]),
|
752 |
|
|
.ecl_shft_enshift_e_l(ecl_shft_enshift_e_l),
|
753 |
|
|
.ecl_byp_restore_m (ecl_byp_restore_m),
|
754 |
|
|
.ecl_byp_rs1_mux2_sel_e(ecl_byp_rs1_mux2_sel_e),
|
755 |
|
|
.ecl_byp_rs1_mux2_sel_rf(ecl_byp_rs1_mux2_sel_rf),
|
756 |
|
|
.ecl_byp_rs1_mux2_sel_ld(ecl_byp_rs1_mux2_sel_ld),
|
757 |
|
|
.ecl_byp_rs1_mux2_sel_usemux1(ecl_byp_rs1_mux2_sel_usemux1),
|
758 |
|
|
.ecl_byp_rs1_mux1_sel_m(ecl_byp_rs1_mux1_sel_m),
|
759 |
|
|
.ecl_byp_rs1_mux1_sel_w(ecl_byp_rs1_mux1_sel_w),
|
760 |
|
|
.ecl_byp_rs1_mux1_sel_w2(ecl_byp_rs1_mux1_sel_w2),
|
761 |
|
|
.ecl_byp_rs1_mux1_sel_other(ecl_byp_rs1_mux1_sel_other),
|
762 |
|
|
.ecl_byp_rcc_mux2_sel_e(ecl_byp_rcc_mux2_sel_e),
|
763 |
|
|
.ecl_byp_rcc_mux2_sel_rf(ecl_byp_rcc_mux2_sel_rf),
|
764 |
|
|
.ecl_byp_rcc_mux2_sel_ld(ecl_byp_rcc_mux2_sel_ld),
|
765 |
|
|
.ecl_byp_rcc_mux2_sel_usemux1(ecl_byp_rcc_mux2_sel_usemux1),
|
766 |
|
|
.ecl_byp_rcc_mux1_sel_m(ecl_byp_rcc_mux1_sel_m),
|
767 |
|
|
.ecl_byp_rcc_mux1_sel_w(ecl_byp_rcc_mux1_sel_w),
|
768 |
|
|
.ecl_byp_rcc_mux1_sel_w2(ecl_byp_rcc_mux1_sel_w2),
|
769 |
|
|
.ecl_byp_rcc_mux1_sel_other(ecl_byp_rcc_mux1_sel_other),
|
770 |
|
|
.ecl_byp_rs2_mux2_sel_e(ecl_byp_rs2_mux2_sel_e),
|
771 |
|
|
.ecl_byp_rs2_mux2_sel_rf(ecl_byp_rs2_mux2_sel_rf),
|
772 |
|
|
.ecl_byp_rs2_mux2_sel_ld(ecl_byp_rs2_mux2_sel_ld),
|
773 |
|
|
.ecl_byp_rs2_mux2_sel_usemux1(ecl_byp_rs2_mux2_sel_usemux1),
|
774 |
|
|
.ecl_byp_rs2_mux1_sel_m(ecl_byp_rs2_mux1_sel_m),
|
775 |
|
|
.ecl_byp_rs2_mux1_sel_w(ecl_byp_rs2_mux1_sel_w),
|
776 |
|
|
.ecl_byp_rs2_mux1_sel_w2(ecl_byp_rs2_mux1_sel_w2),
|
777 |
|
|
.ecl_byp_rs2_mux1_sel_other(ecl_byp_rs2_mux1_sel_other),
|
778 |
|
|
.ecl_byp_rs3_mux2_sel_e(ecl_byp_rs3_mux2_sel_e),
|
779 |
|
|
.ecl_byp_rs3_mux2_sel_rf(ecl_byp_rs3_mux2_sel_rf),
|
780 |
|
|
.ecl_byp_rs3_mux2_sel_ld(ecl_byp_rs3_mux2_sel_ld),
|
781 |
|
|
.ecl_byp_rs3_mux2_sel_usemux1(ecl_byp_rs3_mux2_sel_usemux1),
|
782 |
|
|
.ecl_byp_rs3_mux1_sel_m(ecl_byp_rs3_mux1_sel_m),
|
783 |
|
|
.ecl_byp_rs3_mux1_sel_w(ecl_byp_rs3_mux1_sel_w),
|
784 |
|
|
.ecl_byp_rs3_mux1_sel_w2(ecl_byp_rs3_mux1_sel_w2),
|
785 |
|
|
.ecl_byp_rs3_mux1_sel_other(ecl_byp_rs3_mux1_sel_other),
|
786 |
|
|
.ecl_byp_rs3h_mux2_sel_e(ecl_byp_rs3h_mux2_sel_e),
|
787 |
|
|
.ecl_byp_rs3h_mux2_sel_rf(ecl_byp_rs3h_mux2_sel_rf),
|
788 |
|
|
.ecl_byp_rs3h_mux2_sel_ld(ecl_byp_rs3h_mux2_sel_ld),
|
789 |
|
|
.ecl_byp_rs3h_mux2_sel_usemux1(ecl_byp_rs3h_mux2_sel_usemux1),
|
790 |
|
|
.ecl_byp_rs3h_mux1_sel_m(ecl_byp_rs3h_mux1_sel_m),
|
791 |
|
|
.ecl_byp_rs3h_mux1_sel_w(ecl_byp_rs3h_mux1_sel_w),
|
792 |
|
|
.ecl_byp_rs3h_mux1_sel_w2(ecl_byp_rs3h_mux1_sel_w2),
|
793 |
|
|
.ecl_byp_rs3h_mux1_sel_other(ecl_byp_rs3h_mux1_sel_other),
|
794 |
|
|
.ecl_byp_rs1_longmux_sel_g2(ecl_byp_rs1_longmux_sel_g2),
|
795 |
|
|
.ecl_byp_rs1_longmux_sel_w2(ecl_byp_rs1_longmux_sel_w2),
|
796 |
|
|
.ecl_byp_rs1_longmux_sel_ldxa(ecl_byp_rs1_longmux_sel_ldxa),
|
797 |
|
|
.ecl_byp_rs2_longmux_sel_g2(ecl_byp_rs2_longmux_sel_g2),
|
798 |
|
|
.ecl_byp_rs2_longmux_sel_w2(ecl_byp_rs2_longmux_sel_w2),
|
799 |
|
|
.ecl_byp_rs2_longmux_sel_ldxa(ecl_byp_rs2_longmux_sel_ldxa),
|
800 |
|
|
.ecl_byp_rs3_longmux_sel_g2(ecl_byp_rs3_longmux_sel_g2),
|
801 |
|
|
.ecl_byp_rs3_longmux_sel_w2(ecl_byp_rs3_longmux_sel_w2),
|
802 |
|
|
.ecl_byp_rs3_longmux_sel_ldxa(ecl_byp_rs3_longmux_sel_ldxa),
|
803 |
|
|
.ecl_byp_rs3h_longmux_sel_g2(ecl_byp_rs3h_longmux_sel_g2),
|
804 |
|
|
.ecl_byp_rs3h_longmux_sel_w2(ecl_byp_rs3h_longmux_sel_w2),
|
805 |
|
|
.ecl_byp_rs3h_longmux_sel_ldxa(ecl_byp_rs3h_longmux_sel_ldxa),
|
806 |
|
|
.ecl_byp_std_e_l (ecl_byp_std_e_l),
|
807 |
|
|
.ecl_byp_ldxa_g (ecl_byp_ldxa_g),
|
808 |
|
|
.ecl_byp_3lsb_m (ecl_byp_3lsb_m[2:0]),
|
809 |
|
|
.ecl_ecc_rs1_use_rf_e(ecl_ecc_rs1_use_rf_e),
|
810 |
|
|
.ecl_ecc_rs2_use_rf_e(ecl_ecc_rs2_use_rf_e),
|
811 |
|
|
.ecl_ecc_rs3_use_rf_e(ecl_ecc_rs3_use_rf_e),
|
812 |
|
|
.ecl_irf_rd_m (ecl_irf_rd_m[4:0]),
|
813 |
|
|
.ecl_irf_tid_m (ecl_irf_tid_m[1:0]),
|
814 |
|
|
.ecl_irf_wen_w (ecl_irf_wen_w),
|
815 |
|
|
.ecl_irf_wen_w2 (ecl_irf_wen_w2),
|
816 |
|
|
.ecl_irf_rd_g (ecl_irf_rd_g[4:0]),
|
817 |
|
|
.ecl_irf_tid_g (ecl_irf_tid_g[1:0]),
|
818 |
|
|
.ecl_div_thr_e (ecl_div_thr_e[3:0]),
|
819 |
|
|
.ecl_rml_thr_m (ecl_rml_thr_m[3:0]),
|
820 |
|
|
.ecl_rml_thr_w (ecl_rml_thr_w[3:0]),
|
821 |
|
|
.ecl_rml_xor_data_e(ecl_rml_xor_data_e[2:0]),
|
822 |
|
|
.ecl_div_ld_inputs (ecl_div_ld_inputs),
|
823 |
|
|
.ecl_div_sel_div (ecl_div_sel_div),
|
824 |
|
|
.ecl_div_div64 (ecl_div_div64),
|
825 |
|
|
.exu_ifu_cc_d (exu_ifu_cc_d[7:0]),
|
826 |
|
|
.ecl_shft_extendbit_e(ecl_shft_extendbit_e),
|
827 |
|
|
.ecl_shft_extend32bit_e_l(ecl_shft_extend32bit_e_l),
|
828 |
|
|
.ecl_div_zero_rs2_e(ecl_div_zero_rs2_e),
|
829 |
|
|
.ecl_div_muls_rs1_31_e_l(ecl_div_muls_rs1_31_e_l),
|
830 |
|
|
.ecl_div_yreg_data_31_g(ecl_div_yreg_data_31_g),
|
831 |
|
|
.exu_tlu_va_oor_m (exu_tlu_va_oor_m),
|
832 |
|
|
.exu_tlu_va_oor_jl_ret_m(exu_tlu_va_oor_jl_ret_m),
|
833 |
|
|
.ecl_rml_kill_e (ecl_rml_kill_e),
|
834 |
|
|
.ecl_rml_kill_w (ecl_rml_kill_w),
|
835 |
|
|
.ecl_byp_sel_ecc_m (ecl_byp_sel_ecc_m),
|
836 |
|
|
.exu_tlu_ttype_m (exu_tlu_ttype_m[8:0]),
|
837 |
|
|
.exu_tlu_ttype_vld_m(exu_tlu_ttype_vld_m),
|
838 |
|
|
.exu_tlu_ue_trap_m (exu_tlu_ue_trap_m),
|
839 |
|
|
.exu_tlu_misalign_addr_jmpl_rtn_m(exu_tlu_misalign_addr_jmpl_rtn_m),
|
840 |
|
|
.exu_lsu_priority_trap_m(exu_lsu_priority_trap_m),
|
841 |
|
|
.ecl_div_mul_wen (ecl_div_mul_wen),
|
842 |
|
|
.ecl_div_muls (ecl_div_muls),
|
843 |
|
|
.ecl_rml_early_flush_w(ecl_rml_early_flush_w),
|
844 |
|
|
.ecl_rml_inst_vld_w(ecl_rml_inst_vld_w),
|
845 |
|
|
// Inputs
|
846 |
|
|
.div_ecl_adder_out_31(div_ecl_adder_out_31),
|
847 |
|
|
.div_ecl_cout32 (div_ecl_cout32),
|
848 |
|
|
.div_ecl_cout64 (div_ecl_cout64),
|
849 |
|
|
.div_ecl_d_62 (div_ecl_d_62),
|
850 |
|
|
.div_ecl_d_msb (div_ecl_d_msb),
|
851 |
|
|
.div_ecl_detect_zero_high(div_ecl_detect_zero_high),
|
852 |
|
|
.div_ecl_detect_zero_low(div_ecl_detect_zero_low),
|
853 |
|
|
.div_ecl_dividend_msb(div_ecl_dividend_msb),
|
854 |
|
|
.div_ecl_gencc_in_31(div_ecl_gencc_in_31),
|
855 |
|
|
.div_ecl_gencc_in_msb_l(div_ecl_gencc_in_msb_l),
|
856 |
|
|
.div_ecl_low32_nonzero(div_ecl_low32_nonzero),
|
857 |
|
|
.div_ecl_upper32_equal(div_ecl_upper32_equal),
|
858 |
|
|
.div_ecl_x_msb (div_ecl_x_msb),
|
859 |
|
|
.div_ecl_xin_msb_l (div_ecl_xin_msb_l),
|
860 |
|
|
.ecc_ecl_rs1_ce (ecc_ecl_rs1_ce),
|
861 |
|
|
.ecc_ecl_rs1_ue (ecc_ecl_rs1_ue),
|
862 |
|
|
.ecc_ecl_rs2_ce (ecc_ecl_rs2_ce),
|
863 |
|
|
.ecc_ecl_rs2_ue (ecc_ecl_rs2_ue),
|
864 |
|
|
.ecc_ecl_rs3_ce (ecc_ecl_rs3_ce),
|
865 |
|
|
.ecc_ecl_rs3_ue (ecc_ecl_rs3_ue),
|
866 |
|
|
.ifu_exu_disable_ce_e(ifu_exu_disable_ce_e),
|
867 |
|
|
.ifu_exu_ecc_mask (ifu_exu_ecc_mask[7:0]),
|
868 |
|
|
.ifu_exu_inj_irferr(ifu_exu_inj_irferr),
|
869 |
|
|
.ifu_exu_inst_vld_e(ifu_exu_inst_vld_e),
|
870 |
|
|
.ifu_exu_inst_vld_w(ifu_exu_inst_vld_w),
|
871 |
|
|
.ifu_exu_muldivop_d(ifu_exu_muldivop_d[4:0]),
|
872 |
|
|
.ifu_exu_return_d (ifu_exu_return_d),
|
873 |
|
|
.ifu_tlu_sraddr_d (ifu_tlu_sraddr_d[6:0]),
|
874 |
|
|
.ifu_tlu_wsr_inst_d(ifu_tlu_wsr_inst_d),
|
875 |
|
|
.lsu_exu_ldst_miss_g2(lsu_exu_ldst_miss_g2),
|
876 |
|
|
.mul_exu_ack (mul_exu_ack),
|
877 |
|
|
.rml_ecl_canrestore_d(rml_ecl_canrestore_d[2:0]),
|
878 |
|
|
.rml_ecl_cansave_d (rml_ecl_cansave_d[2:0]),
|
879 |
|
|
.rml_ecl_cleanwin_d(rml_ecl_cleanwin_d[2:0]),
|
880 |
|
|
.rml_ecl_cwp_d (rml_ecl_cwp_d[2:0]),
|
881 |
|
|
.rml_ecl_gl_e (rml_ecl_gl_e[1:0]),
|
882 |
|
|
.rml_ecl_kill_m (rml_ecl_kill_m),
|
883 |
|
|
.rml_ecl_otherwin_d(rml_ecl_otherwin_d[2:0]),
|
884 |
|
|
.rml_ecl_rmlop_done_e(rml_ecl_rmlop_done_e),
|
885 |
|
|
.rml_ecl_swap_done (rml_ecl_swap_done[3:0]),
|
886 |
|
|
.rml_ecl_wstate_d (rml_ecl_wstate_d[5:0]),
|
887 |
|
|
.sehold (sehold),
|
888 |
|
|
.tlu_exu_ccr_m (tlu_exu_ccr_m[7:0]),
|
889 |
|
|
.tlu_exu_cwpccr_update_m(tlu_exu_cwpccr_update_m),
|
890 |
|
|
.rclk (rclk),
|
891 |
|
|
.se (se),
|
892 |
|
|
.grst_l (grst_l),
|
893 |
|
|
.arst_l (arst_l),
|
894 |
|
|
.ifu_exu_dbrinst_d (ifu_exu_dbrinst_d),
|
895 |
|
|
.ifu_exu_aluop_d (ifu_exu_aluop_d[2:0]),
|
896 |
|
|
.ifu_exu_shiftop_d (ifu_exu_shiftop_d[2:0]),
|
897 |
|
|
.ifu_exu_invert_d (ifu_exu_invert_d),
|
898 |
|
|
.ifu_exu_usecin_d (ifu_exu_usecin_d),
|
899 |
|
|
.ifu_exu_enshift_d (ifu_exu_enshift_d),
|
900 |
|
|
.byp_ecl_rs2_3_0_e (byp_ecl_rs2_3_0_e[3:0]),
|
901 |
|
|
.byp_ecl_rs1_2_0_e (byp_ecl_rs1_2_0_e[2:0]),
|
902 |
|
|
.ifu_exu_use_rsr_e_l(ifu_exu_use_rsr_e_l),
|
903 |
|
|
.ifu_exu_rd_exusr_e(ifu_exu_rd_exusr_e),
|
904 |
|
|
.ifu_exu_rd_ifusr_e(ifu_exu_rd_ifusr_e),
|
905 |
|
|
.ifu_exu_rd_ffusr_e(ifu_exu_rd_ffusr_e),
|
906 |
|
|
.ifu_exu_rs1_vld_d (ifu_exu_rs1_vld_d),
|
907 |
|
|
.ifu_exu_rs2_vld_d (ifu_exu_rs2_vld_d),
|
908 |
|
|
.ifu_exu_rs3e_vld_d(ifu_exu_rs3e_vld_d),
|
909 |
|
|
.ifu_exu_rs3o_vld_d(ifu_exu_rs3o_vld_d),
|
910 |
|
|
.ifu_exu_dontmv_regz0_e(ifu_exu_dontmv_regz0_e),
|
911 |
|
|
.ifu_exu_dontmv_regz1_e(ifu_exu_dontmv_regz1_e),
|
912 |
|
|
.ifu_exu_rd_d (ifu_exu_rd_d[4:0]),
|
913 |
|
|
.ifu_exu_tid_s2 (ifu_exu_tid_s2[1:0]),
|
914 |
|
|
.ifu_exu_kill_e (ifu_exu_kill_e),
|
915 |
|
|
.ifu_exu_wen_d (ifu_exu_wen_d),
|
916 |
|
|
.ifu_exu_ialign_d (ifu_exu_ialign_d),
|
917 |
|
|
.alu_ecl_add_n64_e (alu_ecl_add_n64_e),
|
918 |
|
|
.alu_ecl_add_n32_e (alu_ecl_add_n32_e),
|
919 |
|
|
.alu_ecl_log_n64_e (alu_ecl_log_n64_e),
|
920 |
|
|
.alu_ecl_log_n32_e (alu_ecl_log_n32_e),
|
921 |
|
|
.alu_ecl_zhigh_e (alu_ecl_zhigh_e),
|
922 |
|
|
.alu_ecl_zlow_e (alu_ecl_zlow_e),
|
923 |
|
|
.ifu_exu_setcc_d (ifu_exu_setcc_d),
|
924 |
|
|
.lsu_exu_dfill_vld_g(lsu_exu_dfill_vld_g),
|
925 |
|
|
.lsu_exu_rd_m (lsu_exu_rd_m[4:0]),
|
926 |
|
|
.lsu_exu_thr_m (lsu_exu_thr_m[1:0]),
|
927 |
|
|
.lsu_exu_ldxa_m (lsu_exu_ldxa_m),
|
928 |
|
|
.byp_ecl_rs1_31_e (byp_ecl_rs1_31_e),
|
929 |
|
|
.byp_ecl_rs2_31_e (byp_ecl_rs2_31_e),
|
930 |
|
|
.byp_ecl_rs1_63_e (byp_ecl_rs1_63_e),
|
931 |
|
|
.alu_ecl_cout64_e_l(alu_ecl_cout64_e_l),
|
932 |
|
|
.alu_ecl_cout32_e (alu_ecl_cout32_e),
|
933 |
|
|
.alu_ecl_adder_out_63_e(alu_ecl_adder_out_63_e),
|
934 |
|
|
.alu_ecl_adderin2_63_e(alu_ecl_adderin2_63_e),
|
935 |
|
|
.alu_ecl_adderin2_31_e(alu_ecl_adderin2_31_e),
|
936 |
|
|
.ifu_exu_rs1_s (ifu_exu_rs1_s[4:0]),
|
937 |
|
|
.ifu_exu_rs2_s (ifu_exu_rs2_s[4:0]),
|
938 |
|
|
.ifu_exu_rs3_s (ifu_exu_rs3_s[4:0]),
|
939 |
|
|
.ifu_exu_tagop_d (ifu_exu_tagop_d),
|
940 |
|
|
.ifu_exu_tv_d (ifu_exu_tv_d),
|
941 |
|
|
.ifu_exu_muls_d (ifu_exu_muls_d),
|
942 |
|
|
.div_ecl_yreg_0_l (div_ecl_yreg_0_l[3:0]),
|
943 |
|
|
.alu_ecl_mem_addr_invalid_e_l(alu_ecl_mem_addr_invalid_e_l),
|
944 |
|
|
.ifu_exu_range_check_jlret_d(ifu_exu_range_check_jlret_d),
|
945 |
|
|
.ifu_exu_range_check_other_d(ifu_exu_range_check_other_d),
|
946 |
|
|
.ifu_exu_addr_mask_d(ifu_exu_addr_mask_d),
|
947 |
|
|
.ifu_exu_save_d (ifu_exu_save_d),
|
948 |
|
|
.ifu_exu_restore_d (ifu_exu_restore_d),
|
949 |
|
|
.ifu_exu_casa_d (ifu_exu_casa_d),
|
950 |
|
|
.rml_ecl_clean_window_e(rml_ecl_clean_window_e),
|
951 |
|
|
.rml_ecl_fill_e (rml_ecl_fill_e),
|
952 |
|
|
.rml_ecl_other_e (rml_ecl_other_e),
|
953 |
|
|
.rml_ecl_wtype_e (rml_ecl_wtype_e[2:0]),
|
954 |
|
|
.ifu_exu_tcc_e (ifu_exu_tcc_e),
|
955 |
|
|
.ifu_exu_useimm_d (ifu_exu_useimm_d),
|
956 |
|
|
.ifu_exu_nceen_e (ifu_exu_nceen_e),
|
957 |
|
|
.ifu_tlu_flush_m (ifu_tlu_flush_m),
|
958 |
|
|
.ifu_exu_ttype_vld_m(ifu_exu_ttype_vld_m),
|
959 |
|
|
.tlu_exu_priv_trap_m(tlu_exu_priv_trap_m),
|
960 |
|
|
.tlu_exu_pic_onebelow_m(tlu_exu_pic_onebelow_m),
|
961 |
|
|
.tlu_exu_pic_twobelow_m(tlu_exu_pic_twobelow_m),
|
962 |
|
|
.lsu_exu_flush_pipe_w(lsu_exu_flush_pipe_w),
|
963 |
|
|
.ifu_exu_sethi_inst_d(ifu_exu_sethi_inst_d),
|
964 |
|
|
.lsu_exu_st_dtlb_perr_g(lsu_exu_st_dtlb_perr_g));
|
965 |
|
|
|
966 |
|
|
sparc_exu_alu alu(
|
967 |
|
|
.byp_alu_rs3_data_e(exu_lsu_rs3_data_e[63:0]),
|
968 |
|
|
.so (scan0_2),
|
969 |
|
|
.si (scan0_1),
|
970 |
|
|
.ifu_lsu_casa_e (ecl_alu_casa_e),
|
971 |
|
|
/*AUTOINST*/
|
972 |
|
|
// Outputs
|
973 |
|
|
.alu_byp_rd_data_e (alu_byp_rd_data_e[63:0]),
|
974 |
|
|
.exu_ifu_brpc_e (exu_ifu_brpc_e[47:0]),
|
975 |
|
|
.exu_lsu_ldst_va_e (exu_lsu_ldst_va_e[47:0]),
|
976 |
|
|
.exu_lsu_early_va_e(exu_lsu_early_va_e[10:3]),
|
977 |
|
|
.exu_mmu_early_va_e(exu_mmu_early_va_e[7:0]),
|
978 |
|
|
.alu_ecl_add_n64_e (alu_ecl_add_n64_e),
|
979 |
|
|
.alu_ecl_add_n32_e (alu_ecl_add_n32_e),
|
980 |
|
|
.alu_ecl_log_n64_e (alu_ecl_log_n64_e),
|
981 |
|
|
.alu_ecl_log_n32_e (alu_ecl_log_n32_e),
|
982 |
|
|
.alu_ecl_zhigh_e (alu_ecl_zhigh_e),
|
983 |
|
|
.alu_ecl_zlow_e (alu_ecl_zlow_e),
|
984 |
|
|
.exu_ifu_regz_e (exu_ifu_regz_e),
|
985 |
|
|
.exu_ifu_regn_e (exu_ifu_regn_e),
|
986 |
|
|
.alu_ecl_adderin2_63_e(alu_ecl_adderin2_63_e),
|
987 |
|
|
.alu_ecl_adderin2_31_e(alu_ecl_adderin2_31_e),
|
988 |
|
|
.alu_ecl_adder_out_63_e(alu_ecl_adder_out_63_e),
|
989 |
|
|
.alu_ecl_cout32_e (alu_ecl_cout32_e),
|
990 |
|
|
.alu_ecl_cout64_e_l(alu_ecl_cout64_e_l),
|
991 |
|
|
.alu_ecl_mem_addr_invalid_e_l(alu_ecl_mem_addr_invalid_e_l),
|
992 |
|
|
// Inputs
|
993 |
|
|
.rclk (rclk),
|
994 |
|
|
.se (se),
|
995 |
|
|
.byp_alu_rs1_data_e(byp_alu_rs1_data_e[63:0]),
|
996 |
|
|
.byp_alu_rs2_data_e_l(byp_alu_rs2_data_e_l[63:0]),
|
997 |
|
|
.byp_alu_rcc_data_e(byp_alu_rcc_data_e[63:0]),
|
998 |
|
|
.ecl_alu_cin_e (ecl_alu_cin_e),
|
999 |
|
|
.ifu_exu_invert_d (ifu_exu_invert_d),
|
1000 |
|
|
.ecl_alu_log_sel_and_e(ecl_alu_log_sel_and_e),
|
1001 |
|
|
.ecl_alu_log_sel_or_e(ecl_alu_log_sel_or_e),
|
1002 |
|
|
.ecl_alu_log_sel_xor_e(ecl_alu_log_sel_xor_e),
|
1003 |
|
|
.ecl_alu_log_sel_move_e(ecl_alu_log_sel_move_e),
|
1004 |
|
|
.ecl_alu_out_sel_sum_e_l(ecl_alu_out_sel_sum_e_l),
|
1005 |
|
|
.ecl_alu_out_sel_rs3_e_l(ecl_alu_out_sel_rs3_e_l),
|
1006 |
|
|
.ecl_alu_out_sel_shift_e_l(ecl_alu_out_sel_shift_e_l),
|
1007 |
|
|
.ecl_alu_out_sel_logic_e_l(ecl_alu_out_sel_logic_e_l),
|
1008 |
|
|
.shft_alu_shift_out_e(shft_alu_shift_out_e[63:0]),
|
1009 |
|
|
.ecl_alu_sethi_inst_e(ecl_alu_sethi_inst_e));
|
1010 |
|
|
sparc_exu_shft shft(/*AUTOINST*/
|
1011 |
|
|
// Outputs
|
1012 |
|
|
.shft_alu_shift_out_e(shft_alu_shift_out_e[63:0]),
|
1013 |
|
|
// Inputs
|
1014 |
|
|
.ecl_shft_lshift_e_l(ecl_shft_lshift_e_l),
|
1015 |
|
|
.ecl_shft_op32_e (ecl_shft_op32_e),
|
1016 |
|
|
.ecl_shft_shift4_e(ecl_shft_shift4_e[3:0]),
|
1017 |
|
|
.ecl_shft_shift1_e(ecl_shft_shift1_e[3:0]),
|
1018 |
|
|
.byp_alu_rs1_data_e(byp_alu_rs1_data_e[63:0]),
|
1019 |
|
|
.byp_alu_rs2_data_e(byp_alu_rs2_data_e[5:4]),
|
1020 |
|
|
.ecl_shft_enshift_e_l(ecl_shft_enshift_e_l),
|
1021 |
|
|
.ecl_shft_extendbit_e(ecl_shft_extendbit_e),
|
1022 |
|
|
.ecl_shft_extend32bit_e_l(ecl_shft_extend32bit_e_l));
|
1023 |
|
|
|
1024 |
|
|
sparc_exu_div div(
|
1025 |
|
|
.so (scan0_3),
|
1026 |
|
|
.si (scan0_2),
|
1027 |
|
|
.byp_div_rs1_data_e(byp_alu_rs1_data_e[63:0]),
|
1028 |
|
|
.byp_div_rs2_data_e(byp_alu_rs2_data_e[63:0]),
|
1029 |
|
|
.byp_div_yreg_data_w(byp_irf_rd_data_w[31:0]),
|
1030 |
|
|
/*AUTOINST*/
|
1031 |
|
|
// Outputs
|
1032 |
|
|
.div_ecl_xin_msb_l (div_ecl_xin_msb_l),
|
1033 |
|
|
.div_ecl_x_msb (div_ecl_x_msb),
|
1034 |
|
|
.div_ecl_d_msb (div_ecl_d_msb),
|
1035 |
|
|
.div_ecl_cout64 (div_ecl_cout64),
|
1036 |
|
|
.div_ecl_cout32 (div_ecl_cout32),
|
1037 |
|
|
.div_ecl_gencc_in_msb_l(div_ecl_gencc_in_msb_l),
|
1038 |
|
|
.div_ecl_gencc_in_31(div_ecl_gencc_in_31),
|
1039 |
|
|
.div_ecl_upper32_equal(div_ecl_upper32_equal),
|
1040 |
|
|
.div_ecl_low32_nonzero(div_ecl_low32_nonzero),
|
1041 |
|
|
.div_ecl_dividend_msb(div_ecl_dividend_msb),
|
1042 |
|
|
.div_byp_muldivout_g(div_byp_muldivout_g[63:0]),
|
1043 |
|
|
.div_byp_yreg_e (div_byp_yreg_e[31:0]),
|
1044 |
|
|
.div_ecl_yreg_0_l (div_ecl_yreg_0_l[3:0]),
|
1045 |
|
|
.exu_mul_rs1_data (exu_mul_rs1_data[63:0]),
|
1046 |
|
|
.exu_mul_rs2_data (exu_mul_rs2_data[63:0]),
|
1047 |
|
|
.div_ecl_adder_out_31(div_ecl_adder_out_31),
|
1048 |
|
|
.div_ecl_detect_zero_low(div_ecl_detect_zero_low),
|
1049 |
|
|
.div_ecl_detect_zero_high(div_ecl_detect_zero_high),
|
1050 |
|
|
.div_ecl_d_62 (div_ecl_d_62),
|
1051 |
|
|
// Inputs
|
1052 |
|
|
.ecl_div_thr_e (ecl_div_thr_e[3:0]),
|
1053 |
|
|
.ecl_div_yreg_data_31_g(ecl_div_yreg_data_31_g),
|
1054 |
|
|
.ecl_div_yreg_shift_g(ecl_div_yreg_shift_g[3:0]),
|
1055 |
|
|
.ecl_div_yreg_wen_g(ecl_div_yreg_wen_g[3:0]),
|
1056 |
|
|
.ecl_div_yreg_wen_l(ecl_div_yreg_wen_l[3:0]),
|
1057 |
|
|
.ecl_div_yreg_wen_w(ecl_div_yreg_wen_w[3:0]),
|
1058 |
|
|
.rclk (rclk),
|
1059 |
|
|
.se (se),
|
1060 |
|
|
.ecl_div_keep_d (ecl_div_keep_d),
|
1061 |
|
|
.ecl_div_ld_inputs (ecl_div_ld_inputs),
|
1062 |
|
|
.ecl_div_sel_adder (ecl_div_sel_adder),
|
1063 |
|
|
.ecl_div_last_cycle(ecl_div_last_cycle),
|
1064 |
|
|
.ecl_div_almostlast_cycle(ecl_div_almostlast_cycle),
|
1065 |
|
|
.ecl_div_div64 (ecl_div_div64),
|
1066 |
|
|
.ecl_div_sel_u32 (ecl_div_sel_u32),
|
1067 |
|
|
.ecl_div_sel_pos32 (ecl_div_sel_pos32),
|
1068 |
|
|
.ecl_div_sel_neg32 (ecl_div_sel_neg32),
|
1069 |
|
|
.ecl_div_sel_64b (ecl_div_sel_64b),
|
1070 |
|
|
.ecl_div_upper32_zero(ecl_div_upper32_zero),
|
1071 |
|
|
.ecl_div_upper33_one(ecl_div_upper33_one),
|
1072 |
|
|
.ecl_div_upper33_zero(ecl_div_upper33_zero),
|
1073 |
|
|
.mul_exu_data_g (mul_exu_data_g[63:0]),
|
1074 |
|
|
.ecl_div_sel_div (ecl_div_sel_div),
|
1075 |
|
|
.ecl_div_mul_wen (ecl_div_mul_wen),
|
1076 |
|
|
.ecl_div_dividend_sign(ecl_div_dividend_sign),
|
1077 |
|
|
.ecl_div_subtract_l(ecl_div_subtract_l),
|
1078 |
|
|
.ecl_div_cin (ecl_div_cin),
|
1079 |
|
|
.ecl_div_newq (ecl_div_newq),
|
1080 |
|
|
.ecl_div_xinmask (ecl_div_xinmask),
|
1081 |
|
|
.ecl_div_keepx (ecl_div_keepx),
|
1082 |
|
|
.ecl_div_mul_get_new_data(ecl_div_mul_get_new_data),
|
1083 |
|
|
.ecl_div_mul_keep_data(ecl_div_mul_keep_data),
|
1084 |
|
|
.ecl_div_mul_get_32bit_data(ecl_div_mul_get_32bit_data),
|
1085 |
|
|
.ecl_div_mul_sext_rs2_e(ecl_div_mul_sext_rs2_e),
|
1086 |
|
|
.ecl_div_mul_sext_rs1_e(ecl_div_mul_sext_rs1_e),
|
1087 |
|
|
.ecl_div_muls_rs1_31_e_l(ecl_div_muls_rs1_31_e_l),
|
1088 |
|
|
.ecl_div_muls (ecl_div_muls),
|
1089 |
|
|
.ecl_div_zero_rs2_e(ecl_div_zero_rs2_e));
|
1090 |
|
|
|
1091 |
|
|
sparc_exu_rml rml(
|
1092 |
|
|
.so (so0),
|
1093 |
|
|
.si (scan0_3),
|
1094 |
|
|
.rst_tri_en (mux_drive_disable),
|
1095 |
|
|
.exu_tlu_wsr_data_w(byp_irf_rd_data_w[5:0]),
|
1096 |
|
|
.rml_irf_old_e_cwp_e(rml_irf_old_e_cwp_e[1:0]),
|
1097 |
|
|
.rml_irf_new_e_cwp_e(rml_irf_new_e_cwp_e[1:0]),
|
1098 |
|
|
/*AUTOINST*/
|
1099 |
|
|
// Outputs
|
1100 |
|
|
.exu_tlu_cwp0_w (exu_tlu_cwp0_w[2:0]),
|
1101 |
|
|
.exu_tlu_cwp1_w (exu_tlu_cwp1_w[2:0]),
|
1102 |
|
|
.exu_tlu_cwp2_w (exu_tlu_cwp2_w[2:0]),
|
1103 |
|
|
.exu_tlu_cwp3_w (exu_tlu_cwp3_w[2:0]),
|
1104 |
|
|
.exu_tlu_cwp_retry (exu_tlu_cwp_retry),
|
1105 |
|
|
.exu_tlu_spill_other(exu_tlu_spill_other),
|
1106 |
|
|
.exu_tlu_spill_wtype(exu_tlu_spill_wtype[2:0]),
|
1107 |
|
|
.exu_tlu_cwp_cmplt (exu_tlu_cwp_cmplt),
|
1108 |
|
|
.exu_tlu_cwp_cmplt_tid(exu_tlu_cwp_cmplt_tid[1:0]),
|
1109 |
|
|
.rml_ecl_cwp_d (rml_ecl_cwp_d[2:0]),
|
1110 |
|
|
.rml_ecl_cansave_d (rml_ecl_cansave_d[2:0]),
|
1111 |
|
|
.rml_ecl_canrestore_d(rml_ecl_canrestore_d[2:0]),
|
1112 |
|
|
.rml_ecl_otherwin_d(rml_ecl_otherwin_d[2:0]),
|
1113 |
|
|
.rml_ecl_wstate_d (rml_ecl_wstate_d[5:0]),
|
1114 |
|
|
.rml_ecl_cleanwin_d(rml_ecl_cleanwin_d[2:0]),
|
1115 |
|
|
.rml_ecl_fill_e (rml_ecl_fill_e),
|
1116 |
|
|
.rml_ecl_clean_window_e(rml_ecl_clean_window_e),
|
1117 |
|
|
.rml_ecl_other_e (rml_ecl_other_e),
|
1118 |
|
|
.rml_ecl_wtype_e (rml_ecl_wtype_e[2:0]),
|
1119 |
|
|
.exu_ifu_spill_e (exu_ifu_spill_e),
|
1120 |
|
|
.rml_ecl_gl_e (rml_ecl_gl_e[1:0]),
|
1121 |
|
|
.rml_irf_old_lo_cwp_e(rml_irf_old_lo_cwp_e[2:0]),
|
1122 |
|
|
.rml_irf_new_lo_cwp_e(rml_irf_new_lo_cwp_e[2:0]),
|
1123 |
|
|
.rml_irf_swap_even_e(rml_irf_swap_even_e),
|
1124 |
|
|
.rml_irf_swap_odd_e(rml_irf_swap_odd_e),
|
1125 |
|
|
.rml_irf_swap_local_e(rml_irf_swap_local_e),
|
1126 |
|
|
.rml_irf_kill_restore_w(rml_irf_kill_restore_w),
|
1127 |
|
|
.rml_irf_cwpswap_tid_e(rml_irf_cwpswap_tid_e[1:0]),
|
1128 |
|
|
.rml_ecl_swap_done (rml_ecl_swap_done[3:0]),
|
1129 |
|
|
.rml_ecl_rmlop_done_e(rml_ecl_rmlop_done_e),
|
1130 |
|
|
.exu_ifu_oddwin_s (exu_ifu_oddwin_s[3:0]),
|
1131 |
|
|
.exu_tlu_spill (exu_tlu_spill),
|
1132 |
|
|
.exu_tlu_spill_tid (exu_tlu_spill_tid[1:0]),
|
1133 |
|
|
.rml_ecl_kill_m (rml_ecl_kill_m),
|
1134 |
|
|
.rml_irf_old_agp (rml_irf_old_agp[1:0]),
|
1135 |
|
|
.rml_irf_new_agp (rml_irf_new_agp[1:0]),
|
1136 |
|
|
.rml_irf_swap_global(rml_irf_swap_global),
|
1137 |
|
|
.rml_irf_global_tid(rml_irf_global_tid[1:0]),
|
1138 |
|
|
// Inputs
|
1139 |
|
|
.rclk (rclk),
|
1140 |
|
|
.se (se),
|
1141 |
|
|
.grst_l (grst_l),
|
1142 |
|
|
.arst_l (arst_l),
|
1143 |
|
|
.ifu_exu_tid_s2 (ifu_exu_tid_s2[1:0]),
|
1144 |
|
|
.ifu_exu_save_d (ifu_exu_save_d),
|
1145 |
|
|
.ifu_exu_restore_d (ifu_exu_restore_d),
|
1146 |
|
|
.ifu_exu_saved_e (ifu_exu_saved_e),
|
1147 |
|
|
.ifu_exu_restored_e(ifu_exu_restored_e),
|
1148 |
|
|
.ifu_exu_flushw_e (ifu_exu_flushw_e),
|
1149 |
|
|
.ecl_rml_thr_m (ecl_rml_thr_m[3:0]),
|
1150 |
|
|
.ecl_rml_thr_w (ecl_rml_thr_w[3:0]),
|
1151 |
|
|
.ecl_rml_cwp_wen_e (ecl_rml_cwp_wen_e),
|
1152 |
|
|
.ecl_rml_cansave_wen_w(ecl_rml_cansave_wen_w),
|
1153 |
|
|
.ecl_rml_canrestore_wen_w(ecl_rml_canrestore_wen_w),
|
1154 |
|
|
.ecl_rml_otherwin_wen_w(ecl_rml_otherwin_wen_w),
|
1155 |
|
|
.ecl_rml_wstate_wen_w(ecl_rml_wstate_wen_w),
|
1156 |
|
|
.ecl_rml_cleanwin_wen_w(ecl_rml_cleanwin_wen_w),
|
1157 |
|
|
.ecl_rml_xor_data_e(ecl_rml_xor_data_e[2:0]),
|
1158 |
|
|
.ecl_rml_kill_e (ecl_rml_kill_e),
|
1159 |
|
|
.ecl_rml_kill_w (ecl_rml_kill_w),
|
1160 |
|
|
.ecl_rml_early_flush_w(ecl_rml_early_flush_w),
|
1161 |
|
|
.tlu_exu_agp (tlu_exu_agp[1:0]),
|
1162 |
|
|
.tlu_exu_agp_swap (tlu_exu_agp_swap),
|
1163 |
|
|
.tlu_exu_agp_tid (tlu_exu_agp_tid[1:0]),
|
1164 |
|
|
.tlu_exu_cwp_m (tlu_exu_cwp_m[2:0]),
|
1165 |
|
|
.tlu_exu_cwpccr_update_m(tlu_exu_cwpccr_update_m),
|
1166 |
|
|
.ecl_rml_inst_vld_w(ecl_rml_inst_vld_w),
|
1167 |
|
|
.tlu_exu_cwp_retry_m(tlu_exu_cwp_retry_m));
|
1168 |
|
|
endmodule // sparc_exu
|
1169 |
|
|
// Local Variables:
|
1170 |
|
|
// verilog-library-directories:("." "../../../srams/rtl")
|
1171 |
|
|
// End:
|