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// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: sparc_exu_ecc.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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/*
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// Module Name: sparc_exu_ecc
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// Description: This block performs the ecc check and correction as well as
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// doing the w2 write port arbitration and the w2 ecc generation.
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*/
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module sparc_exu_ecc (/*AUTOARG*/
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// Outputs
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so, ecc_ecl_rs1_ce, ecc_ecl_rs1_ue, ecc_ecl_rs2_ce,
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ecc_ecl_rs2_ue, ecc_ecl_rs3_ce, ecc_ecl_rs3_ue,
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ecc_byp_ecc_result_m, exu_ifu_err_synd_m,
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// Inputs
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rclk, se, si, byp_ecc_rcc_data_e, ecl_ecc_rs1_use_rf_e,
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byp_ecc_rs1_synd_d, byp_alu_rs2_data_e, ecl_ecc_rs2_use_rf_e,
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byp_ecc_rs2_synd_d, byp_ecc_rs3_data_e, ecl_ecc_rs3_use_rf_e,
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byp_ecc_rs3_synd_d, ecl_ecc_sel_rs1_m_l, ecl_ecc_sel_rs2_m_l,
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ecl_ecc_sel_rs3_m_l, ecl_ecc_log_rs1_m, ecl_ecc_log_rs2_m,
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ecl_ecc_log_rs3_m
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) ;
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input rclk;
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input se;
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input si;
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input [63:0] byp_ecc_rcc_data_e;
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input ecl_ecc_rs1_use_rf_e;
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input [7:0] byp_ecc_rs1_synd_d;
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input [63:0] byp_alu_rs2_data_e;
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input ecl_ecc_rs2_use_rf_e;
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input [7:0] byp_ecc_rs2_synd_d;
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input [63:0] byp_ecc_rs3_data_e;
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input ecl_ecc_rs3_use_rf_e;
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input [7:0] byp_ecc_rs3_synd_d;
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input ecl_ecc_sel_rs1_m_l;
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input ecl_ecc_sel_rs2_m_l;
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input ecl_ecc_sel_rs3_m_l;
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input ecl_ecc_log_rs1_m;
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input ecl_ecc_log_rs2_m;
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input ecl_ecc_log_rs3_m;
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output so;
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output ecc_ecl_rs1_ce;
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output ecc_ecl_rs1_ue;
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output ecc_ecl_rs2_ce;
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output ecc_ecl_rs2_ue;
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output ecc_ecl_rs3_ce;
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output ecc_ecl_rs3_ue;
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output [63:0] ecc_byp_ecc_result_m;
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output [6:0] exu_ifu_err_synd_m;
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wire clk;
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wire sel_rs1_m;
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wire sel_rs2_m;
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wire sel_rs3_m;
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wire [7:0] rs1_ecc_e;
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wire [6:0] rs1_err_e; // syndrome generated by checker
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wire [6:0] rs1_err_m; // syndrome generated by checker
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wire [7:0] rs2_ecc_e;
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wire [6:0] rs2_err_e; // syndrome generated by checker
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wire [6:0] rs2_err_m; // syndrome generated by checker
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wire [7:0] rs3_ecc_e;
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wire [6:0] rs3_err_e; // syndrome generated by checker
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wire [6:0] rs3_err_m; // syndrome generated by checker
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wire [6:0] err_m;
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wire [63:0] ecc_datain_m;
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wire [63:0] byp_ecc_rcc_data_m;
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wire [63:0] byp_alu_rs2_data_m;
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wire [63:0] exu_lsu_rs3_data_m;
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wire [63:0] error_data_m;
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assign clk = rclk;
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// Pass along ecc parity bits from RF
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dff #(8) rs1_ecc_d2e(.din(byp_ecc_rs1_synd_d[7:0]), .clk(clk), .q(rs1_ecc_e[7:0]),
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.se(se), .si(), .so());
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dff #(8) rs2_ecc_d2e(.din(byp_ecc_rs2_synd_d[7:0]), .clk(clk), .q(rs2_ecc_e[7:0]),
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.se(se), .si(), .so());
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dff #(8) rs3_ecc_d2e(.din(byp_ecc_rs3_synd_d[7:0]), .clk(clk), .q(rs3_ecc_e[7:0]),
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.se(se), .si(), .so());
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// Check the ecc for all 4 outputs from RF
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zzecc_exu_chkecc2 chk_rs1(.d(byp_ecc_rcc_data_e[63:0]),
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.vld(ecl_ecc_rs1_use_rf_e),
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.p(rs1_ecc_e[7:0]),
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.q(rs1_err_e[6:0]),
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.ce(ecc_ecl_rs1_ce), .ue(ecc_ecl_rs1_ue), .ne());
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zzecc_exu_chkecc2 chk_rs2(.d(byp_alu_rs2_data_e[63:0]),
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.vld(ecl_ecc_rs2_use_rf_e),
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.p(rs2_ecc_e[7:0]),
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.q(rs2_err_e[6:0]),
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.ce(ecc_ecl_rs2_ce), .ue(ecc_ecl_rs2_ue), .ne());
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zzecc_exu_chkecc2 chk_rs3(.d(byp_ecc_rs3_data_e[63:0]),
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.vld(ecl_ecc_rs3_use_rf_e),
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.p(rs3_ecc_e[7:0]),
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.q(rs3_err_e[6:0]),
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.ce(ecc_ecl_rs3_ce), .ue(ecc_ecl_rs3_ue), .ne());
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// Put results from checkers into flops
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dff #(7) rs1_err_e2m(.din(rs1_err_e[6:0]), .clk(clk), .q(rs1_err_m[6:0]),
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.se(se), .si(), .so());
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dff #(7) rs2_err_e2m(.din(rs2_err_e[6:0]), .clk(clk), .q(rs2_err_m[6:0]),
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.se(se), .si(), .so());
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dff #(7) rs3o_err_e2m(.din(rs3_err_e[6:0]), .clk(clk), .q(rs3_err_m[6:0]),
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.se(se), .si(), .so());
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// Pass along RF data to M stage
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dff #(64) rs1_data_e2m(.din(byp_ecc_rcc_data_e[63:0]), .clk(clk), .q(byp_ecc_rcc_data_m[63:0]),
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.se(se), .si(), .so());
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dff #(64) rs2_data_e2m(.din(byp_alu_rs2_data_e[63:0]), .clk(clk), .q(byp_alu_rs2_data_m[63:0]),
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.se(se), .si(), .so());
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dff #(64) rs3_data_e2m(.din(byp_ecc_rs3_data_e[63:0]), .clk(clk),
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.q(exu_lsu_rs3_data_m[63:0]),
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.se(se), .si(), .so());
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// Mux between 3 different ports for syndrome and data
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assign sel_rs1_m = ~ecl_ecc_sel_rs1_m_l;
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assign sel_rs2_m = ~ecl_ecc_sel_rs2_m_l;
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assign sel_rs3_m = ~ecl_ecc_sel_rs3_m_l;
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mux3ds #(7) syn_mux(.dout(err_m[6:0]),
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.in0(rs1_err_m[6:0]),
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.in1(rs2_err_m[6:0]),
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.in2(rs3_err_m[6:0]),
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.sel0(sel_rs1_m),
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.sel1(sel_rs2_m),
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.sel2(sel_rs3_m));
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mux3ds #(64) data_m_mux(.dout(ecc_datain_m[63:0]),
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.in0(byp_ecc_rcc_data_m[63:0]),
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.in1(byp_alu_rs2_data_m[63:0]),
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.in2(exu_lsu_rs3_data_m[63:0]),
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.sel0(sel_rs1_m),
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.sel1(sel_rs2_m),
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.sel2(sel_rs3_m));
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mux3ds #(7) syn_log_mux(.dout(exu_ifu_err_synd_m[6:0]),
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.in0(rs1_err_m[6:0]),
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.in1(rs2_err_m[6:0]),
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.in2(rs3_err_m[6:0]),
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.sel0(ecl_ecc_log_rs1_m),
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.sel1(ecl_ecc_log_rs2_m),
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.sel2(ecl_ecc_log_rs3_m));
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// Decode syndrome from checker
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sparc_exu_ecc_dec decode(.e (error_data_m[63:0]),
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.q (err_m[6:0]));
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assign ecc_byp_ecc_result_m[63:0] = ecc_datain_m[63:0] ^ error_data_m[63:0];
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endmodule // sparc_exu_ecc
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