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95 |
fafa1971 |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: sparc_ffu.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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/*
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// Module Name: sparc_ffu
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// Description: This is the top level for the floating point frontend unit (ffu).
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// It instantiates the control (ffu_ctl), datapath (ffu_dp), and register file
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// (frf).
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*/
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113 |
albert.wat |
`include "iop.h"
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`define FPRET_CMP 69
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`define FPRET_CC_HI 68
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`define FPRET_CC_LO 67
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`define FPRET_EXC_HI 76
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`define FPRET_EXC_LO 72
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95 |
fafa1971 |
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module sparc_ffu (/*AUTOARG*/
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// Outputs
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so, ffu_tlu_trap_ue, ffu_tlu_trap_other, ffu_tlu_trap_ieee754,
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ffu_tlu_ill_inst_m, ffu_tlu_fpu_tid, ffu_tlu_fpu_cmplt,
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ffu_lsu_kill_fst_w, ffu_lsu_fpop_rq_vld, ffu_lsu_blk_st_va_e,
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ffu_lsu_blk_st_e, ffu_ifu_tid_w2, ffu_ifu_stallreq,
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ffu_ifu_inj_ack, ffu_ifu_fst_ce_w, ffu_ifu_fpop_done_w2,
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ffu_ifu_err_synd_w2, ffu_ifu_err_reg_w2, ffu_ifu_ecc_ue_w2,
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ffu_ifu_ecc_ce_w2, ffu_ifu_cc_w2, ffu_ifu_cc_vld_w2, ffu_lsu_data,
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short_so0, ffu_exu_rsr_data_m,
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// Inputs
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si, sehold, se, rclk, lsu_ffu_stb_full3, lsu_ffu_stb_full2,
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lsu_ffu_stb_full1, lsu_ffu_stb_full0, lsu_ffu_ld_vld,
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lsu_ffu_ld_data, lsu_ffu_flush_pipe_w, lsu_ffu_blk_asi_e,
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lsu_ffu_bld_cnt_w, lsu_ffu_ack, ifu_tlu_sraddr_d,
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ifu_tlu_inst_vld_w, ifu_tlu_flush_w, ifu_tlu_flsh_inst_e,
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ifu_lsu_ld_inst_e, ifu_ffu_visop_d, ifu_ffu_tid_d,
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ifu_ffu_stfsr_d, ifu_ffu_quad_op_e, ifu_ffu_mvcnd_m,
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ifu_ffu_ldxfsr_d, ifu_ffu_ldst_single_d, ifu_ffu_ldfsr_d,
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ifu_ffu_inj_frferr, ifu_ffu_fst_d, ifu_ffu_frs2_d, ifu_ffu_frs1_d,
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ifu_ffu_frd_d, ifu_ffu_fpopcode_d, ifu_ffu_fpop2_d,
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ifu_ffu_fpop1_d, ifu_ffu_fld_d, ifu_ffu_fcc_num_d,
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ifu_exu_nceen_e, ifu_exu_ecc_mask, ifu_exu_disable_ce_e, grst_l,
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exu_ffu_wsr_inst_e, exu_ffu_ist_e, exu_ffu_gsr_scale_m,
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exu_ffu_gsr_rnd_m, exu_ffu_gsr_mask_m, exu_ffu_gsr_align_m,
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cpx_vld, cpx_req, cpx_fpu_data, cpx_fpexc, cpx_fcmp, cpx_fccval,
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arst_l, mux_drive_disable, mem_write_disable, short_si0,
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//sotheas,8/17/04: eco 6529
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lsu_ffu_st_dtlb_perr_g
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//////////////////////////////////
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) ;
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output [80:0] ffu_lsu_data; // From dp of sparc_ffu_dp.v, ...
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output short_so0;
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input mux_drive_disable;
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input mem_write_disable;
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input short_si0;
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input arst_l; // To ctl of sparc_ffu_ctl.v
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input [1:0] cpx_fccval; // To ctl of sparc_ffu_ctl.v
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input cpx_fcmp; // To ctl of sparc_ffu_ctl.v
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input [4:0] cpx_fpexc; // To ctl of sparc_ffu_ctl.v
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input [63:0] cpx_fpu_data; // To dp of sparc_ffu_dp.v
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input [3:0] cpx_req; // To ctl of sparc_ffu_ctl.v
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input cpx_vld; // To ctl of sparc_ffu_ctl.v
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input [2:0] exu_ffu_gsr_align_m; // To ctl of sparc_ffu_ctl.v
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input [31:0] exu_ffu_gsr_mask_m; // To ctl of sparc_ffu_ctl.v
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input [2:0] exu_ffu_gsr_rnd_m; // To ctl of sparc_ffu_ctl.v
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input [4:0] exu_ffu_gsr_scale_m; // To ctl of sparc_ffu_ctl.v
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input exu_ffu_ist_e; // To ctl of sparc_ffu_ctl.v
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input exu_ffu_wsr_inst_e; // To ctl of sparc_ffu_ctl.v
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input grst_l; // To ctl of sparc_ffu_ctl.v
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input ifu_exu_disable_ce_e; // To ctl of sparc_ffu_ctl.v
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input [6:0] ifu_exu_ecc_mask; // To ctl of sparc_ffu_ctl.v
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input ifu_exu_nceen_e; // To ctl of sparc_ffu_ctl.v
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input [1:0] ifu_ffu_fcc_num_d; // To ctl of sparc_ffu_ctl.v
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input ifu_ffu_fld_d; // To ctl of sparc_ffu_ctl.v
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input ifu_ffu_fpop1_d; // To ctl of sparc_ffu_ctl.v
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input ifu_ffu_fpop2_d; // To ctl of sparc_ffu_ctl.v
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input [8:0] ifu_ffu_fpopcode_d; // To ctl of sparc_ffu_ctl.v
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input [4:0] ifu_ffu_frd_d; // To ctl of sparc_ffu_ctl.v
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input [4:0] ifu_ffu_frs1_d; // To ctl of sparc_ffu_ctl.v
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input [4:0] ifu_ffu_frs2_d; // To ctl of sparc_ffu_ctl.v
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input ifu_ffu_fst_d; // To ctl of sparc_ffu_ctl.v
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input ifu_ffu_inj_frferr; // To ctl of sparc_ffu_ctl.v
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input ifu_ffu_ldfsr_d; // To ctl of sparc_ffu_ctl.v
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input ifu_ffu_ldst_single_d; // To ctl of sparc_ffu_ctl.v
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input ifu_ffu_ldxfsr_d; // To ctl of sparc_ffu_ctl.v
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input ifu_ffu_mvcnd_m; // To ctl of sparc_ffu_ctl.v
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input ifu_ffu_quad_op_e; // To ctl of sparc_ffu_ctl.v
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input ifu_ffu_stfsr_d; // To ctl of sparc_ffu_ctl.v
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input [1:0] ifu_ffu_tid_d; // To ctl of sparc_ffu_ctl.v
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input ifu_ffu_visop_d; // To ctl of sparc_ffu_ctl.v
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input ifu_lsu_ld_inst_e; // To ctl of sparc_ffu_ctl.v
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input ifu_tlu_flsh_inst_e; // To ctl of sparc_ffu_ctl.v
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input ifu_tlu_flush_w; // To ctl of sparc_ffu_ctl.v
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input ifu_tlu_inst_vld_w; // To ctl of sparc_ffu_ctl.v
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input [6:0] ifu_tlu_sraddr_d; // To ctl of sparc_ffu_ctl.v
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input lsu_ffu_ack; // To ctl of sparc_ffu_ctl.v
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input [2:0] lsu_ffu_bld_cnt_w; // To ctl of sparc_ffu_ctl.v
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input lsu_ffu_blk_asi_e; // To ctl of sparc_ffu_ctl.v
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input lsu_ffu_flush_pipe_w; // To ctl of sparc_ffu_ctl.v
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input [63:0] lsu_ffu_ld_data; // To dp of sparc_ffu_dp.v
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input lsu_ffu_ld_vld; // To ctl of sparc_ffu_ctl.v
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input lsu_ffu_stb_full0; // To ctl of sparc_ffu_ctl.v
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input lsu_ffu_stb_full1; // To ctl of sparc_ffu_ctl.v
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input lsu_ffu_stb_full2; // To ctl of sparc_ffu_ctl.v
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input lsu_ffu_stb_full3; // To ctl of sparc_ffu_ctl.v
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input lsu_ffu_st_dtlb_perr_g; // sotheas,8/17/04: fixed eco 6529, signal to sparc_ffu_ctl.v
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input rclk; // To frf of bw_r_frf.v, ...
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input se; // To frf of bw_r_frf.v, ...
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input sehold; // To frf of bw_r_frf.v
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input si; // To dp of sparc_ffu_dp.v
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [3:0] ffu_ifu_cc_vld_w2; // From ctl of sparc_ffu_ctl.v
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output [7:0] ffu_ifu_cc_w2; // From ctl of sparc_ffu_ctl.v
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output ffu_ifu_ecc_ce_w2; // From ctl of sparc_ffu_ctl.v
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output ffu_ifu_ecc_ue_w2; // From ctl of sparc_ffu_ctl.v
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output [5:0] ffu_ifu_err_reg_w2; // From ctl of sparc_ffu_ctl.v
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output [13:0] ffu_ifu_err_synd_w2; // From ctl of sparc_ffu_ctl.v
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output ffu_ifu_fpop_done_w2; // From ctl of sparc_ffu_ctl.v
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output ffu_ifu_fst_ce_w; // From ctl of sparc_ffu_ctl.v
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output ffu_ifu_inj_ack; // From ctl of sparc_ffu_ctl.v
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output ffu_ifu_stallreq; // From ctl of sparc_ffu_ctl.v
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output [1:0] ffu_ifu_tid_w2; // From ctl of sparc_ffu_ctl.v
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output ffu_lsu_blk_st_e; // From ctl of sparc_ffu_ctl.v
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output [5:3] ffu_lsu_blk_st_va_e; // From ctl of sparc_ffu_ctl.v
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output ffu_lsu_fpop_rq_vld; // From ctl of sparc_ffu_ctl.v
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output ffu_lsu_kill_fst_w; // From ctl of sparc_ffu_ctl.v
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output ffu_tlu_fpu_cmplt; // From ctl of sparc_ffu_ctl.v
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output [1:0] ffu_tlu_fpu_tid; // From ctl of sparc_ffu_ctl.v
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output ffu_tlu_ill_inst_m; // From ctl of sparc_ffu_ctl.v
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output ffu_tlu_trap_ieee754; // From ctl of sparc_ffu_ctl.v
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output ffu_tlu_trap_other; // From ctl of sparc_ffu_ctl.v
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output ffu_tlu_trap_ue; // From ctl of sparc_ffu_ctl.v
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output so; // From dp of sparc_ffu_dp.v
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire ctl_dp_ecc_sel_frf; // From ctl of sparc_ffu_ctl.v
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wire [9:0] ctl_dp_exc_w2; // From ctl of sparc_ffu_ctl.v
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wire [7:0] ctl_dp_fcc_w2; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_flip_fpu; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_flip_lsu; // From ctl of sparc_ffu_ctl.v
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wire [3:0] ctl_dp_fp_thr; // From ctl of sparc_ffu_ctl.v
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wire [3:0] ctl_dp_fsr_sel_fpu; // From ctl of sparc_ffu_ctl.v
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wire [3:0] ctl_dp_fsr_sel_ld; // From ctl of sparc_ffu_ctl.v
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wire [3:0] ctl_dp_fsr_sel_old; // From ctl of sparc_ffu_ctl.v
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wire [2:0] ctl_dp_ftt_w2; // From ctl of sparc_ffu_ctl.v
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wire [3:0] ctl_dp_gsr_wsr_w2; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_new_rs1; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_noflip_fpu; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_noflip_lsu; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_noshift64_frf; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_output_sel_frf; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_output_sel_fsr; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_output_sel_rs1; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_output_sel_rs2; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_rd_ecc; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_rs2_frf_read; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_rs2_keep_data; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_rs2_sel_fpu_lsu; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_rs2_sel_vis; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_rst_l; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_shift_frf_left; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_shift_frf_right; // From ctl of sparc_ffu_ctl.v
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| 187 |
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wire [1:0] ctl_dp_sign; // From ctl of sparc_ffu_ctl.v
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wire [3:0] ctl_dp_thr_e; // From ctl of sparc_ffu_ctl.v
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wire [36:0] ctl_dp_wsr_data_w2; // From ctl of sparc_ffu_ctl.v
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wire ctl_dp_zero_low32_frf; // From ctl of sparc_ffu_ctl.v
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wire [6:0] ctl_frf_addr; // From ctl of sparc_ffu_ctl.v
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wire ctl_frf_ren; // From ctl of sparc_ffu_ctl.v
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wire [1:0] ctl_frf_wen; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_add32; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_align0; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_align2; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_align4; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_align6; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_align_odd; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_cin; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_log_constant; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_log_invert_rs1; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_log_invert_rs2; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_log_pass_const; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_log_pass_rs1; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_log_pass_rs2; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_log_sel_nand; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_log_sel_nor; // From ctl of sparc_ffu_ctl.v
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wire ctl_vis_log_sel_pass; // From ctl of sparc_ffu_ctl.v
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| 210 |
|
|
wire ctl_vis_log_sel_xor; // From ctl of sparc_ffu_ctl.v
|
| 211 |
|
|
wire ctl_vis_sel_add; // From ctl of sparc_ffu_ctl.v
|
| 212 |
|
|
wire ctl_vis_sel_align; // From ctl of sparc_ffu_ctl.v
|
| 213 |
|
|
wire ctl_vis_sel_log; // From ctl of sparc_ffu_ctl.v
|
| 214 |
|
|
wire ctl_vis_subtract; // From ctl of sparc_ffu_ctl.v
|
| 215 |
|
|
wire [4:0] dp_ctl_fsr_aexc; // From dp of sparc_ffu_dp.v
|
| 216 |
|
|
wire [4:0] dp_ctl_fsr_cexc; // From dp of sparc_ffu_dp.v
|
| 217 |
|
|
wire [7:0] dp_ctl_fsr_fcc; // From dp of sparc_ffu_dp.v
|
| 218 |
|
|
wire [1:0] dp_ctl_fsr_rnd; // From dp of sparc_ffu_dp.v
|
| 219 |
|
|
wire [4:0] dp_ctl_fsr_tem; // From dp of sparc_ffu_dp.v
|
| 220 |
|
|
wire [31:0] dp_ctl_gsr_mask_e; // From dp of sparc_ffu_dp.v
|
| 221 |
|
|
wire [4:0] dp_ctl_gsr_scale_e; // From dp of sparc_ffu_dp.v
|
| 222 |
|
|
wire [7:0] dp_ctl_ld_fcc; // From dp of sparc_ffu_dp.v
|
| 223 |
|
|
wire [1:0] dp_ctl_rs2_sign; // From dp of sparc_ffu_dp.v
|
| 224 |
|
|
wire [6:0] dp_ctl_synd_out_high; // From dp of sparc_ffu_dp.v
|
| 225 |
|
|
wire [6:0] dp_ctl_synd_out_low; // From dp of sparc_ffu_dp.v
|
| 226 |
|
|
wire [63:0] dp_vis_rs1_data; // From dp of sparc_ffu_dp.v
|
| 227 |
|
|
wire [63:0] dp_vis_rs2_data; // From dp of sparc_ffu_dp.v
|
| 228 |
|
|
wire [77:0] frf_dp_data; // From frf of bw_r_frf.v
|
| 229 |
|
|
wire [63:0] vis_dp_rd_data; // From vis of sparc_ffu_vis.v
|
| 230 |
|
|
// End of automatics
|
| 231 |
|
|
wire [77:0] dp_frf_data;
|
| 232 |
|
|
|
| 233 |
|
|
output [63:0] ffu_exu_rsr_data_m;
|
| 234 |
|
|
wire [31:0] ffu_exu_rsr_data_hi_m;
|
| 235 |
|
|
wire [2:0] ffu_exu_rsr_data_mid_m;
|
| 236 |
|
|
wire [7:0] ffu_exu_rsr_data_lo_m;
|
| 237 |
|
|
|
| 238 |
|
|
wire short_scan_1;
|
| 239 |
|
|
|
| 240 |
|
|
assign ffu_exu_rsr_data_m[63:0] = {ffu_exu_rsr_data_hi_m[31:0], 4'b0,
|
| 241 |
|
|
ffu_exu_rsr_data_mid_m[2:0], 17'b0,
|
| 242 |
|
|
ffu_exu_rsr_data_lo_m[7:0]};
|
| 243 |
|
|
|
| 244 |
|
|
bw_r_frf frf(
|
| 245 |
|
|
.si(short_si0),
|
| 246 |
|
|
.so(short_scan_1),
|
| 247 |
|
|
.dp_frf_data (dp_frf_data[77:0]),
|
| 248 |
|
|
.rst_tri_en (mem_write_disable),
|
| 249 |
|
|
/*AUTOINST*/
|
| 250 |
|
|
// Outputs
|
| 251 |
|
|
.frf_dp_data (frf_dp_data[77:0]),
|
| 252 |
|
|
// Inputs
|
| 253 |
|
|
.rclk (rclk),
|
| 254 |
|
|
.se (se),
|
| 255 |
|
|
.sehold (sehold),
|
| 256 |
|
|
.ctl_frf_wen (ctl_frf_wen[1:0]),
|
| 257 |
|
|
.ctl_frf_ren (ctl_frf_ren),
|
| 258 |
|
|
.ctl_frf_addr (ctl_frf_addr[6:0]));
|
| 259 |
|
|
|
| 260 |
|
|
sparc_ffu_dp dp(
|
| 261 |
|
|
.dp_frf_data ({dp_frf_data[70:39],dp_frf_data[31:0]}),
|
| 262 |
|
|
/*AUTOINST*/
|
| 263 |
|
|
// Outputs
|
| 264 |
|
|
.so (so),
|
| 265 |
|
|
.ffu_lsu_data (ffu_lsu_data[63:0]),
|
| 266 |
|
|
.dp_vis_rs1_data (dp_vis_rs1_data[63:0]),
|
| 267 |
|
|
.dp_vis_rs2_data (dp_vis_rs2_data[63:0]),
|
| 268 |
|
|
.dp_ctl_rs2_sign (dp_ctl_rs2_sign[1:0]),
|
| 269 |
|
|
.dp_ctl_fsr_fcc (dp_ctl_fsr_fcc[7:0]),
|
| 270 |
|
|
.dp_ctl_fsr_rnd (dp_ctl_fsr_rnd[1:0]),
|
| 271 |
|
|
.dp_ctl_fsr_tem (dp_ctl_fsr_tem[4:0]),
|
| 272 |
|
|
.dp_ctl_fsr_aexc (dp_ctl_fsr_aexc[4:0]),
|
| 273 |
|
|
.dp_ctl_fsr_cexc (dp_ctl_fsr_cexc[4:0]),
|
| 274 |
|
|
.dp_ctl_ld_fcc (dp_ctl_ld_fcc[7:0]),
|
| 275 |
|
|
.dp_ctl_gsr_mask_e (dp_ctl_gsr_mask_e[31:0]),
|
| 276 |
|
|
.dp_ctl_gsr_scale_e (dp_ctl_gsr_scale_e[4:0]),
|
| 277 |
|
|
.dp_ctl_synd_out_low (dp_ctl_synd_out_low[6:0]),
|
| 278 |
|
|
.dp_ctl_synd_out_high(dp_ctl_synd_out_high[6:0]),
|
| 279 |
|
|
// Inputs
|
| 280 |
|
|
.rclk (rclk),
|
| 281 |
|
|
.se (se),
|
| 282 |
|
|
.si (si),
|
| 283 |
|
|
.ctl_dp_rst_l (ctl_dp_rst_l),
|
| 284 |
|
|
.frf_dp_data (frf_dp_data[77:0]),
|
| 285 |
|
|
.cpx_fpu_data (cpx_fpu_data[63:0]),
|
| 286 |
|
|
.lsu_ffu_ld_data (lsu_ffu_ld_data[63:0]),
|
| 287 |
|
|
.vis_dp_rd_data (vis_dp_rd_data[63:0]),
|
| 288 |
|
|
.ctl_dp_wsr_data_w2 (ctl_dp_wsr_data_w2[36:0]),
|
| 289 |
|
|
.ctl_dp_sign (ctl_dp_sign[1:0]),
|
| 290 |
|
|
.ctl_dp_exc_w2 (ctl_dp_exc_w2[9:0]),
|
| 291 |
|
|
.ctl_dp_fcc_w2 (ctl_dp_fcc_w2[7:0]),
|
| 292 |
|
|
.ctl_dp_ftt_w2 (ctl_dp_ftt_w2[2:0]),
|
| 293 |
|
|
.ctl_dp_noshift64_frf(ctl_dp_noshift64_frf),
|
| 294 |
|
|
.ctl_dp_shift_frf_right(ctl_dp_shift_frf_right),
|
| 295 |
|
|
.ctl_dp_shift_frf_left(ctl_dp_shift_frf_left),
|
| 296 |
|
|
.ctl_dp_zero_low32_frf(ctl_dp_zero_low32_frf),
|
| 297 |
|
|
.ctl_dp_output_sel_rs1(ctl_dp_output_sel_rs1),
|
| 298 |
|
|
.ctl_dp_output_sel_rs2(ctl_dp_output_sel_rs2),
|
| 299 |
|
|
.ctl_dp_output_sel_frf(ctl_dp_output_sel_frf),
|
| 300 |
|
|
.ctl_dp_output_sel_fsr(ctl_dp_output_sel_fsr),
|
| 301 |
|
|
.ctl_dp_noflip_lsu (ctl_dp_noflip_lsu),
|
| 302 |
|
|
.ctl_dp_flip_lsu (ctl_dp_flip_lsu),
|
| 303 |
|
|
.ctl_dp_noflip_fpu (ctl_dp_noflip_fpu),
|
| 304 |
|
|
.ctl_dp_flip_fpu (ctl_dp_flip_fpu),
|
| 305 |
|
|
.ctl_dp_rs2_frf_read (ctl_dp_rs2_frf_read),
|
| 306 |
|
|
.ctl_dp_rs2_sel_vis (ctl_dp_rs2_sel_vis),
|
| 307 |
|
|
.ctl_dp_rs2_sel_fpu_lsu(ctl_dp_rs2_sel_fpu_lsu),
|
| 308 |
|
|
.ctl_dp_rs2_keep_data(ctl_dp_rs2_keep_data),
|
| 309 |
|
|
.ctl_dp_rd_ecc (ctl_dp_rd_ecc),
|
| 310 |
|
|
.ctl_dp_fp_thr (ctl_dp_fp_thr[3:0]),
|
| 311 |
|
|
.ctl_dp_fsr_sel_old (ctl_dp_fsr_sel_old[3:0]),
|
| 312 |
|
|
.ctl_dp_fsr_sel_ld (ctl_dp_fsr_sel_ld[3:0]),
|
| 313 |
|
|
.ctl_dp_fsr_sel_fpu (ctl_dp_fsr_sel_fpu[3:0]),
|
| 314 |
|
|
.ctl_dp_gsr_wsr_w2 (ctl_dp_gsr_wsr_w2[3:0]),
|
| 315 |
|
|
.ctl_dp_thr_e (ctl_dp_thr_e[3:0]),
|
| 316 |
|
|
.ctl_dp_new_rs1 (ctl_dp_new_rs1),
|
| 317 |
|
|
.ctl_dp_ecc_sel_frf (ctl_dp_ecc_sel_frf));
|
| 318 |
|
|
|
| 319 |
|
|
sparc_ffu_ctl ctl(
|
| 320 |
|
|
.si(short_scan_1),
|
| 321 |
|
|
.so (short_so0),
|
| 322 |
|
|
.ffu_exu_rsr_data_hi_m(ffu_exu_rsr_data_hi_m[31:0]),
|
| 323 |
|
|
.ffu_exu_rsr_data_lo_m(ffu_exu_rsr_data_lo_m[7:0]),
|
| 324 |
|
|
.ffu_exu_rsr_data_mid_m(ffu_exu_rsr_data_mid_m[2:0]),
|
| 325 |
|
|
.ctl_frf_write_synd({dp_frf_data[77:71],dp_frf_data[38:32]}),
|
| 326 |
|
|
.rst_tri_en (mux_drive_disable),
|
| 327 |
|
|
/*AUTOINST*/
|
| 328 |
|
|
// Outputs
|
| 329 |
|
|
.ctl_dp_gsr_wsr_w2 (ctl_dp_gsr_wsr_w2[3:0]),
|
| 330 |
|
|
.ctl_dp_thr_e (ctl_dp_thr_e[3:0]),
|
| 331 |
|
|
.ctl_dp_wsr_data_w2(ctl_dp_wsr_data_w2[36:0]),
|
| 332 |
|
|
.ctl_vis_add32 (ctl_vis_add32),
|
| 333 |
|
|
.ctl_vis_align0 (ctl_vis_align0),
|
| 334 |
|
|
.ctl_vis_align2 (ctl_vis_align2),
|
| 335 |
|
|
.ctl_vis_align4 (ctl_vis_align4),
|
| 336 |
|
|
.ctl_vis_align6 (ctl_vis_align6),
|
| 337 |
|
|
.ctl_vis_align_odd (ctl_vis_align_odd),
|
| 338 |
|
|
.ctl_vis_cin (ctl_vis_cin),
|
| 339 |
|
|
.ctl_vis_log_constant(ctl_vis_log_constant),
|
| 340 |
|
|
.ctl_vis_log_invert_rs1(ctl_vis_log_invert_rs1),
|
| 341 |
|
|
.ctl_vis_log_invert_rs2(ctl_vis_log_invert_rs2),
|
| 342 |
|
|
.ctl_vis_log_pass_const(ctl_vis_log_pass_const),
|
| 343 |
|
|
.ctl_vis_log_pass_rs1(ctl_vis_log_pass_rs1),
|
| 344 |
|
|
.ctl_vis_log_pass_rs2(ctl_vis_log_pass_rs2),
|
| 345 |
|
|
.ctl_vis_log_sel_nand(ctl_vis_log_sel_nand),
|
| 346 |
|
|
.ctl_vis_log_sel_nor(ctl_vis_log_sel_nor),
|
| 347 |
|
|
.ctl_vis_log_sel_pass(ctl_vis_log_sel_pass),
|
| 348 |
|
|
.ctl_vis_log_sel_xor(ctl_vis_log_sel_xor),
|
| 349 |
|
|
.ctl_vis_sel_add (ctl_vis_sel_add),
|
| 350 |
|
|
.ctl_vis_sel_align (ctl_vis_sel_align),
|
| 351 |
|
|
.ctl_vis_sel_log (ctl_vis_sel_log),
|
| 352 |
|
|
.ctl_vis_subtract (ctl_vis_subtract),
|
| 353 |
|
|
.ctl_dp_rst_l (ctl_dp_rst_l),
|
| 354 |
|
|
.ffu_ifu_fpop_done_w2(ffu_ifu_fpop_done_w2),
|
| 355 |
|
|
.ffu_ifu_cc_vld_w2 (ffu_ifu_cc_vld_w2[3:0]),
|
| 356 |
|
|
.ffu_ifu_cc_w2 (ffu_ifu_cc_w2[7:0]),
|
| 357 |
|
|
.ffu_ifu_tid_w2 (ffu_ifu_tid_w2[1:0]),
|
| 358 |
|
|
.ffu_ifu_stallreq (ffu_ifu_stallreq),
|
| 359 |
|
|
.ffu_ifu_ecc_ce_w2 (ffu_ifu_ecc_ce_w2),
|
| 360 |
|
|
.ffu_ifu_ecc_ue_w2 (ffu_ifu_ecc_ue_w2),
|
| 361 |
|
|
.ffu_ifu_err_reg_w2(ffu_ifu_err_reg_w2[5:0]),
|
| 362 |
|
|
.ffu_ifu_err_synd_w2(ffu_ifu_err_synd_w2[13:0]),
|
| 363 |
|
|
.ffu_ifu_fst_ce_w (ffu_ifu_fst_ce_w),
|
| 364 |
|
|
.ffu_lsu_kill_fst_w(ffu_lsu_kill_fst_w),
|
| 365 |
|
|
.ffu_ifu_inj_ack (ffu_ifu_inj_ack),
|
| 366 |
|
|
.ffu_lsu_data (ffu_lsu_data[80:64]),
|
| 367 |
|
|
.ffu_lsu_fpop_rq_vld(ffu_lsu_fpop_rq_vld),
|
| 368 |
|
|
.ffu_lsu_blk_st_va_e(ffu_lsu_blk_st_va_e[5:3]),
|
| 369 |
|
|
.ffu_lsu_blk_st_e (ffu_lsu_blk_st_e),
|
| 370 |
|
|
.ffu_tlu_trap_ieee754(ffu_tlu_trap_ieee754),
|
| 371 |
|
|
.ffu_tlu_trap_other(ffu_tlu_trap_other),
|
| 372 |
|
|
.ffu_tlu_trap_ue (ffu_tlu_trap_ue),
|
| 373 |
|
|
.ffu_tlu_ill_inst_m(ffu_tlu_ill_inst_m),
|
| 374 |
|
|
.ffu_tlu_fpu_tid (ffu_tlu_fpu_tid[1:0]),
|
| 375 |
|
|
.ffu_tlu_fpu_cmplt (ffu_tlu_fpu_cmplt),
|
| 376 |
|
|
.ctl_frf_ren (ctl_frf_ren),
|
| 377 |
|
|
.ctl_frf_wen (ctl_frf_wen[1:0]),
|
| 378 |
|
|
.ctl_frf_addr (ctl_frf_addr[6:0]),
|
| 379 |
|
|
.ctl_dp_fp_thr (ctl_dp_fp_thr[3:0]),
|
| 380 |
|
|
.ctl_dp_fcc_w2 (ctl_dp_fcc_w2[7:0]),
|
| 381 |
|
|
.ctl_dp_ftt_w2 (ctl_dp_ftt_w2[2:0]),
|
| 382 |
|
|
.ctl_dp_exc_w2 (ctl_dp_exc_w2[9:0]),
|
| 383 |
|
|
.ctl_dp_ecc_sel_frf(ctl_dp_ecc_sel_frf),
|
| 384 |
|
|
.ctl_dp_output_sel_rs1(ctl_dp_output_sel_rs1),
|
| 385 |
|
|
.ctl_dp_output_sel_rs2(ctl_dp_output_sel_rs2),
|
| 386 |
|
|
.ctl_dp_output_sel_frf(ctl_dp_output_sel_frf),
|
| 387 |
|
|
.ctl_dp_output_sel_fsr(ctl_dp_output_sel_fsr),
|
| 388 |
|
|
.ctl_dp_rs2_frf_read(ctl_dp_rs2_frf_read),
|
| 389 |
|
|
.ctl_dp_rs2_sel_vis(ctl_dp_rs2_sel_vis),
|
| 390 |
|
|
.ctl_dp_rs2_sel_fpu_lsu(ctl_dp_rs2_sel_fpu_lsu),
|
| 391 |
|
|
.ctl_dp_rs2_keep_data(ctl_dp_rs2_keep_data),
|
| 392 |
|
|
.ctl_dp_rd_ecc (ctl_dp_rd_ecc),
|
| 393 |
|
|
.ctl_dp_fsr_sel_ld (ctl_dp_fsr_sel_ld[3:0]),
|
| 394 |
|
|
.ctl_dp_fsr_sel_fpu(ctl_dp_fsr_sel_fpu[3:0]),
|
| 395 |
|
|
.ctl_dp_fsr_sel_old(ctl_dp_fsr_sel_old[3:0]),
|
| 396 |
|
|
.ctl_dp_noshift64_frf(ctl_dp_noshift64_frf),
|
| 397 |
|
|
.ctl_dp_shift_frf_right(ctl_dp_shift_frf_right),
|
| 398 |
|
|
.ctl_dp_shift_frf_left(ctl_dp_shift_frf_left),
|
| 399 |
|
|
.ctl_dp_zero_low32_frf(ctl_dp_zero_low32_frf),
|
| 400 |
|
|
.ctl_dp_new_rs1 (ctl_dp_new_rs1),
|
| 401 |
|
|
.ctl_dp_sign (ctl_dp_sign[1:0]),
|
| 402 |
|
|
.ctl_dp_flip_fpu (ctl_dp_flip_fpu),
|
| 403 |
|
|
.ctl_dp_flip_lsu (ctl_dp_flip_lsu),
|
| 404 |
|
|
.ctl_dp_noflip_fpu (ctl_dp_noflip_fpu),
|
| 405 |
|
|
.ctl_dp_noflip_lsu (ctl_dp_noflip_lsu),
|
| 406 |
|
|
// Inputs
|
| 407 |
|
|
.dp_ctl_gsr_mask_e (dp_ctl_gsr_mask_e[31:0]),
|
| 408 |
|
|
.dp_ctl_gsr_scale_e(dp_ctl_gsr_scale_e[4:0]),
|
| 409 |
|
|
.exu_ffu_gsr_align_m(exu_ffu_gsr_align_m[2:0]),
|
| 410 |
|
|
.exu_ffu_gsr_mask_m(exu_ffu_gsr_mask_m[31:0]),
|
| 411 |
|
|
.exu_ffu_gsr_rnd_m (exu_ffu_gsr_rnd_m[2:0]),
|
| 412 |
|
|
.exu_ffu_gsr_scale_m(exu_ffu_gsr_scale_m[4:0]),
|
| 413 |
|
|
.exu_ffu_wsr_inst_e(exu_ffu_wsr_inst_e),
|
| 414 |
|
|
.ifu_tlu_sraddr_d (ifu_tlu_sraddr_d[6:0]),
|
| 415 |
|
|
.lsu_ffu_st_dtlb_perr_g (lsu_ffu_st_dtlb_perr_g), //sotheas,8/17/04: fixed eco 6529
|
| 416 |
|
|
.rclk (rclk),
|
| 417 |
|
|
.se (se),
|
| 418 |
|
|
.grst_l (grst_l),
|
| 419 |
|
|
.arst_l (arst_l),
|
| 420 |
|
|
.dp_ctl_rs2_sign (dp_ctl_rs2_sign[1:0]),
|
| 421 |
|
|
.cpx_vld (cpx_vld),
|
| 422 |
|
|
.cpx_fcmp (cpx_fcmp),
|
| 423 |
|
|
.cpx_req (cpx_req[3:0]),
|
| 424 |
|
|
.cpx_fccval (cpx_fccval[1:0]),
|
| 425 |
|
|
.cpx_fpexc (cpx_fpexc[4:0]),
|
| 426 |
|
|
.dp_ctl_fsr_fcc (dp_ctl_fsr_fcc[7:0]),
|
| 427 |
|
|
.dp_ctl_fsr_rnd (dp_ctl_fsr_rnd[1:0]),
|
| 428 |
|
|
.dp_ctl_fsr_tem (dp_ctl_fsr_tem[4:0]),
|
| 429 |
|
|
.dp_ctl_fsr_aexc (dp_ctl_fsr_aexc[4:0]),
|
| 430 |
|
|
.dp_ctl_fsr_cexc (dp_ctl_fsr_cexc[4:0]),
|
| 431 |
|
|
.dp_ctl_synd_out_low(dp_ctl_synd_out_low[6:0]),
|
| 432 |
|
|
.dp_ctl_synd_out_high(dp_ctl_synd_out_high[6:0]),
|
| 433 |
|
|
.ifu_ffu_fpop1_d (ifu_ffu_fpop1_d),
|
| 434 |
|
|
.ifu_ffu_fpop2_d (ifu_ffu_fpop2_d),
|
| 435 |
|
|
.ifu_ffu_visop_d (ifu_ffu_visop_d),
|
| 436 |
|
|
.ifu_ffu_fpopcode_d(ifu_ffu_fpopcode_d[8:0]),
|
| 437 |
|
|
.ifu_ffu_frs1_d (ifu_ffu_frs1_d[4:0]),
|
| 438 |
|
|
.ifu_ffu_frs2_d (ifu_ffu_frs2_d[4:0]),
|
| 439 |
|
|
.ifu_ffu_frd_d (ifu_ffu_frd_d[4:0]),
|
| 440 |
|
|
.ifu_ffu_fld_d (ifu_ffu_fld_d),
|
| 441 |
|
|
.ifu_ffu_fst_d (ifu_ffu_fst_d),
|
| 442 |
|
|
.ifu_ffu_ldst_single_d(ifu_ffu_ldst_single_d),
|
| 443 |
|
|
.ifu_ffu_tid_d (ifu_ffu_tid_d[1:0]),
|
| 444 |
|
|
.ifu_ffu_fcc_num_d (ifu_ffu_fcc_num_d[1:0]),
|
| 445 |
|
|
.ifu_ffu_mvcnd_m (ifu_ffu_mvcnd_m),
|
| 446 |
|
|
.ifu_ffu_inj_frferr(ifu_ffu_inj_frferr),
|
| 447 |
|
|
.ifu_exu_ecc_mask (ifu_exu_ecc_mask[6:0]),
|
| 448 |
|
|
.ifu_ffu_ldfsr_d (ifu_ffu_ldfsr_d),
|
| 449 |
|
|
.ifu_ffu_ldxfsr_d (ifu_ffu_ldxfsr_d),
|
| 450 |
|
|
.ifu_ffu_stfsr_d (ifu_ffu_stfsr_d),
|
| 451 |
|
|
.ifu_ffu_quad_op_e (ifu_ffu_quad_op_e),
|
| 452 |
|
|
.ifu_tlu_inst_vld_w(ifu_tlu_inst_vld_w),
|
| 453 |
|
|
.lsu_ffu_flush_pipe_w(lsu_ffu_flush_pipe_w),
|
| 454 |
|
|
.ifu_tlu_flush_w (ifu_tlu_flush_w),
|
| 455 |
|
|
.lsu_ffu_ack (lsu_ffu_ack),
|
| 456 |
|
|
.lsu_ffu_ld_vld (lsu_ffu_ld_vld),
|
| 457 |
|
|
.lsu_ffu_bld_cnt_w (lsu_ffu_bld_cnt_w[2:0]),
|
| 458 |
|
|
.dp_ctl_ld_fcc (dp_ctl_ld_fcc[7:0]),
|
| 459 |
|
|
.ifu_exu_nceen_e (ifu_exu_nceen_e),
|
| 460 |
|
|
.ifu_exu_disable_ce_e(ifu_exu_disable_ce_e),
|
| 461 |
|
|
.lsu_ffu_blk_asi_e (lsu_ffu_blk_asi_e),
|
| 462 |
|
|
.exu_ffu_ist_e (exu_ffu_ist_e),
|
| 463 |
|
|
.ifu_tlu_flsh_inst_e(ifu_tlu_flsh_inst_e),
|
| 464 |
|
|
.ifu_lsu_ld_inst_e (ifu_lsu_ld_inst_e),
|
| 465 |
|
|
.lsu_ffu_stb_full0 (lsu_ffu_stb_full0),
|
| 466 |
|
|
.lsu_ffu_stb_full1 (lsu_ffu_stb_full1),
|
| 467 |
|
|
.lsu_ffu_stb_full2 (lsu_ffu_stb_full2),
|
| 468 |
|
|
.lsu_ffu_stb_full3 (lsu_ffu_stb_full3));
|
| 469 |
|
|
|
| 470 |
|
|
sparc_ffu_vis vis(/*AUTOINST*/
|
| 471 |
|
|
// Outputs
|
| 472 |
|
|
.vis_dp_rd_data (vis_dp_rd_data[63:0]),
|
| 473 |
|
|
// Inputs
|
| 474 |
|
|
.dp_vis_rs1_data (dp_vis_rs1_data[63:0]),
|
| 475 |
|
|
.dp_vis_rs2_data (dp_vis_rs2_data[63:0]),
|
| 476 |
|
|
.ctl_vis_sel_add (ctl_vis_sel_add),
|
| 477 |
|
|
.ctl_vis_sel_log (ctl_vis_sel_log),
|
| 478 |
|
|
.ctl_vis_sel_align (ctl_vis_sel_align),
|
| 479 |
|
|
.ctl_vis_add32 (ctl_vis_add32),
|
| 480 |
|
|
.ctl_vis_subtract (ctl_vis_subtract),
|
| 481 |
|
|
.ctl_vis_cin (ctl_vis_cin),
|
| 482 |
|
|
.ctl_vis_align0 (ctl_vis_align0),
|
| 483 |
|
|
.ctl_vis_align2 (ctl_vis_align2),
|
| 484 |
|
|
.ctl_vis_align4 (ctl_vis_align4),
|
| 485 |
|
|
.ctl_vis_align6 (ctl_vis_align6),
|
| 486 |
|
|
.ctl_vis_align_odd (ctl_vis_align_odd),
|
| 487 |
|
|
.ctl_vis_log_sel_pass(ctl_vis_log_sel_pass),
|
| 488 |
|
|
.ctl_vis_log_sel_nand(ctl_vis_log_sel_nand),
|
| 489 |
|
|
.ctl_vis_log_sel_nor(ctl_vis_log_sel_nor),
|
| 490 |
|
|
.ctl_vis_log_sel_xor(ctl_vis_log_sel_xor),
|
| 491 |
|
|
.ctl_vis_log_invert_rs1(ctl_vis_log_invert_rs1),
|
| 492 |
|
|
.ctl_vis_log_invert_rs2(ctl_vis_log_invert_rs2),
|
| 493 |
|
|
.ctl_vis_log_constant(ctl_vis_log_constant),
|
| 494 |
|
|
.ctl_vis_log_pass_const(ctl_vis_log_pass_const),
|
| 495 |
|
|
.ctl_vis_log_pass_rs1(ctl_vis_log_pass_rs1),
|
| 496 |
|
|
.ctl_vis_log_pass_rs2(ctl_vis_log_pass_rs2));
|
| 497 |
|
|
endmodule // sparc_ffu
|
| 498 |
|
|
// Local Variables:
|
| 499 |
|
|
// verilog-library-directories:("." "../../../srams/rtl")
|
| 500 |
|
|
// End:
|
| 501 |
|
|
|
