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// ========== Copyright Header Begin ==========================================

// 

// OpenSPARC T1 Processor File: sparc_ifu_errdp.v

// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

// 

// The above named program is free software; you can redistribute it and/or

// modify it under the terms of the GNU General Public

// License version 2 as published by the Free Software Foundation.

// 

// The above named program is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

// General Public License for more details.

// 

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// ========== Copyright Header End ============================================

////////////////////////////////////////////////////////////////////////

/*

//  Module Name:  sparc_ifu_errdp

*/

////////////////////////////////////////////////////////////////////////

// Global header file includes

////////////////////////////////////////////////////////////////////////

/*

/* ========== Copyright Header Begin ==========================================

*

* OpenSPARC T1 Processor File: lsu.h

* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

*

* The above named program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public

* License version 2 as published by the Free Software Foundation.

*

* The above named program is distributed in the hope that it will be

* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

* General Public License for more details.

*

* You should have received a copy of the GNU General Public

* License along with this work; if not, write to the Free Software

* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

*

* ========== Copyright Header End ============================================

*/

//`define STB_PCX_WY_HI   107

//`define STB_PCX_WY_LO   106

// TLB Tag and Data Format

// I-TLB version - lsu_tlb only.

// Invalidate Format

//addr<5:4>=00

//addr<5:4>=01

//addr<5:4>=10

//addr<5:4>=11

// cpuid - 4b

// CPUany, addr<5:4>=00,10

// CPUany, addr<5:4>=01,11

// CPUany, addr<5:4>=01,11

// DTAG parity error Invalidate

// CPX BINIT STORE

/*

/* ========== Copyright Header Begin ==========================================

*

* OpenSPARC T1 Processor File: ifu.h

* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

*

* The above named program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public

* License version 2 as published by the Free Software Foundation.

*

* The above named program is distributed in the hope that it will be

* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

* General Public License for more details.

*

* You should have received a copy of the GNU General Public

* License along with this work; if not, write to the Free Software

* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

*

* ========== Copyright Header End ============================================

*/

////////////////////////////////////////////////////////////////////////

/*

//

//  Module Name: ifu.h

//  Description:

//  All ifu defines

*/

//--------------------------------------------

// Icache Values in IFU::ICD/ICV/ICT/FDP/IFQDP

//--------------------------------------------

// Set Values

// IC_IDX_HI = log(icache_size/4ways) - 1

// !!IMPORTANT!! a change to IC_LINE_SZ will mean a change to the code as

//   well.  Unfortunately this has not been properly parametrized.

//   Changing the IC_LINE_SZ param alone is *not* enough.

// !!IMPORTANT!! a change to IC_TAG_HI will mean a change to the code as

//   well.  Changing the IC_TAG_HI param alone is *not* enough to

//   change the PA range. 

// highest bit of PA

// Derived Values

// 4095

// number of entries - 1 = 511

// 12

// 28

// 7

// tags for all 4 ways + parity

// 116

// 115

//----------------------------------------------------------------------

// For thread scheduler in IFU::DTU::SWL

//----------------------------------------------------------------------

// thread states:  (thr_state[4:0])

// thread configuration register bit fields

//----------------------------------------------------------------------

// For MIL fsm in IFU::IFQ

//----------------------------------------------------------------------

//---------------------------------------------------

// Interrupt Block

//---------------------------------------------------

//-------------------------------------

// IFQ

//-------------------------------------

// valid bit plus ifill

//`ifdef SPARC_L2_64B

//`else

//`define BANK_ID_HI 8

//`define BANK_ID_LO 7

//`endif

//`define CPX_INV_PA_HI  116

//`define CPX_INV_PA_LO  112

//----------------------------------------

// IFU Traps

//----------------------------------------

// precise

// disrupting

module sparc_ifu_errdp(/*AUTOARG*/

   // Outputs

   so, ifu_lsu_ldxa_data_w2, erb_dtu_imask, erd_erc_tlbt_pe_s1,

   erd_erc_tlbd_pe_s1, erd_erc_tagpe_s1, erd_erc_nirpe_s1,

   erd_erc_fetpe_s1, erd_erc_tte_pgsz,

   // Inputs

   rclk, se, si, erb_reset, itlb_rd_tte_data, itlb_rd_tte_tag,

   itlb_ifq_paddr_s, wsel_fdp_fetdata_s1, wsel_fdp_topdata_s1,

   wsel_erb_asidata_s, ict_itlb_tags_f, icv_itlb_valid_f,

   lsu_ifu_err_addr, spu_ifu_err_addr_w2, fdp_erb_pc_f,

   exu_ifu_err_reg_m, exu_ifu_err_synd_m, ffu_ifu_err_reg_w2,

   ffu_ifu_err_synd_w2, tlu_itlb_rw_index_g, erc_erd_pgsz_b0,

   erc_erd_pgsz_b1, erc_erd_erren_asidata, erc_erd_errstat_asidata,

   erc_erd_errinj_asidata, ifq_erb_asidata_i2, ifq_erb_wrtag_f,

   ifq_erb_wrindex_f, erc_erd_asiway_s1_l, fcl_erb_itlbrd_data_s,

   erc_erd_ld_imask, erc_erd_asisrc_sel_icd_s_l,

   erc_erd_asisrc_sel_misc_s_l, erc_erd_asisrc_sel_err_s_l,

   erc_erd_asisrc_sel_itlb_s_l, erc_erd_errasi_sel_en_l,

   erc_erd_errasi_sel_stat_l, erc_erd_errasi_sel_inj_l,

   erc_erd_errasi_sel_addr_l, erc_erd_miscasi_sel_ict_l,

   erc_erd_miscasi_sel_imask_l, erc_erd_miscasi_sel_other_l,

   erc_erd_asi_thr_l, erc_erd_eadr0_sel_irf_l,

   erc_erd_eadr0_sel_itlb_l, erc_erd_eadr0_sel_frf_l,

   erc_erd_eadr0_sel_lsu_l, erc_erd_eadr1_sel_pcd1_l,

   erc_erd_eadr1_sel_l1pa_l, erc_erd_eadr1_sel_l2pa_l,

   erc_erd_eadr1_sel_other_l, erc_erd_eadr2_sel_mx1_l,

   erc_erd_eadr2_sel_wrt_l, erc_erd_eadr2_sel_mx0_l,

   erc_erd_eadr2_sel_old_l

   );

   input       rclk,

               se,

               si,

               erb_reset;

   input [42:0] itlb_rd_tte_data;   // this is in s1

   input [58:0] itlb_rd_tte_tag;    // this is in s1

   input [39:10] itlb_ifq_paddr_s;

   input [33:0] wsel_fdp_fetdata_s1,

                            wsel_fdp_topdata_s1;

   input [33:0] wsel_erb_asidata_s;

   input [(((39 - 11) * 4) + 3):0] ict_itlb_tags_f;

   input [3:0]              icv_itlb_valid_f;

   input [47:4]  lsu_ifu_err_addr;

   input [39:4]  spu_ifu_err_addr_w2;

   input [47:0]  fdp_erb_pc_f;

   input [7:0]   exu_ifu_err_reg_m;

   input [7:0]   exu_ifu_err_synd_m;

   input [5:0]   ffu_ifu_err_reg_w2;

   input [13:0]  ffu_ifu_err_synd_w2;

   input [5:0]   tlu_itlb_rw_index_g;

   input         erc_erd_pgsz_b0,

                 erc_erd_pgsz_b1;

   input [1:0]   erc_erd_erren_asidata;

   input [22:0]  erc_erd_errstat_asidata;

   input [31:0]  erc_erd_errinj_asidata;

   input [47:0]  ifq_erb_asidata_i2;

   input [(39 - 11)-1:0] ifq_erb_wrtag_f;

   input [11:4]   ifq_erb_wrindex_f;

   // mux selects

   input [3:0]  erc_erd_asiway_s1_l;

   input        fcl_erb_itlbrd_data_s;

   input        erc_erd_ld_imask;

   input        erc_erd_asisrc_sel_icd_s_l,

                            erc_erd_asisrc_sel_misc_s_l,

                            erc_erd_asisrc_sel_err_s_l,

                            erc_erd_asisrc_sel_itlb_s_l;

   input        erc_erd_errasi_sel_en_l,

                            erc_erd_errasi_sel_stat_l,

                            erc_erd_errasi_sel_inj_l,

                            erc_erd_errasi_sel_addr_l;

   input        erc_erd_miscasi_sel_ict_l,

                            erc_erd_miscasi_sel_imask_l,

                            erc_erd_miscasi_sel_other_l;

   input [3:0]  erc_erd_asi_thr_l;

   input [3:0]  erc_erd_eadr0_sel_irf_l,

                            erc_erd_eadr0_sel_itlb_l,

                            erc_erd_eadr0_sel_frf_l,

                            erc_erd_eadr0_sel_lsu_l;

   input [3:0]  erc_erd_eadr1_sel_pcd1_l,

                            erc_erd_eadr1_sel_l1pa_l,

                            erc_erd_eadr1_sel_l2pa_l,

                            erc_erd_eadr1_sel_other_l;

   input [3:0]  erc_erd_eadr2_sel_mx1_l,

                            erc_erd_eadr2_sel_wrt_l,

                            erc_erd_eadr2_sel_mx0_l,

                            erc_erd_eadr2_sel_old_l;

   output       so;

   output [63:0] ifu_lsu_ldxa_data_w2;

   output [38:0] erb_dtu_imask;

//   output [9:0]  erb_ifq_paddr_s;

   output [1:0]  erd_erc_tlbt_pe_s1,

                             erd_erc_tlbd_pe_s1;

   output [3:0]  erd_erc_tagpe_s1;

   output        erd_erc_nirpe_s1,

                             erd_erc_fetpe_s1;

   output [2:0]  erd_erc_tte_pgsz;

//   

// local signals   

//

   wire [47:4]   lsu_err_addr;

   wire [(((39 - 11) * 4) + 3):0]  ictags_s1;

   wire [3:0]               icv_data_s1;

   wire [31:0]              tag_asi_data;

   wire [47:4]              t0_eadr_mx0_out,

                                        t1_eadr_mx0_out,

                                        t2_eadr_mx0_out,

                                        t3_eadr_mx0_out,

                                        t0_eadr_mx1_out,

                                        t1_eadr_mx1_out,

                                        t2_eadr_mx1_out,

                                        t3_eadr_mx1_out;

   wire [47:4]              t0_err_addr_nxt,

                                        t0_err_addr,

                                        t1_err_addr_nxt,

                                        t1_err_addr,

                                        t2_err_addr_nxt,

                                        t2_err_addr,

                                        t3_err_addr_nxt,

                                        t3_err_addr;

   wire [47:4]              err_addr_asidata;

   wire [63:0]              formatted_tte_data,

                                        formatted_tte_tag,

                                        tlb_asi_data,

                                        misc_asi_data,

                                        err_asi_data,

                            ldxa_data_s,

                            ldxa_data_d;

   wire [39:4]              paddr_s1,

                                        paddr_d1;

   wire [39:4]              ifet_addr_f;

   wire [47:0]              pc_s1;

   wire [47:4]              pc_d1;

   wire [7:0]               irfaddr_w,

                            irfsynd_w;

   wire                     irfaddr_4_w;

   wire [5:0]               itlb_asi_index;

   wire [38:0]              imask_next;

   wire                     clk;

//

// Code Begins Here

//

   assign                   clk = rclk;

//-------------

// Tags

//-------------   

   dff #((((39 - 11) * 4) + 4)) tags_reg(.din (ict_itlb_tags_f),

                                           .q   (ictags_s1),

                                           .clk (clk),

                                           .se  (se), .si(), .so());

   dff #(4) vbits_reg(.din (icv_itlb_valid_f[3:0]),

                                  .q   (icv_data_s1),

                                  .clk (clk), .se(se), .si(), .so());

   // check parity

   sparc_ifu_par32  tag_par0(.in  ({3'b0, ictags_s1[(39 - 11):0]}),

                                               .out (erd_erc_tagpe_s1[0]));

   sparc_ifu_par32  tag_par1(.in  ({3'b0, ictags_s1[((2*(39 - 11)) + 1):((39 - 11)+1)]}),

                                               .out (erd_erc_tagpe_s1[1]));

   sparc_ifu_par32  tag_par2(.in  ({3'b0, ictags_s1[((3*(39 - 11)) + 2):(2*((39 - 11))+2)]}),

                                               .out (erd_erc_tagpe_s1[2]));

   sparc_ifu_par32  tag_par3(.in  ({3'b0, ictags_s1[((4*(39 - 11)) + 3):(3*((39 - 11))+3)]}),

                                               .out (erd_erc_tagpe_s1[3]));

   dp_mux4ds #(32) asitag_mux(.dout (tag_asi_data[31:0]),

                         .in0  ({icv_data_s1[0], 1'b0, ictags_s1[28], 1'b0, ictags_s1[27:0]}),

                         .in1  ({icv_data_s1[1], 1'b0, ictags_s1[57], 1'b0, ictags_s1[56:29]}),

                         .in2  ({icv_data_s1[2], 1'b0, ictags_s1[86], 1'b0, ictags_s1[85:58]}),

                         .in3  ({icv_data_s1[3], 1'b0, ictags_s1[115], 1'b0, ictags_s1[114:87]}),

                         .sel0_l (erc_erd_asiway_s1_l[0]),

                         .sel1_l (erc_erd_asiway_s1_l[1]),

                         .sel2_l (erc_erd_asiway_s1_l[2]),

                         .sel3_l (erc_erd_asiway_s1_l[3]));

//------------------

// Data

//------------------

   // parity check on instruction

   // This may have to be done in the next stage (at least partially)

   sparc_ifu_par34 nir_par(.in  (wsel_fdp_topdata_s1[33:0]),

                                             .out (erd_erc_nirpe_s1));

   sparc_ifu_par34 inst_par(.in  (wsel_fdp_fetdata_s1[33:0]),

                                              .out (erd_erc_fetpe_s1));

//----------------------------------------------------------------------

// TLB read data

//----------------------------------------------------------------------

//`ifdef SPARC_HPV_EN

   // don't include v(26) and u(24) bits in parity   

   sparc_ifu_par32 tt_tag_par0(.in  ({itlb_rd_tte_tag[33:27],

                                                              itlb_rd_tte_tag[25],

                                                              itlb_rd_tte_tag[23:0]}),

                                                 .out (erd_erc_tlbt_pe_s1[0]));

//`else

//   // don't include v(28) and u(26) bits in parity

//   sparc_ifu_par32 tt_tag_par0(.in  ({itlb_rd_tte_tag[33:29],

//                                                            itlb_rd_tte_tag[27],

//                                                            itlb_rd_tte_tag[25:0]}),

//                                               .out (erd_erc_tlbt_pe_s1[0]));

//`endif // !`ifdef SPARC_HPV_EN

   sparc_ifu_par32 tt_tag_par1(.in  ({7'b0, itlb_rd_tte_tag[58:34]}),

                                                 .out (erd_erc_tlbt_pe_s1[1]));

   sparc_ifu_par32 tt_data_par0(.in  (itlb_rd_tte_data[31:0]),

                                                        .out (erd_erc_tlbd_pe_s1[0]));

   sparc_ifu_par16 tt_data_par1(.in  ({5'b0, itlb_rd_tte_data[42:32]}),

                                                        .out (erd_erc_tlbd_pe_s1[1]));

//   assign erd_erc_tte_lock_s1 = itlb_rd_tte_data[`STLB_DATA_L];

//`ifdef        SPARC_HPV_EN

   assign erd_erc_tte_pgsz[2:0] = {itlb_rd_tte_data[23],

                                                           itlb_rd_tte_data[16],

                                                           itlb_rd_tte_data[12]};

   assign formatted_tte_tag[63:0] =

          {

//           `ifdef SUN4V_TAG_RD

           // implement this!

           itlb_rd_tte_tag[58:55],

//           `else

//         {4{itlb_rd_tte_tag[53]}},                                     // 4b

//           `endif

           itlb_rd_tte_tag[54],     // Parity                 1b

           itlb_rd_tte_tag[27], // mxsel2 - b27:22 vld    1b