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// ========== Copyright Header Begin ==========================================

// 

// OpenSPARC T1 Processor File: sparc_ifu_fcl.v

// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

// 

// The above named program is free software; you can redistribute it and/or

// modify it under the terms of the GNU General Public

// License version 2 as published by the Free Software Foundation.

// 

// The above named program is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

// General Public License for more details.

// 

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// ========== Copyright Header End ============================================

//////////////////////////////////////////////////////////////////////

/*

//  Module Name: sparc_ifu_fcl

//  Description:

//  The FCL is the fetch control logic.  It controls the PC datapath

//  and the fetch/next instruction datapath.  It also manages access

//  to the icache data, tags, vbits and to the tlb.

//  The FCL starts fetching from the reset PC upon reset.  It is up to

//  the DTU to specify which thread to fetch from.  Only T0 is set to

//  the reset PC.  If the decode unit specifies any other thread, it

//  will fetch from an indeterminate address.

//  The fetch block automatically stalls the machine when an Imiss is

//  detected and there is no thread to switch to.

//

*/

////////////////////////////////////////////////////////////////////////

// Global header file includes

////////////////////////////////////////////////////////////////////////

/*

/* ========== Copyright Header Begin ==========================================

*

* OpenSPARC T1 Processor File: ifu.h

* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

*

* The above named program is free software; you can redistribute it and/or

* modify it under the terms of the GNU General Public

* License version 2 as published by the Free Software Foundation.

*

* The above named program is distributed in the hope that it will be

* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

* General Public License for more details.

*

* You should have received a copy of the GNU General Public

* License along with this work; if not, write to the Free Software

* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

*

* ========== Copyright Header End ============================================

*/

////////////////////////////////////////////////////////////////////////

/*

//

//  Module Name: ifu.h

//  Description:

//  All ifu defines

*/

//--------------------------------------------

// Icache Values in IFU::ICD/ICV/ICT/FDP/IFQDP

//--------------------------------------------

// Set Values

// IC_IDX_HI = log(icache_size/4ways) - 1

// !!IMPORTANT!! a change to IC_LINE_SZ will mean a change to the code as

//   well.  Unfortunately this has not been properly parametrized.

//   Changing the IC_LINE_SZ param alone is *not* enough.

// !!IMPORTANT!! a change to IC_TAG_HI will mean a change to the code as

//   well.  Changing the IC_TAG_HI param alone is *not* enough to

//   change the PA range. 

// highest bit of PA

// Derived Values

// 4095

// number of entries - 1 = 511

// 12

// 28

// 7

// tags for all 4 ways + parity

// 116

// 115

//----------------------------------------------------------------------

// For thread scheduler in IFU::DTU::SWL

//----------------------------------------------------------------------

// thread states:  (thr_state[4:0])

// thread configuration register bit fields

//----------------------------------------------------------------------

// For MIL fsm in IFU::IFQ

//----------------------------------------------------------------------

//---------------------------------------------------

// Interrupt Block

//---------------------------------------------------

//-------------------------------------

// IFQ

//-------------------------------------

// valid bit plus ifill

//`ifdef SPARC_L2_64B

//`else

//`define BANK_ID_HI 8

//`define BANK_ID_LO 7

//`endif

//`define CPX_INV_PA_HI  116

//`define CPX_INV_PA_LO  112

//----------------------------------------

// IFU Traps

//----------------------------------------

// precise

// disrupting

module sparc_ifu_fcl(/*AUTOARG*/

   // Outputs

   fcl_icd_rdreq_bf, fcl_icv_rdreq_bf, fcl_icd_wrreq_bf,

   fcl_ict_wrreq_bf, fcl_icv_wrreq_bf, fcl_icd_index_sel_ifq_bf,

   fcl_ifq_grant_bf, fcl_ifq_icmiss_s1, fcl_ifq_rdreq_s1,

   fcl_ifq_icache_en_s_l, fcl_ifq_thr_s1, fcl_ifq_canthr,

   fcl_itlb_cam_vld_bf, fcl_itlb_cam_bypass_bf, fcl_itlb_addr_mask_l,

   fcl_itlb_cam_real_bf, fcl_itlb_cam_pid_bf, fcl_itlb_wr_vld_bf,

   fcl_itlb_dmp_vld_bf, fcl_itlb_dmp_all_bf, fcl_itlb_tag_rd_vld_bf,

   fcl_itlb_invall_f_l, fcl_itlb_data_rd_vld_bf, fcl_erb_ievld_s1,

   fcl_erb_tevld_s1, fcl_erb_immuevld_s1, ifu_lsu_thrid_s,

   fcl_erb_asi_tid_f, fcl_erb_clear_iferr, fcl_erb_itlbrd_vld_s,

   fcl_erb_itlbrd_data_s, fcl_dec_dslot_s, fcl_dtu_inst_vld_e,

   fcl_dtu_intr_vld_e, fcl_dtu_inst_vld_d, fcl_dtu_ely_inst_vld_d,

   fcl_dec_intr_vld_d, fcl_erb_inst_issue_d, fcl_erb_inst_vld_d1,

   ifu_tlu_inst_vld_m, ifu_exu_inst_vld_e, ifu_exu_inst_vld_w,

   ifu_spu_inst_vld_w, ifu_tlu_inst_vld_w, ifu_tlu_flush_w,

   ifu_tlu_flush_m, fcl_swl_int_activate_i3, fcl_swl_flush_wake_w,

   fcl_swl_flush_w, fcl_dcl_regz_e, ifu_tlu_thrid_e, ifu_tlu_thrid_d,

   ifu_tlu_immu_miss_m, ifu_tlu_priv_violtn_m, ifu_tlu_icmiss_e,

   ifu_tlu_ttype_vld_m, ifu_exu_ttype_vld_m, ifu_mmu_trap_m,

   ifu_tlu_trap_m, ifu_tlu_ttype_m, ifu_tlu_hwint_m,

   ifu_tlu_sftint_m, ifu_tlu_rstint_m, fcl_dtu_rst_thr_w,

   fcl_dtu_resum_thr_w, ifu_tlu_itlb_done, ifu_spu_trap_ack,

   ifu_exu_tid_s2, ifu_exu_ren1_s, ifu_exu_ren2_s, ifu_exu_ren3_s,

   ifu_exu_disable_ce_e, fcl_dtu_sync_intr_d, fcl_dtu_tlzero_d,

   fcl_dtu_privmode_d, fcl_dtu_hprivmode_d, fcl_dtu_hprivmode_w2,

   fcl_dtu_nuke_thr_w, fcl_swl_swout_f, fcl_dtu_stall_bf,

   fcl_swl_swcvld_s, fcl_dtu_thr_f, fcl_imd_oddwin_d,

   fcl_fdp_oddwin_s, fcl_fdp_pcoor_vec_f, fcl_fdp_pcoor_f,

   fcl_fdp_mask32b_f, fcl_fdp_addr_mask_d, fcl_fdp_tctxt_sel_prim,

   fcl_fdp_usenir_sel_nir_s1, fcl_fdp_rbinst_sel_inste_s,

   fcl_fdp_thrtnpc_sel_tnpc_l, fcl_fdp_thrtnpc_sel_npcw_l,

   fcl_fdp_thrtnpc_sel_pcf_l, fcl_fdp_thrtnpc_sel_old_l,

   fcl_fdp_thr_s1_l, fcl_fdp_next_thr_bf_l, fcl_fdp_next_ctxt_bf_l,

   fcl_fdp_nirthr_s1_l, fcl_fdp_thr_s2_l,

   fcl_fdp_tpcbf_sel_pcp4_bf_l, fcl_fdp_tpcbf_sel_brpc_bf_l,

   fcl_fdp_tpcbf_sel_trap_bf_l, fcl_fdp_tpcbf_sel_old_bf_l,

   fcl_fdp_pcbf_sel_nosw_bf_l, fcl_fdp_pcbf_sel_swpc_bf_l,

   fcl_fdp_pcbf_sel_br_bf_l, fcl_fdp_trrbpc_sel_trap_bf_l,

   fcl_fdp_trrbpc_sel_rb_bf_l, fcl_fdp_trrbpc_sel_err_bf_l,

   fcl_fdp_trrbpc_sel_pcs_bf_l, fcl_fdp_noswpc_sel_tnpc_l_bf,

   fcl_fdp_noswpc_sel_old_l_bf, fcl_fdp_noswpc_sel_inc_l_bf,

   fcl_fdp_nextpcs_sel_pce_f_l, fcl_fdp_nextpcs_sel_pcd_f_l,

   fcl_fdp_nextpcs_sel_pcs_f_l, fcl_fdp_nextpcs_sel_pcf_f_l,

   fcl_fdp_inst_sel_curr_s_l, fcl_fdp_inst_sel_switch_s_l,

   fcl_fdp_inst_sel_nir_s_l, fcl_fdp_inst_sel_nop_s_l,

   fcl_fdp_tinst_sel_curr_s_l, fcl_fdp_tinst_sel_rb_s_l,

   fcl_fdp_tinst_sel_old_s_l, fcl_fdp_tinst_sel_ifq_s_l,

   fcl_fdp_dmpthr_l, fcl_fdp_ctxt_sel_dmp_bf_l,

   fcl_fdp_ctxt_sel_sw_bf_l, fcl_fdp_ctxt_sel_curr_bf_l,

   fcl_fdp_rdsr_sel_pc_e_l, fcl_fdp_rdsr_sel_thr_e_l,

   fcl_fdp_rdsr_sel_ver_e_l, so, ifu_reset_l,

   // Inputs

   rclk, grst_l, arst_l, se, sehold, si, rst_tri_en,

   tlu_ifu_flush_pipe_w, exu_ifu_va_oor_m, exu_ifu_oddwin_s,

   spu_ifu_ttype_tid_w2, spu_ifu_ttype_vld_w2, spu_ifu_ttype_w2,

   erb_fcl_spu_uetrap, exu_ifu_regz_e, dcl_fcl_bcregz0_e,

   dcl_fcl_bcregz1_e, dtu_fcl_rollback_g, dtu_fcl_retract_d,

   dtu_fcl_br_inst_d, dtu_fcl_sir_inst_e, dtu_fcl_privop_e,

   dtu_fcl_fpdis_e, dtu_fcl_imask_hit_e, dtu_fcl_illinst_e,

   dtu_fcl_thr_active, dec_fcl_rdsr_sel_pc_d, dec_fcl_rdsr_sel_thr_d,

   ifq_fcl_wrreq_bf, ifq_fcl_icd_wrreq_bf, ifq_fcl_ictv_wrreq_bf,

   ifq_fcl_rdreq_bf, ifq_fcl_asi_tid_bf, ifq_fcl_asird_bf,

   ifq_fcl_invreq_bf, erb_fcl_itlb_ce_d1, erb_dtu_ifeterr_d1,

   erb_fcl_ifet_uevec_d1, erb_fcl_ue_trapvec, erb_fcl_ce_trapvec,

   dtu_fcl_nextthr_bf, dtu_fcl_ntr_s, dtu_fcl_running_s,

   dtu_fcl_flush_sonly_e, fdp_fcl_swc_s2, fdp_fcl_va2_bf,

   itlb_fcl_tlbmiss_f_l, itlb_fcl_priv_s1, itlb_fcl_cp_s1,

   itlb_fcl_imiss_s_l, fdp_fcl_pc_oor_vec_f, fdp_fcl_pc_oor_e,

   fdp_fcl_op_s, fdp_fcl_op3_s, fdp_fcl_ibit_s, lsu_ifu_stallreq,

   ffu_ifu_stallreq, wbm_spc_stallreq, ifq_fcl_stallreq, dtu_inst_anull_e,

   ifq_fcl_fill_thr, ifq_fcl_flush_sonly_e, tlu_ifu_trap_tid_w1,

   tlu_ifu_trappc_vld_w1, tlu_ifu_trapnpc_vld_w1,

   tlu_lsu_pstate_priv, tlu_lsu_pstate_am, tlu_hpstate_priv,

   tlu_lsu_redmode, tlu_hpstate_enb, lsu_ifu_addr_real_l,

   lsu_pid_state0, lsu_pid_state1, lsu_pid_state2, lsu_pid_state3,

   lsu_ifu_icache_en, lsu_ifu_dc_parity_error_w2, lsu_ifu_t0_tlz,

   lsu_ifu_t1_tlz, lsu_ifu_t2_tlz, lsu_ifu_t3_tlz, tlu_ifu_hwint_i3,

   tlu_ifu_pstate_ie, tlu_ifu_sftint_vld, tlu_ifu_hintp_vld,

   tlu_ifu_rerr_vld, tlu_ifu_rstthr_i2, tlu_ifu_rstint_i2,

   tlu_ifu_resumint_i2, tlu_ifu_nukeint_i2, tlu_itlb_wr_vld_g,

   tlu_itlb_dmp_vld_g, tlu_itlb_dmp_all_g, tlu_itlb_data_rd_g,

   tlu_itlb_tag_rd_g, tlu_itlb_invalidate_all_g, tlu_fcl_dmp_pid_bf,

   tlu_fcl_dmp_real_bf, tlu_idtlb_dmp_thrid_g, exu_ifu_ecc_ce_m,

   ffu_ifu_fst_ce_w

   );

   input  rclk,

                grst_l,

          arst_l,

                se,

          sehold,

                si;

   input  rst_tri_en;

   input  tlu_ifu_flush_pipe_w; // flush pipe on a trap

   input  exu_ifu_va_oor_m;

   input [3:0] exu_ifu_oddwin_s;

   input [1:0] spu_ifu_ttype_tid_w2;

   input       spu_ifu_ttype_vld_w2;

   input       spu_ifu_ttype_w2;

   input [3:0] erb_fcl_spu_uetrap;  // use m3

//   input       dtu_fcl_brtaken_e;    // branch taken

   input       exu_ifu_regz_e;

   input       dcl_fcl_bcregz0_e,

               dcl_fcl_bcregz1_e;

   input       dtu_fcl_rollback_g;

   input       dtu_fcl_retract_d;

   input       dtu_fcl_br_inst_d;

   input       dtu_fcl_sir_inst_e;

   input       dtu_fcl_privop_e,

                           dtu_fcl_fpdis_e,

               dtu_fcl_imask_hit_e,

                           dtu_fcl_illinst_e;

   input [3:0] dtu_fcl_thr_active;

   input       dec_fcl_rdsr_sel_pc_d,

                           dec_fcl_rdsr_sel_thr_d;

   input       ifq_fcl_wrreq_bf;

   input       ifq_fcl_icd_wrreq_bf,

                           ifq_fcl_ictv_wrreq_bf,

                           ifq_fcl_rdreq_bf;

   input [1:0] ifq_fcl_asi_tid_bf;

   input       ifq_fcl_asird_bf;

   input       ifq_fcl_invreq_bf;

   input       erb_fcl_itlb_ce_d1;

   input       erb_dtu_ifeterr_d1;

   input [3:0] erb_fcl_ifet_uevec_d1,

                           erb_fcl_ue_trapvec,

                           erb_fcl_ce_trapvec;

   input [3:0] dtu_fcl_nextthr_bf;   // thread to switch to

   input       dtu_fcl_ntr_s,        // next thread ready for ex

               dtu_fcl_running_s;

   input       dtu_fcl_flush_sonly_e;

//               dec_fcl_kill4sta_e;

   input       fdp_fcl_swc_s2,       // instruction switch condition

                           fdp_fcl_va2_bf,       // bit 2 of vaddr

                           itlb_fcl_tlbmiss_f_l,  // itlb miss

                           itlb_fcl_priv_s1,     // privileged access page

                           itlb_fcl_cp_s1,       // uncached access page

                           itlb_fcl_imiss_s_l;     // icache miss in s1

   input [3:0] fdp_fcl_pc_oor_vec_f;

   input       fdp_fcl_pc_oor_e;

   input [1:0] fdp_fcl_op_s;

   input [5:2] fdp_fcl_op3_s;

   input       fdp_fcl_ibit_s;

   input       lsu_ifu_stallreq,

                     ffu_ifu_stallreq, wbm_spc_stallreq,

               ifq_fcl_stallreq;

   input       dtu_inst_anull_e;

   input [3:0] ifq_fcl_fill_thr;     // fill inst goes to this

                                         // thread instruction register

   input       ifq_fcl_flush_sonly_e;

   input [1:0] tlu_ifu_trap_tid_w1;     // thr for which trappc is sent

   input       tlu_ifu_trappc_vld_w1,   // ld pc on trap or done/retry

                           tlu_ifu_trapnpc_vld_w1;  // ld Npc for a retry

   input [3:0] tlu_lsu_pstate_priv;     // may need to flop these three

   input [3:0] tlu_lsu_pstate_am;

   input [3:0] tlu_hpstate_priv;

   input [3:0] tlu_lsu_redmode;

   input [3:0] tlu_hpstate_enb;

   input [3:0] lsu_ifu_addr_real_l;

   input [2:0] lsu_pid_state0,

               lsu_pid_state1,

               lsu_pid_state2,

               lsu_pid_state3;

   input [3:0] lsu_ifu_icache_en;

   input       lsu_ifu_dc_parity_error_w2;

//   input       lsu_ifu_flush_ireg;  // not needed any more

   input       lsu_ifu_t0_tlz,

                           lsu_ifu_t1_tlz,

                           lsu_ifu_t2_tlz,

                           lsu_ifu_t3_tlz;

   input [3:0] tlu_ifu_hwint_i3,        // normal interrupt

                           tlu_ifu_pstate_ie,

                           tlu_ifu_sftint_vld,

                           tlu_ifu_hintp_vld,

                           tlu_ifu_rerr_vld,

                           tlu_ifu_rstthr_i2;       // reset or idle interrupt

   input       tlu_ifu_rstint_i2,       // reset to a dead thread

                           tlu_ifu_resumint_i2,

                           tlu_ifu_nukeint_i2;

   input       tlu_itlb_wr_vld_g,

                           tlu_itlb_dmp_vld_g,

               tlu_itlb_dmp_all_g,

                           tlu_itlb_data_rd_g,

                           tlu_itlb_tag_rd_g;

   input       tlu_itlb_invalidate_all_g;

   input [2:0] tlu_fcl_dmp_pid_bf;

   input       tlu_fcl_dmp_real_bf;

   input [1:0] tlu_idtlb_dmp_thrid_g;

   input       exu_ifu_ecc_ce_m;

   input       ffu_ifu_fst_ce_w;

   // to icd

   output      fcl_icd_rdreq_bf,

               fcl_icv_rdreq_bf,

                           fcl_icd_wrreq_bf,

                           fcl_ict_wrreq_bf,

                           fcl_icv_wrreq_bf;

   output      fcl_icd_index_sel_ifq_bf;

   output      fcl_ifq_grant_bf;

   // to ifq

   output      fcl_ifq_icmiss_s1;  // if icache turned off

   output      fcl_ifq_rdreq_s1;

   output      fcl_ifq_icache_en_s_l;

   output [1:0] fcl_ifq_thr_s1;

   output [3:0] fcl_ifq_canthr;     // cancel ifetch to this thread

   // to itlb

   output       fcl_itlb_cam_vld_bf,

                fcl_itlb_cam_bypass_bf,

                            fcl_itlb_addr_mask_l,

                fcl_itlb_cam_real_bf;

   output [2:0] fcl_itlb_cam_pid_bf;

   output       fcl_itlb_wr_vld_bf,

                            fcl_itlb_dmp_vld_bf,

                fcl_itlb_dmp_all_bf,

                            fcl_itlb_tag_rd_vld_bf,

                            fcl_itlb_invall_f_l,

                            fcl_itlb_data_rd_vld_bf;

   // to erb

   output       fcl_erb_ievld_s1,

                            fcl_erb_tevld_s1,

                            fcl_erb_immuevld_s1;

   output [1:0] ifu_lsu_thrid_s,

                            fcl_erb_asi_tid_f;

   output [3:0] fcl_erb_clear_iferr;

   output       fcl_erb_itlbrd_vld_s,

                            fcl_erb_itlbrd_data_s;

   output       fcl_dec_dslot_s;

   output       fcl_dtu_inst_vld_e,

                fcl_dtu_intr_vld_e,

                            fcl_dtu_inst_vld_d,

                fcl_dtu_ely_inst_vld_d,

                fcl_dec_intr_vld_d,

                            fcl_erb_inst_issue_d,

                            fcl_erb_inst_vld_d1,

                            ifu_tlu_inst_vld_m,

//                          ifu_lsu_inst_vld_m,

                            ifu_exu_inst_vld_e,

                            ifu_exu_inst_vld_w,

                            ifu_spu_inst_vld_w,

                            ifu_tlu_inst_vld_w;

   output       ifu_tlu_flush_w;

   output       ifu_tlu_flush_m;

   output [3:0] fcl_swl_int_activate_i3;

   output       fcl_swl_flush_wake_w;

   output       fcl_swl_flush_w;

   output       fcl_dcl_regz_e;

   // to tlu

   output [1:0] ifu_tlu_thrid_e;

   output [1:0] ifu_tlu_thrid_d;

   output       ifu_tlu_immu_miss_m,

                            ifu_tlu_priv_violtn_m;

   output       ifu_tlu_icmiss_e;

   output       ifu_tlu_ttype_vld_m;

   output       ifu_exu_ttype_vld_m;

   output       ifu_mmu_trap_m;

   output       ifu_tlu_trap_m;

   output [8:0] ifu_tlu_ttype_m;

   output       ifu_tlu_hwint_m;

   output       ifu_tlu_sftint_m;

//   output       ifu_tlu_hintp_m;

//   output       ifu_tlu_rerr_m;

   output       ifu_tlu_rstint_m;

   output       fcl_dtu_rst_thr_w;

   output       fcl_dtu_resum_thr_w;

   output       ifu_tlu_itlb_done;

   output       ifu_spu_trap_ack;

   // to exu

   output [1:0] ifu_exu_tid_s2;

   output       ifu_exu_ren1_s,

                            ifu_exu_ren2_s,

                            ifu_exu_ren3_s;

   output       ifu_exu_disable_ce_e;  // to exu and ffu

   // to dtu

   output       fcl_dtu_sync_intr_d;

   output       fcl_dtu_tlzero_d;

   output       fcl_dtu_privmode_d;

   output       fcl_dtu_hprivmode_d;

   output       fcl_dtu_hprivmode_w2;

   output       fcl_dtu_nuke_thr_w;

   output       fcl_swl_swout_f;

   output       fcl_dtu_stall_bf;

//   output       fcl_dtu_switch_s;     // indicates to the DTU that a

                                      // switch took place to next_thr

   output       fcl_swl_swcvld_s;

   output [3:0] fcl_dtu_thr_f;

   output       fcl_imd_oddwin_d;

   // to fdp

   output       fcl_fdp_oddwin_s;

   output [3:0] fcl_fdp_pcoor_vec_f;

   output       fcl_fdp_pcoor_f;

   output       fcl_fdp_mask32b_f;

   output       fcl_fdp_addr_mask_d;

   output [3:0] fcl_fdp_tctxt_sel_prim;

   // 2:1 mux selects

   output       fcl_fdp_usenir_sel_nir_s1;   // same as usenir_d2

   output [3:0] fcl_fdp_rbinst_sel_inste_s;

   output [3:0] fcl_fdp_thrtnpc_sel_tnpc_l,  // load npc

                            fcl_fdp_thrtnpc_sel_npcw_l,

                            fcl_fdp_thrtnpc_sel_pcf_l,

                            fcl_fdp_thrtnpc_sel_old_l;

   output [3:0] fcl_fdp_thr_s1_l;            // s1 thr for thrNIR input mux

   // other mux selects   

   output [3:0] fcl_fdp_next_thr_bf_l,  // for thrpc output mux

                fcl_fdp_next_ctxt_bf_l, // for ctxt output mux

                            fcl_fdp_nirthr_s1_l,    // select NIR in s1 stage

                            fcl_fdp_thr_s2_l;       // s2 thr for thr_inst_reg

   output [3:0] fcl_fdp_tpcbf_sel_pcp4_bf_l, // selects for thread PC muxes

                            fcl_fdp_tpcbf_sel_brpc_bf_l,

                            fcl_fdp_tpcbf_sel_trap_bf_l,

                            fcl_fdp_tpcbf_sel_old_bf_l;

   output       fcl_fdp_pcbf_sel_nosw_bf_l,      // F stage pc mux selects

                            fcl_fdp_pcbf_sel_swpc_bf_l,

                            fcl_fdp_pcbf_sel_br_bf_l;

   output [3:0] fcl_fdp_trrbpc_sel_trap_bf_l,

                            fcl_fdp_trrbpc_sel_rb_bf_l,

                            fcl_fdp_trrbpc_sel_err_bf_l,

                            fcl_fdp_trrbpc_sel_pcs_bf_l;

   output       fcl_fdp_noswpc_sel_tnpc_l_bf,    // next pc select,

                            fcl_fdp_noswpc_sel_old_l_bf,                 // dont need anymore

                            fcl_fdp_noswpc_sel_inc_l_bf;

   output [3:0] fcl_fdp_nextpcs_sel_pce_f_l,

                            fcl_fdp_nextpcs_sel_pcd_f_l,

                            fcl_fdp_nextpcs_sel_pcs_f_l,

                            fcl_fdp_nextpcs_sel_pcf_f_l;

   output       fcl_fdp_inst_sel_curr_s_l,   // selects for inst_s2

                            fcl_fdp_inst_sel_switch_s_l,

                            fcl_fdp_inst_sel_nir_s_l,

                            fcl_fdp_inst_sel_nop_s_l;

   output [3:0] fcl_fdp_tinst_sel_curr_s_l,  // selects for tinst regs

                            fcl_fdp_tinst_sel_rb_s_l,

                            fcl_fdp_tinst_sel_old_s_l,

                            fcl_fdp_tinst_sel_ifq_s_l;

   output [3:0] fcl_fdp_dmpthr_l;

   output       fcl_fdp_ctxt_sel_dmp_bf_l,

                            fcl_fdp_ctxt_sel_sw_bf_l,

                            fcl_fdp_ctxt_sel_curr_bf_l;

   output       fcl_fdp_rdsr_sel_pc_e_l,

                fcl_fdp_rdsr_sel_thr_e_l,

                fcl_fdp_rdsr_sel_ver_e_l;

   output       so,

                ifu_reset_l;

   //----------------------------------------------------------------------

   // Declarations

   //----------------------------------------------------------------------

   reg [3:0]    fcl_fdp_tpcbf_sel_old_bf_l,

                            fcl_fdp_tpcbf_sel_pcp4_bf_l,

                            fcl_fdp_tpcbf_sel_trap_bf_l,

                            fcl_fdp_tpcbf_sel_brpc_bf_l;

   wire         fcl_fdp_inst_sel_nop_s_l,

                fcl_fdp_inst_sel_nir_s_l,

                            fcl_fdp_inst_sel_curr_s_l,

                            fcl_fdp_inst_sel_switch_s_l;

   // local signals

   wire         //sw_itlb_on,

                sw_itlb_real,

                            sw_itlb_am,

                            //this_itlb_on,

                this_itlb_real,

                            itlb_on;

   wire [3:0]   xlate_en,

                xlate_en_d1;

   wire [2:0]   sw_pid_bf,

                curr_pid_bf;

   wire         pid_sel_sw,

                pid_sel_curr,

                pid_sel_dmp;

   wire         itlb_access_gnt,

                            itlb_access_en,

                itlb_write_en,

                ctxt_sel_dmp,

                            itlb_access_done,

                itlb_write_done,

                            itlb_rd_access_done,

                            itlb_rd_access_done_d1,

                            itlb_rd_access_done_d2,

                            itlb_rd_req_bf,

                            itlb_rd_req_f,

                            itlb_data_rd_f,

                itlb_data_rd_s;

   wire [1:0]   asi_tid_bf;

   wire [1:0]   spu_tid_w2;

   wire         fetch_bf,       // fetch an instruction next cycle

                allow_ifq_access_icd_bf,

                inst_access_bf,

                ia1_bf,

                ia0_bf,

                no_instacc_bf;

   wire         cam_vld_bf,

                tlb_invall_bf,

                tlb_invall_f,

//                tlb_invall_req_bf,

                inst_vld_bf;

   wire         rdreq_bf,     // read from I$ next cycle

                            rdreq_f;

   wire         ic_wrreq_bf;

   wire         running_s2,

                valid_s,

                            running_s1,

                ely_running_s1,

                            running_d,

                            running_e,

                            running_m,

                        inst_vld_f,

                            inst_vld_s,

                inst_vld_s_crit,

                            inst_vld_s1,

                            inst_vld_s2,    // valid bit of S stage

                                            // instruction.  If this is 0,

                                            // convert inst to no-op

                            inst_vld_d,

                inst_vld_d_crit,

                            inst_vld_d1,

                            inst_vld_e,

                            inst_vld_qual_e,

                            inst_vld_m,

                            inst_vld_w;

   wire         inst_vld_w_crit;

   wire         no_iftrap_m,

                no_iftrap_w;

   wire         stall_f,

                            stall_s1,

                            stall_s1_nxt,

                ely_stall_thisthr_f,

                part_stall_thisthr_f,

                            stall_thisthr_f;

   wire         rdreq_s1;

   wire         usenir_bf,

                            usenir_f,

                            usenir_s1;

   wire [3:0]   tinst_vld_s,    // valid bit of thr instr register

                                            // in s stage

                            tinst_vld_nxt;

   wire [3:0]   val_thr_s1,

                            val_thr_f,

                thr_e_v2,

                            val_thr_e;

   wire         flush_sonly_qual_e,

                flush_sonly_all_m,

                flush_sonly_qual_m,

                ims_flush_sonly_m,

                ims_flush_sonly_w,

                ims_flush_coll_m,

                ims_flush_coll_w,

                flush_sonly_m;

   wire         flush_pipe_w;

   wire         kill_thread_d,

//                          kill_thread_e,

                            kill_thread_m,

                kill_local_m,

                ely_kill_thread_s2,

                ely_kill_thread_m,

                            kill_thread_s2;

   wire [3:0]   clear_s_d1,