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// ========== Copyright Header Begin ==========================================

// 

// OpenSPARC T1 Processor File: sparc_ifu_ifqctl.v

// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

// 

// The above named program is free software; you can redistribute it and/or

// modify it under the terms of the GNU General Public

// License version 2 as published by the Free Software Foundation.

// 

// The above named program is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

// General Public License for more details.

// 

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// ========== Copyright Header End ============================================

`ifdef SIMPLY_RISC_TWEAKS

`define SIMPLY_RISC_SCANIN .si(0)

`else

`define SIMPLY_RISC_SCANIN .si()

`endif

////////////////////////////////////////////////////////////////////////

/*

//  Module Name: sparc_ifu_ifqctl

//  Description:

//  Contains the control logic for the ifq and mil.

*/

////////////////////////////////////////////////////////////////////////

// Global header file includes

////////////////////////////////////////////////////////////////////////

`include "iop.h"

`include "ifu.h"

module sparc_ifu_ifqctl(/*AUTOARG*/

   // Outputs

   ifu_lsu_inv_clear, ifu_lsu_ibuf_busy, ifu_lsu_asi_ack,

   ifu_lsu_ldxa_illgl_va_w2, ifu_lsu_fwd_wr_ack, ifu_lsu_pcxreq_d,

   ifu_lsu_destid_s, ifu_tlu_l2imiss, ifq_fcl_stallreq,

   ifq_swl_stallreq, ifq_fcl_flush_sonly_e, ifq_fcl_wrreq_bf,

   ifq_fcl_rdreq_bf, ifq_fcl_icd_wrreq_bf, ifq_fcl_ictv_wrreq_bf,

   ifq_erb_fwdrd_bf, ifq_erb_rdtag_f, ifq_erb_rdinst_f,

   ifq_erb_asi_erren_i2, ifq_erb_asi_errstat_i2,

   ifq_erb_asi_errinj_i2, ifq_erb_asi_erraddr_i2,

   ifq_erb_asi_imask_i2, ifq_erb_asiwr_i2, ifq_fcl_asird_bf,

   ifq_fcl_asi_tid_bf, ifq_erb_ue_rep, ifq_erb_ce_rep, ifq_erb_l2_ue,

   ifq_erb_io_ue, ifq_erb_ifet_ce, ifq_erb_l2err_tid,

   ifq_icv_wrdata_bf, ifq_icd_worden_bf, ifq_fcl_fill_thr,

   ifq_dtu_thrrdy, ifq_dtu_pred_rdy, ifc_ifd_filladdr4_i2,

   ifc_ifd_reqvalid_e, ifc_ifd_idx_sel_fwd_i2, ifc_ifd_errinv_e,

   ifc_ifd_uncached_e, ifc_ifd_thrid_e, ifc_ifd_pcxline_adj_d,

   ifc_inv_asireq_i2, ifc_ifd_repway_s, ifq_sscan_data,

   ifc_ifd_milfill_sel_i2_l, ifc_ifd_finst_sel_l,

   ifc_ifd_milreq_sel_d_l, ifc_ifd_ifqbyp_sel_fwd_l,

   ifc_ifd_ifqbyp_sel_inq_l, ifc_ifd_ifqbyp_sel_asi_l,

   ifc_ifd_ifqbyp_sel_lsu_l, ifc_ifd_ifqbyp_en_l,

   ifc_ifd_addr_sel_bist_i2_l, ifc_ifd_addr_sel_asi_i2_l,

   ifc_ifd_addr_sel_old_i2_l, ifc_ifd_addr_sel_fill_i2_l,

   ifq_icd_data_sel_bist_i2, ifq_icd_data_sel_fill_i2,

   ifq_icd_data_sel_old_i2, ifc_ifd_ldmil_sel_new, ifc_ifd_ld_inq_i1,

   ifc_inv_ifqadv_i2, so,

   // Inputs

   lsu_ifu_cpxpkt_wayvld_i1, ifd_ifc_milhit_s, ifd_ifc_instoffset0, ifd_ifc_instoffset1,

   ifd_ifc_instoffset2, ifd_ifc_instoffset3, ifd_ifc_cpxvalid_i1,

   ifd_ifc_cpxreq_i1, ifd_ifc_cpxreq_nxt, ifd_ifc_cpxthr_nxt,

   ifd_ifc_cpxvld_i2, ifd_ifc_iobpkt_i2, ifd_ifc_4bpkt_i2,

   ifd_ifc_cpxnc_i2, ifd_ifc_fwd2ic_i2, ifd_ifc_cpxce_i2,

   ifd_ifc_cpxue_i2, ifd_ifc_cpxms_i2, ifd_ifc_miladdr4_i2,

   ifd_ifc_asiaddr_i2, ifd_ifc_asi_vachklo_i2, ifd_ifc_destid0,

   ifd_ifc_destid1, ifd_ifc_destid2, ifd_ifc_destid3,

   ifd_ifc_newdestid_s, ifd_ifc_pcxline_d, inv_ifc_inv_pending,

   fcl_ifq_icmiss_s1, fcl_ifq_rdreq_s1, fcl_ifq_thr_s1,

   fcl_ifq_canthr, fcl_ifq_grant_bf, dtu_ifq_kill_latest_d,

   erb_ifq_ifeterr_d1, erb_ifq_itlberr_s1, lsu_ifu_pcxpkt_ack_d,

   lsu_ifu_direct_map_l1, lsu_ifu_asi_vld, lsu_ifu_asi_state,

   lsu_ifu_asi_load, lsu_ifu_asi_thrid, fcl_ifq_icache_en_s_l,

   mbist_ifq_run_bist, mbist_icache_write, mbist_icache_read,

   ctu_sscan_tid, rclk, se, si, gdbginit_l, arst_l, grst_l,

   rst_tri_en, sehold

   );

   input          lsu_ifu_cpxpkt_wayvld_i1;

   input [3:0]     ifd_ifc_milhit_s;      // if an Imiss hits in MIL

   input [1:0]    ifd_ifc_instoffset0; // to select inst to TIR

   input [1:0]    ifd_ifc_instoffset1; // to select inst to TIR

   input [1:0]    ifd_ifc_instoffset2; // to select inst to TIR

   input [1:0]    ifd_ifc_instoffset3; // to select inst to TIR

   input         ifd_ifc_cpxvalid_i1;

   input [`CPX_RQ_SIZE:0] ifd_ifc_cpxreq_i1;

   input [3:0]   ifd_ifc_cpxreq_nxt;

   input [1:0]   ifd_ifc_cpxthr_nxt;

   input         ifd_ifc_cpxvld_i2;

   input         ifd_ifc_iobpkt_i2;

   input         ifd_ifc_4bpkt_i2;

   input         ifd_ifc_cpxnc_i2;

   input         ifd_ifc_fwd2ic_i2;

   input         ifd_ifc_cpxce_i2,

                             ifd_ifc_cpxue_i2,

                 ifd_ifc_cpxms_i2;

   input [3:0]   ifd_ifc_miladdr4_i2;

   input [3:2]   ifd_ifc_asiaddr_i2;

   input         ifd_ifc_asi_vachklo_i2;

   input [2:0]   ifd_ifc_destid0,

                             ifd_ifc_destid1,

                             ifd_ifc_destid2,

                             ifd_ifc_destid3,

                             ifd_ifc_newdestid_s;

   input [4:2]   ifd_ifc_pcxline_d;

//   input [7:0]   ifd_ifc_mil_repway_s;   

   input         inv_ifc_inv_pending;

   input         fcl_ifq_icmiss_s1;   // icache miss

   input         fcl_ifq_rdreq_s1;

   input [1:0]   fcl_ifq_thr_s1;

   input [3:0]   fcl_ifq_canthr;        // cancel the imiss reqs to

                                        // these threads

   input         fcl_ifq_grant_bf;

   input         dtu_ifq_kill_latest_d;

   input         erb_ifq_ifeterr_d1;

   input         erb_ifq_itlberr_s1;

   input         lsu_ifu_pcxpkt_ack_d;

   input         lsu_ifu_direct_map_l1;

   input         lsu_ifu_asi_vld;

   input [7:0]   lsu_ifu_asi_state;

   input         lsu_ifu_asi_load;

   input [1:0]   lsu_ifu_asi_thrid;

   input         fcl_ifq_icache_en_s_l;

   input         mbist_ifq_run_bist,

                 mbist_icache_write,

                             mbist_icache_read;

   input [3:0]   ctu_sscan_tid;

   input         rclk,

                 se,

                 si,

                 gdbginit_l,

                 arst_l,

                 grst_l;

   input         rst_tri_en;

   input         sehold;

   // outputs

   output        ifu_lsu_inv_clear;

   output        ifu_lsu_ibuf_busy;

   output        ifu_lsu_asi_ack;

   output        ifu_lsu_ldxa_illgl_va_w2;

   output        ifu_lsu_fwd_wr_ack;

   output        ifu_lsu_pcxreq_d;

   output [2:0]  ifu_lsu_destid_s;

   output [3:0]  ifu_tlu_l2imiss;

   output        ifq_fcl_stallreq;

   output        ifq_swl_stallreq;

   output        ifq_fcl_flush_sonly_e;

   output        ifq_fcl_wrreq_bf;

   output        ifq_fcl_rdreq_bf;

   output        ifq_fcl_icd_wrreq_bf,

                             ifq_fcl_ictv_wrreq_bf;

   output        ifq_erb_fwdrd_bf;

   output        ifq_erb_rdtag_f;

   output        ifq_erb_rdinst_f;

   output        ifq_erb_asi_erren_i2;

   output        ifq_erb_asi_errstat_i2;

   output        ifq_erb_asi_errinj_i2;

   output        ifq_erb_asi_erraddr_i2;

   output        ifq_erb_asi_imask_i2;

   output        ifq_erb_asiwr_i2;

   output        ifq_fcl_asird_bf;

   output [1:0]  ifq_fcl_asi_tid_bf;

   output        ifq_erb_ue_rep;

   output        ifq_erb_ce_rep;

   output        ifq_erb_l2_ue;

   output        ifq_erb_io_ue;

   output        ifq_erb_ifet_ce;

   output [1:0]  ifq_erb_l2err_tid;

   output        ifq_icv_wrdata_bf;

   output [3:0]  ifq_icd_worden_bf;

   output [3:0]  ifq_fcl_fill_thr;     // should be same stage as 

   // fill_inst

   output [3:0]  ifq_dtu_thrrdy;

   output [3:0]  ifq_dtu_pred_rdy;

   output        ifc_ifd_filladdr4_i2;

   output        ifc_ifd_reqvalid_e;

   output        ifc_ifd_idx_sel_fwd_i2;

   output        ifc_ifd_errinv_e;

   output        ifc_ifd_uncached_e;

   output [1:0]  ifc_ifd_thrid_e;

   output [4:2]  ifc_ifd_pcxline_adj_d;

   output        ifc_inv_asireq_i2;

   output [1:0]  ifc_ifd_repway_s;

   output [3:0]  ifq_sscan_data;

   // mux selects

   output [3:0]  ifc_ifd_milfill_sel_i2_l;

   output [3:0]  ifc_ifd_finst_sel_l;

   output [3:0]  ifc_ifd_milreq_sel_d_l;

   output        ifc_ifd_ifqbyp_sel_fwd_l, // select next input to ifq pipe

                             ifc_ifd_ifqbyp_sel_inq_l,

                             ifc_ifd_ifqbyp_sel_asi_l,

                             ifc_ifd_ifqbyp_sel_lsu_l;

         output        ifc_ifd_ifqbyp_en_l;

   output        ifc_ifd_addr_sel_bist_i2_l,

                             ifc_ifd_addr_sel_asi_i2_l,

                 ifc_ifd_addr_sel_old_i2_l,

                             ifc_ifd_addr_sel_fill_i2_l;

   output        ifq_icd_data_sel_bist_i2,

                             ifq_icd_data_sel_fill_i2,

                             ifq_icd_data_sel_old_i2;

   // 2:1 mux selects

   output [3:0]  ifc_ifd_ldmil_sel_new;     // mil load enable

   output        ifc_ifd_ld_inq_i1;

   output        ifc_inv_ifqadv_i2;         // move a new op from ifq

         // pipe to icache

   output        so;

   //----------------------------------------------------------------------

   // Declarations

   //----------------------------------------------------------------------   

   // local signals

   wire [3:0]    thr_s1,      // s1 thread which missed in I$

                             thr_d1,

                 thr_e1,

                             dfthr_f,     // thread currently being filled in I$

                 dfthr_next_i2,

                             dfthr_i2,    // next thread to be filled from CPX

                 milfthr_i2,

                             dpcxthr_s,

                             dpcxthr_d;   // thread being transmitted to lsu

   wire [1:0]    thrid_d,

                 thrid_e;

   wire [3:0]    pcx_accept_d;

   wire          req_pending_d,

//                           req_pending_e,

                             req_accept_d,

//                 can_pcx_d,

                 pcxreq_vbit_d;

   wire [3:0]    comp_valid_s,

                             mil_valid_s,

                 mil_cancel;

   wire [3:0]    finst_i2,

                 finst0,

                 finst1,

                 finst2,

                 finst3;

   wire [2:0]    milchld0,

                             milchld1,

                             milchld2,

                             milchld3,

                             next_milchld,

                             milchld_d1;

   wire          milchld_vld_f,

                             next_milchld_i2,

                             milchld_vld_i2;

   wire [3:0]    mil0_state,

                 mil1_state,

                 mil2_state,

                 mil3_state;

   wire [2:0]    i2out;         // state machine output in i2 stage

   wire          any_milhit_qual_s,     // hit in MIL

                 any_qualhit_or_io_s,

                             icmiss_qual_s,

//                           reqq_empty,    // no pending requests in MIL

                             oldreq_valid,

                             next_wrreq_i2,

                             wrreq_f;

   wire          block_fetch_s1,

                 block_fetch_d1;

   wire [3:0]    mil_thr_ready,

                 all_retry_rdy_e1,

                 all_retry_rdy_m1;

   wire          retry_rdy_final_d1,

                 retry_rdy_e1;

   wire          rst_starv_ctr_l;

   wire          starv_alert;

   wire [3:0]    milhit_vec_s;

   wire          any_milhit_s;

   wire [1:0]    rand_repway_s;

//   wire [1:0]    mil_repway_s;

   wire [3:0]    errthr_d1,

                             err_vec_d1,

                             err_req;

   wire          errinv_d1;

   wire          ifeterr_qual_d1,

                 ifeterr_e1;

   wire          thr_match_d1e1;

   wire          ifqadv_i1;

   wire          ifqadvi2_nxt,

                 ifqadv_i2_ff;

   wire          access_grant_l;

   wire          addrbit4_i2;

   wire          addrbit4_nxt_i2;

   wire [3:0]    cpxreq_i2;

   wire [1:0]    cpxthr_i2;

   wire          uncached_i2,

                 uncached_s,

                 mil_vld_i2,

                 mil_uncan_i2,

                 mil_nc_i2,

                 mil_nc_e,

                 mil_nc_d,

                             uncached_fill_i2,

                             uncached_f;

   wire [3:0]    mil_nc_vec,

                 mil_nc_vec_nxt;

   wire [3:0]    pcxreq_s,          // req bit from MIL

                 pcxreq_qual_s,

//                           newpcxreq_s,       // valid new request from latest miss

//                           oldpcxreq_s,

                             rr_gnt,          // round robin grant signal

                             fill_addr4_i2;    // fill address bit 4 - determines

         // which 16B of the 32B line gets

         // written. Assume 0 first then 1

   wire          newreq_valid,    // latest S stage miss creates request.

                             nextreq_valid_s, // if either a new req from i$ or old

                                         // req from MIL is made in this cycle.

                             req_valid_d;     // req to LSU is valid

   wire          inq_vld,

                             inq_vld_nxt;

   wire          ic_pkt_i1;

//   wire          fill_this16b;

   wire [1:0]    filltid_i2,

                             next_filltid_i2,

                             filltid_f;

   wire          imissrtn_i2,   // input cpx is ifill return

                 imissrtn_next_i2,

                 imissrtn_f,

                             imissrtn_i1;   // pkt in inq is ifill ret

   wire          invalidate_i1;

   wire [3:0]    icmiss_thr_s,

                             icmiss_thr_d;

   wire          icmiss_d1,

                 icmiss_qual_d1;

   wire          canthr_s1,

                 canthr_d1,

                 canthr_s1_del1;

   wire          itlberr_d1;

   wire [2:0]    old_destid_s;

   wire          destid_iob_s,

                 destid_iob_d;

   wire          iosp_d1_l,

                 n763;

   wire [3:0]    wrt_tir;

   wire [3:0]    wr_complete_f;

   wire [3:0]    pred_rdy_i2;

   wire [3:0]    fill_retn_thr_i2;

   wire          filladdr4_f;

   wire [3:0]    milhit_to_thr_s,

                             icmiss_for_milchk,

                 qualhit_pe_s,

                 qualhit_or_io_s;

//                           milhit_qual_s;

   wire          l2_ue_i2,

                             l2_ce_i2,

                             io_ue_i2;

   wire          l2_miss_i2,

                 l2_miss_f;

//   wire [3:0]    l2ms_thr;

   wire          ce_rep_i2,

                             ue_rep_i2;

   wire          fwdreq_i2,

                 fwdreq_i3,

                 fwd_stall,

                 fwdwr_i3,

                 fwdrd_i3;

   wire          cpxnc_i3;

   wire          stallreq_d0,

                 stallreq_d1;

   wire          ifu_asireq_i1,

                 ifu_asireq_i0,

                 byp_sel_asi_l,

                 asird_i1,

                             asireq_i2,

                 asireq_i2_l,

                             asi_load_i1,

                             asi_load_i2,

                             asi_vld_next,

                 asi_vld_i0,

                 asi_vld_qual_i0;

   wire [7:0]    asi_state_i1;

   wire          asi_ic_data_i1,

                             asi_ic_data_i2,

                             asi_ic_tag_i1,

                             asi_ic_tag_i2;

   wire          asi_erren_i1,

                             asi_errstat_i1,

                             asi_errinj_i1,

                             asi_erraddr_i1,

                             asi_imask_i1;

   wire          asi_ic_data_unchk_i1,

                             asi_ic_tag_unchk_i1;

   wire          asi_erren_unchk_i1,

                             asi_errstat_unchk_i1,

                             asi_errinj_unchk_i1,

                             asi_erraddr_unchk_i1,

                             asi_imask_unchk_i1;

   wire          illva_i0,

                 illva_i1,

                 illva_i2,

                 illva_f,

                 illva_s,

                 illva_w2;

   wire [3:0]    word_sel_i2;

   wire          bist_op;

   wire          rdinst_bf,

                             rd_tag_bf;

   wire          errpkt_i1;

   wire          stpkt_i1,

                 strmack_i1,

                             ldpkt_i1,

                             evpkt_i1,

                             errpkt_i2;

   wire          icv_wrdata_i2,

                             icv_wbit_i2,

                             icv_wrdata_f;

   wire          rst_way_lfsr;

   wire          inq_wayvld_i1;

   wire          inq_wayvld_i1_nxt;

   wire          ldinv_i1;

   wire          ldinv_i2_nxt;

   wire          ldinv_i2;

   wire          ifq_reset,

                 rnd_reset,

                 ifq_reset_l;

   wire          clk;

//----------------------------------------------------------------------

// Code start here 

//----------------------------------------------------------------------

   assign        clk = rclk;

   // reset buffer

   dffrl_async rstff(.din (grst_l),

                     .q   (ifq_reset_l),

                     .clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so(),

                     .rst_l (arst_l));

   assign       ifq_reset = ~ifq_reset_l;

//---------

// MIL fsm

//---------   

   sparc_ifu_milfsm mil0(

                               .ifc_fsm_can_thisthr      (fcl_ifq_canthr[0]),

                         //     .ifc_fsm_orphan_thisthr (orphan_thr_d1[0]),

                               .ifc_fsm_fill_thisthr_i2  (fill_retn_thr_i2[0]),

                               .ifc_fsm_wr_complete_f    (wr_complete_f[0]),

                         .ifqadv_i2  (ifc_inv_ifqadv_i2),

                         .ifd_ifc_4bpkt_i2         (ifd_ifc_4bpkt_i2),

                               .fcl_ifq_thr_s1           (fcl_ifq_thr_s1),

                               .ifc_fsm_imiss_thisthr_s  (icmiss_thr_s[0]),

                               .ifc_fsm_milhit_s         (any_milhit_qual_s),

                               .ifc_fsm_hiton_thismil_s  (milhit_to_thr_s[0]),

                               .ifc_fsm_pcxaccept_thisthr(pcx_accept_d[0]),

                         .ifc_fsm_miladdr4         (ifd_ifc_miladdr4_i2[0]),

                               .clk                      (clk),

                         .se                       (se),

                         .si                       (si),

                               .reset                    (ifq_reset),

                         .so                       (),

                               .ifc_fsm_err_thisthr      (errthr_d1[0]),

                               // outputs        

                         .fsm_ifc_errreq           (err_req[0]),

                               .fsm_ifc_wrt_tir          (wrt_tir[0]),

                               .fsm_ifc_comp_valid       (comp_valid_s[0]),

                               .fsm_ifc_mil_valid        (mil_valid_s[0]),

                               .fsm_ifc_mil_cancel       (mil_cancel[0]),

                         .fsm_ifc_milstate         (mil0_state[3:0]),

                               .fsm_ifc_thr_ready        (mil_thr_ready[0]),

                               .fsm_ifc_pred_rdy         (pred_rdy_i2[0]),

                               .fsm_ifc_pcxreq           (pcxreq_s[0]),

                               .fsm_ifc_addrbit4_i2      (fill_addr4_i2[0]),

                               .fsm_ifc_milchld          (milchld0[2:0]));

   sparc_ifu_milfsm mil1(

                         .ifc_fsm_can_thisthr      (fcl_ifq_canthr[1]),

                         //        .ifc_fsm_orphan_thisthr   (orphan_thr_d1[1]),     

                               .ifc_fsm_fill_thisthr_i2  (fill_retn_thr_i2[1]),

                               .ifc_fsm_wr_complete_f    (wr_complete_f[1]),

                         .ifqadv_i2  (ifc_inv_ifqadv_i2),

                         .ifd_ifc_4bpkt_i2         (ifd_ifc_4bpkt_i2),

                               .fcl_ifq_thr_s1           (fcl_ifq_thr_s1),

                               .ifc_fsm_milhit_s         (any_milhit_qual_s),

                               .ifc_fsm_hiton_thismil_s (milhit_to_thr_s[1]),

                               .ifc_fsm_imiss_thisthr_s   (icmiss_thr_s[1]),

                               .ifc_fsm_pcxaccept_thisthr   (pcx_accept_d[1]),

                         //        .ifc_fsm_reqq_empty       (reqq_empty),         

                         .ifc_fsm_miladdr4         (ifd_ifc_miladdr4_i2[1]),

                               .clk                      (clk),

                         .se                       (se),

                         .si                       (si),

                               .reset                    (ifq_reset),

                               .ifc_fsm_err_thisthr      (errthr_d1[1]),

                               // outputs        

                         .fsm_ifc_errreq           (err_req[1]),

                               .fsm_ifc_wrt_tir          (wrt_tir[1]),

                         .so                       (),

                         //        .fsm_ifc_cm_pending       (can_miss_pending[1]),

                         //        .fsm_ifc_delay_mil        (delay_mil[1]),

                               .fsm_ifc_comp_valid       (comp_valid_s[1]),

                               .fsm_ifc_mil_valid        (mil_valid_s[1]),

                               .fsm_ifc_mil_cancel       (mil_cancel[1]),

                         .fsm_ifc_milstate         (mil1_state[3:0]),

                               .fsm_ifc_pcxreq           (pcxreq_s[1]),

                               .fsm_ifc_thr_ready        (mil_thr_ready[1]),

                               .fsm_ifc_pred_rdy         (pred_rdy_i2[1]),

                               .fsm_ifc_addrbit4_i2      (fill_addr4_i2[1]),

                               .fsm_ifc_milchld          (milchld1[2:0]));

   sparc_ifu_milfsm mil2(

                         .ifc_fsm_can_thisthr      (fcl_ifq_canthr[2]),

                         //        .ifc_fsm_orphan_thisthr   (orphan_thr_d1[2]),     

                               .ifc_fsm_fill_thisthr_i2  (fill_retn_thr_i2[2]),

                               .ifc_fsm_wr_complete_f    (wr_complete_f[2]),

                         .ifqadv_i2  (ifc_inv_ifqadv_i2),

                         .ifd_ifc_4bpkt_i2         (ifd_ifc_4bpkt_i2),

                               .fcl_ifq_thr_s1           (fcl_ifq_thr_s1),

                               .ifc_fsm_milhit_s         (any_milhit_qual_s),

                               .ifc_fsm_hiton_thismil_s (milhit_to_thr_s[2]),

                               .ifc_fsm_imiss_thisthr_s  (icmiss_thr_s[2]),

                               .ifc_fsm_pcxaccept_thisthr(pcx_accept_d[2]),

                         //        .ifc_fsm_reqq_empty       (reqq_empty),         

                         .ifc_fsm_miladdr4         (ifd_ifc_miladdr4_i2[2]),

                               .clk                      (clk),

                         .se                       (se),

                         .si                       (si),

                               .reset                    (ifq_reset),

                               .ifc_fsm_err_thisthr      (errthr_d1[2]),

                               // outputs        

                         .fsm_ifc_errreq           (err_req[2]),

                         .so                       (),

                         //        .fsm_ifc_cm_pending       (can_miss_pending[2]),

                         //        .fsm_ifc_delay_mil        (delay_mil[2]),

                               .fsm_ifc_wrt_tir          (wrt_tir[2]),

                               .fsm_ifc_comp_valid       (comp_valid_s[2]),

                               .fsm_ifc_mil_valid        (mil_valid_s[2]),

                               .fsm_ifc_mil_cancel       (mil_cancel[2]),

                         .fsm_ifc_milstate         (mil2_state[3:0]),

                               .fsm_ifc_pcxreq           (pcxreq_s[2]),

                               .fsm_ifc_thr_ready        (mil_thr_ready[2]),

                               .fsm_ifc_pred_rdy         (pred_rdy_i2[2]),

                               .fsm_ifc_addrbit4_i2      (fill_addr4_i2[2]),

                               .fsm_ifc_milchld          (milchld2[2:0]));

   sparc_ifu_milfsm mil3(

                         .ifc_fsm_can_thisthr      (fcl_ifq_canthr[3]),

                         //        .ifc_fsm_orphan_thisthr   (orphan_thr_d1[3]),     

                               .ifc_fsm_fill_thisthr_i2  (fill_retn_thr_i2[3]),

                               .ifc_fsm_wr_complete_f    (wr_complete_f[3]),

                         .ifqadv_i2  (ifc_inv_ifqadv_i2),

                         .ifd_ifc_4bpkt_i2         (ifd_ifc_4bpkt_i2),

                               .fcl_ifq_thr_s1           (fcl_ifq_thr_s1),

                               .ifc_fsm_milhit_s         (any_milhit_qual_s),

                               .ifc_fsm_hiton_thismil_s (milhit_to_thr_s[3]),

                               .ifc_fsm_imiss_thisthr_s   (icmiss_thr_s[3]),

                               .ifc_fsm_pcxaccept_thisthr(pcx_accept_d[3]),

                         //        .ifc_fsm_reqq_empty       (reqq_empty),         

                         .ifc_fsm_miladdr4         (ifd_ifc_miladdr4_i2[3]),

                               .clk                      (clk),

                         .se                       (se),

                         .si                       (si),

                               .reset                    (ifq_reset),

                               .ifc_fsm_err_thisthr      (errthr_d1[3]),

                               // outputs        

                         .fsm_ifc_errreq           (err_req[3]),

                         .so                       (),

                         //        .fsm_ifc_cm_pending       (can_miss_pending[3]),

                         //        .fsm_ifc_delay_mil        (delay_mil[3]),