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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [sparc_ifu_lfsr5.v] - Blame information for rev 113

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// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T1 Processor File: sparc_ifu_lfsr5.v
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================
`ifdef SIMPLY_RISC_TWEAKS
`define SIMPLY_RISC_SCANIN .si(0)
`else
`define SIMPLY_RISC_SCANIN .si()
`endif
////////////////////////////////////////////////////////////////////////
/*
//  Module Name: sparc_ifu_lfsr5
//  Description:
//  The IFQ is the icache input queue.  This communicates between the
//  IFU and the outside world.  It handles icache misses and
//  invalidate requests from the crossbar.
*/
////////////////////////////////////////////////////////////////////////
 
module sparc_ifu_lfsr5 (/*AUTOARG*/
   // Outputs
   out,
   // Inputs
   advance, clk, se, si, so, reset
   );
 
   input        advance;
 
   input        clk, se, si, so, reset;
 
   output [1:0] out;
 
   reg [4:0]    q_next;
   wire [4:0]   q;
 
 
/*
   always @ (posedge clk)
     begin
        out = $random;
     end // always @ posedge
 */
 
//   always @ (posedge clk)
//     begin
//      q[4:0] <= q_next[4:0];
//     end
 
   always @ (/*AUTOSENSE*/advance or q or reset)
     begin
              if (reset)
                q_next = 5'b11111;
              else if (advance)
                begin
                   // lfsr -- stable at 000000, period of 63
                   q_next[1] = q[0];
                   q_next[2] = q[1];
                   q_next[3] = q[2];
                   q_next[4] = q[3];
                   q_next[0] = q[1] ^ q[4];
                end
              else
                q_next = q;
     end // always @ (...
 
   assign out = {q[0], q[2]};
 
   dff_s #(5) lfsr_reg(.din  (q_next),
                     .q    (q),
                     .clk  (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
 
endmodule // sparc_ifu_lfsr5
 
 
 
 

Line No.	Rev	Author	Line
1	95	fafa1971	`// ========== Copyright Header Begin ==========================================`
2			`//`
3			`// OpenSPARC T1 Processor File: sparc_ifu_lfsr5.v`
4			`// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.`
5			`// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.`
6			`//`
7			`// The above named program is free software; you can redistribute it and/or`
8			`// modify it under the terms of the GNU General Public`
9			`// License version 2 as published by the Free Software Foundation.`
10			`//`
11			`// The above named program is distributed in the hope that it will be`
12			`// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
14			`// General Public License for more details.`
15			`//`
16			`// You should have received a copy of the GNU General Public`
17			`// License along with this work; if not, write to the Free Software`
18			`// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.`
19			`//`
20			`// ========== Copyright Header End ============================================`
21	113	albert.wat	`ifdef SIMPLY_RISC_TWEAKS
22			`define SIMPLY_RISC_SCANIN .si(0)
23			`else
24			`define SIMPLY_RISC_SCANIN .si()
25			`endif
26	95	fafa1971	`////////////////////////////////////////////////////////////////////////`
27			`/*`
28			`// Module Name: sparc_ifu_lfsr5`
29			`// Description:`
30			`// The IFQ is the icache input queue. This communicates between the`
31			`// IFU and the outside world. It handles icache misses and`
32			`// invalidate requests from the crossbar.`
33			`*/`
34			`////////////////////////////////////////////////////////////////////////`
35
36			`module sparc_ifu_lfsr5 (/AUTOARG/`
37			`// Outputs`
38			`out,`
39			`// Inputs`
40			`advance, clk, se, si, so, reset`
41			`);`
42
43			`input advance;`
44
45			`input clk, se, si, so, reset;`
46
47			`output [1:0] out;`
48
49			`reg [4:0] q_next;`
50			`wire [4:0] q;`
51
52
53			`/*`
54			`always @ (posedge clk)`
55			`begin`
56			`out = $random;`
57			`end // always @ posedge`
58			`*/`
59
60			`// always @ (posedge clk)`
61			`// begin`
62			`// q[4:0] <= q_next[4:0];`
63			`// end`
64
65			`always @ (/AUTOSENSE/advance or q or reset)`
66			`begin`
67			`if (reset)`
68			`q_next = 5'b11111;`
69			`else if (advance)`
70			`begin`
71			`// lfsr -- stable at 000000, period of 63`
72			`q_next[1] = q[0];`
73			`q_next[2] = q[1];`
74			`q_next[3] = q[2];`
75			`q_next[4] = q[3];`
76			`q_next[0] = q[1] ^ q[4];`
77			`end`
78			`else`
79			`q_next = q;`
80			`end // always @ (...`
81
82			`assign out = {q[0], q[2]};`
83
84	113	albert.wat	`dff_s #(5) lfsr_reg(.din (q_next),`
85	95	fafa1971	`.q (q),`
86	113	albert.wat	.clk (clk), .se(se), `SIMPLY_RISC_SCANIN, .so());
87	95	fafa1971
88			`endmodule // sparc_ifu_lfsr5`
89
90
91
92

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[/] [s1_core/] [trunk/] [hdl/] [rtl/] [sparc_core/] [sparc_ifu_lfsr5.v] - Blame information for rev 113