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fafa1971 |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: sparc_mul_top.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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113 |
albert.wat |
`ifdef SIMPLY_RISC_TWEAKS
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`define SIMPLY_RISC_SCANIN .si(0)
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`else
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`define SIMPLY_RISC_SCANIN .si()
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`endif
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95 |
fafa1971 |
module sparc_mul_top(/*AUTOARG*/
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// Outputs
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mul_exu_ack, mul_spu_ack, mul_spu_shf_ack, mul_data_out, so,
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// Inputs
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rclk, grst_l, arst_l, exu_mul_input_vld, exu_mul_rs1_data, exu_mul_rs2_data,
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spu_mul_req_vld, spu_mul_acc, spu_mul_areg_shf, spu_mul_areg_rst,
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spu_mul_op1_data, spu_mul_op2_data, spu_mul_mulres_lshft, si, se
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);
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input rclk;
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input grst_l; // system reset
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input arst_l; // async reset
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input si; // scan in
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input se; // scan enablen
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input exu_mul_input_vld; // EXU multipler op request
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input [63:0] exu_mul_rs1_data; // EXU multipler Op1
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input [63:0] exu_mul_rs2_data; // EXU multipler Op2
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input spu_mul_req_vld; // SPU multipler op request
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input spu_mul_acc; // MAC Op: ACCUM += op1 * op2 if spu_mul_acc=1
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// Bypass Op: Out = ACCUM * op1 if spu_mul_acc=0
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input spu_mul_areg_shf; // Shift >> 64 ACCUM register
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input spu_mul_areg_rst; // Reset of ACCUM register (136-bit)
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input [63:0] spu_mul_op1_data; // SPU multiplier Op1
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input [63:0] spu_mul_op2_data; // SPU multiplier Op2
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input spu_mul_mulres_lshft;
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output so; // scan_out
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output mul_exu_ack; // ack signal for EXU mul operation
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output mul_spu_ack; // ack signal for SPU MAC and Bypass mul operation
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output mul_spu_shf_ack; // acl signal for ACCUM >> 64 operation
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output [63:0] mul_data_out; // Shared output data for both EXU and SPU
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wire acc_imm, acc_actc2, acc_actc3, acc_actc5, acc_reg_enb;
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wire acc_reg_rst, acc_reg_shf;
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wire byp_sel, byp_imm, spick, x2;
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wire c0_act;
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wire rst_l;
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wire clk;
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assign clk = rclk ;
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dffrl_async rstff (
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.din (grst_l),
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.clk (clk),
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.rst_l (arst_l),
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.q (rst_l),
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.se (se),
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113 |
albert.wat |
`SIMPLY_RISC_SCANIN,
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95 |
fafa1971 |
.so ());
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sparc_mul_cntl control (
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.ecl_mul_req_vld (exu_mul_input_vld),
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.spu_mul_req_vld (spu_mul_req_vld),
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.spu_mul_acc (spu_mul_acc),
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.spu_mul_areg_shf (spu_mul_areg_shf),
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.spu_mul_areg_rst (spu_mul_areg_rst),
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.spu_mul_mulres_lshft (spu_mul_mulres_lshft),
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.c0_act (c0_act),
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.spick (spick),
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.byp_sel (byp_sel),
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.byp_imm (byp_imm),
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.acc_imm (acc_imm),
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.acc_actc2 (acc_actc2),
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.acc_actc3 (acc_actc3),
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.acc_actc5 (acc_actc5),
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.acc_reg_enb (acc_reg_enb),
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.acc_reg_rst (acc_reg_rst),
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.acc_reg_shf (acc_reg_shf),
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.x2 (x2),
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.mul_ecl_ack (mul_exu_ack),
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.mul_spu_ack (mul_spu_ack),
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.mul_spu_shf_ack (mul_spu_shf_ack),
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.rst_l (rst_l),
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.rclk (clk));
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sparc_mul_dp dpath (
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.ecl_mul_rs1_data (exu_mul_rs1_data),
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.ecl_mul_rs2_data (exu_mul_rs2_data),
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.spu_mul_op1_data (spu_mul_op1_data),
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.spu_mul_op2_data (spu_mul_op2_data),
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.valid (c0_act),
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.spick (spick),
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.byp_sel (byp_sel),
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.byp_imm (byp_imm),
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.acc_imm (acc_imm),
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.acc_actc2 (acc_actc2),
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.acc_actc3 (acc_actc3),
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.acc_actc5 (acc_actc5),
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.acc_reg_enb (acc_reg_enb),
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.acc_reg_rst (acc_reg_rst),
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.acc_reg_shf (acc_reg_shf),
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.x2 (x2),
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.mul_data_out (mul_data_out),
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.rst_l (rst_l),
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113 |
albert.wat |
`SIMPLY_RISC_SCANIN,
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95 |
fafa1971 |
.so (),
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.se (se),
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.rclk (clk));
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endmodule // sparc_mul_top
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