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1 95 fafa1971 
// ========== Copyright Header Begin ==========================================
2 
//
3 
// OpenSPARC T1 Processor File: swrvr_clib.v
4 
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
5 
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6 
//
7 
// The above named program is free software; you can redistribute it and/or
8 
// modify it under the terms of the GNU General Public
9 
// License version 2 as published by the Free Software Foundation.
10 
//
11 
// The above named program is distributed in the hope that it will be
12 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 
// General Public License for more details.
15 
//
16 
// You should have received a copy of the GNU General Public
17 
// License along with this work; if not, write to the Free Software
18 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19 
//
20 
// ========== Copyright Header End ============================================
21 
///////////////////////////////////////////////////////////////////////
22 
/*
23 
//
24 
//  Module Name: swrvr_clib.v
25 
//      Description: Design control behavioural library
26 
*/
27 
 
28 113 albert.wat 
`ifdef FPGA_SYN
29 
`define NO_SCAN
30 
`endif
31 95 fafa1971 
 
32 
// POSITVE-EDGE TRIGGERED FLOP with SCAN
33 113 albert.wat 
module dff_s (din, clk, q, se, si, so);
34 95 fafa1971 
// synopsys template
35 
 
36 
parameter SIZE = 1;
37 
 
38 
input   [SIZE-1:0]       din ;   // data in
39 
input                   clk ;   // clk or scan clk
40 
 
41 
output  [SIZE-1:0]       q ;     // output
42 
 
43 
input                   se ;    // scan-enable
44 
input   [SIZE-1:0]       si ;    // scan-input
45 
output  [SIZE-1:0]       so ;    // scan-output
46 
 
47 
reg     [SIZE-1:0]       q ;
48 
 
49 113 albert.wat 
`ifdef NO_SCAN
50 95 fafa1971 
always @ (posedge clk)
51 
  q[SIZE-1:0]  <= din[SIZE-1:0] ;
52 113 albert.wat 
`else
53 95 fafa1971 
 
54 113 albert.wat 
always @ (posedge clk)
55 95 fafa1971 
 
56 113 albert.wat 
        q[SIZE-1:0]  <= (se) ? si[SIZE-1:0]  : din[SIZE-1:0] ;
57 95 fafa1971 
 
58 113 albert.wat 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
59 95 fafa1971 
 
60 113 albert.wat 
`endif
61 95 fafa1971 
 
62 113 albert.wat 
endmodule // dff_s
63 95 fafa1971 
 
64 113 albert.wat 
`ifndef SIMPLY_RISC_TWEAKS
65 95 fafa1971 
// POSITVE-EDGE TRIGGERED FLOP with SCAN for Shadow-scan
66 
module dff_sscan (din, clk, q, se, si, so);
67 
// synopsys template
68 
 
69 
parameter SIZE = 1;
70 
 
71 
input   [SIZE-1:0]       din ;   // data in
72 
input                   clk ;   // clk or scan clk
73 
 
74 
output  [SIZE-1:0]       q ;     // output
75 
 
76 
input                   se ;    // scan-enable
77 
input   [SIZE-1:0]       si ;    // scan-input
78 
output  [SIZE-1:0]       so ;    // scan-output
79 
 
80 
reg     [SIZE-1:0]       q ;
81 
 
82 113 albert.wat 
`ifdef CONNECT_SHADOW_SCAN
83 95 fafa1971 
 
84 113 albert.wat 
always @ (posedge clk)
85 95 fafa1971 
 
86 113 albert.wat 
        q[SIZE-1:0]  <= (se) ? si[SIZE-1:0]  : din[SIZE-1:0] ;
87 95 fafa1971 
 
88 113 albert.wat 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
89 95 fafa1971 
 
90 113 albert.wat 
`else
91 95 fafa1971 
always @ (posedge clk)
92 
  q[SIZE-1:0]  <= din[SIZE-1:0] ;
93 
 
94 
assign so={SIZE{1'b0}};
95 113 albert.wat 
`endif
96 95 fafa1971 
 
97 113 albert.wat 
endmodule // dff_sscan
98 
`endif
99 95 fafa1971 
 
100 
// POSITVE-EDGE TRIGGERED FLOP without SCAN
101 
module dff_ns (din, clk, q);
102 
// synopsys template
103 
 
104 
parameter SIZE = 1;
105 
 
106 
input   [SIZE-1:0]       din ;   // data in
107 
input                   clk ;   // clk
108 
 
109 
output  [SIZE-1:0]       q ;     // output
110 
 
111 
reg     [SIZE-1:0]       q ;
112 
 
113 
always @ (posedge clk)
114 
 
115 
        q[SIZE-1:0]  <= din[SIZE-1:0] ;
116 
 
117 
endmodule // dff_ns
118 
 
119 
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, RESET
120 113 albert.wat 
module dffr_s (din, clk, rst, q, se, si, so);
121 95 fafa1971 
// synopsys template
122 
 
123 
parameter SIZE = 1;
124 
 
125 
input   [SIZE-1:0]       din ;   // data in
126 
input                   clk ;   // clk or scan clk
127 
input                   rst ;   // reset
128 
 
129 
output  [SIZE-1:0]       q ;     // output
130 
 
131 
input                   se ;    // scan-enable
132 
input   [SIZE-1:0]       si ;    // scan-input
133 
output  [SIZE-1:0]       so ;    // scan-output
134 
 
135 
reg     [SIZE-1:0]       q ;
136 
 
137 113 albert.wat 
`ifdef NO_SCAN
138 95 fafa1971 
always @ (posedge clk)
139 
        q[SIZE-1:0]  <= ((rst) ? {SIZE{1'b0}}  : din[SIZE-1:0] );
140 113 albert.wat 
`else
141 95 fafa1971 
 
142 113 albert.wat 
// Scan-Enable dominates
143 
always @ (posedge clk)
144 95 fafa1971 
 
145 113 albert.wat 
        q[SIZE-1:0]  <= se ? si[SIZE-1:0] : ((rst) ? {SIZE{1'b0}}  : din[SIZE-1:0] );
146 95 fafa1971 
 
147 113 albert.wat 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
148 
`endif
149 95 fafa1971 
 
150 113 albert.wat 
endmodule // dffr_s
151 95 fafa1971 
 
152 113 albert.wat 
`ifndef SIMPLY_RISC_TWEAKS
153 95 fafa1971 
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, RESET_L
154 113 albert.wat 
module dffrl_s (din, clk, rst_l, q, se, si, so);
155 95 fafa1971 
// synopsys template
156 
 
157 
parameter SIZE = 1;
158 
 
159 
input   [SIZE-1:0]       din ;   // data in
160 
input                   clk ;   // clk or scan clk
161 
input                   rst_l ; // reset
162 
 
163 
output  [SIZE-1:0]       q ;     // output
164 
 
165 
input                   se ;    // scan-enable
166 
input   [SIZE-1:0]       si ;    // scan-input
167 
output  [SIZE-1:0]       so ;    // scan-output
168 
 
169 
reg     [SIZE-1:0]       q ;
170 
 
171 113 albert.wat 
`ifdef NO_SCAN
172 95 fafa1971 
always @ (posedge clk)
173 
        q[SIZE-1:0]  <= rst_l ? din[SIZE-1:0] : {SIZE{1'b0}};
174 113 albert.wat 
`else
175 95 fafa1971 
 
176 113 albert.wat 
// Reset dominates
177 
always @ (posedge clk)
178 95 fafa1971 
 
179 113 albert.wat 
        q[SIZE-1:0]  <= rst_l ? ((se) ? si[SIZE-1:0]  : din[SIZE-1:0] ) : {SIZE{1'b0}};
180 95 fafa1971 
 
181 113 albert.wat 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
182 
`endif
183 95 fafa1971 
 
184 113 albert.wat 
endmodule // dffrl_s
185 95 fafa1971 
 
186 
 
187 
// POSITIVE-EDGE TRIGGERED FLOP with RESET, without SCAN
188 
module dffr_ns (din, clk, rst, q);
189 
// synopsys template
190 
 
191 
parameter SIZE = 1;
192 
 
193 
input   [SIZE-1:0]       din ;   // data in
194 
input                   clk ;   // clk
195 
input                   rst ;   // reset
196 
 
197 
output  [SIZE-1:0]       q ;     // output
198 
 
199 
reg     [SIZE-1:0]       q ;
200 
 
201 
// synopsys sync_set_reset "rst"
202 
always @ (posedge clk)
203 
  q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : din[SIZE-1:0];
204 
 
205 
endmodule // dffr_ns
206 113 albert.wat 
`endif
207 95 fafa1971 
 
208 
// POSITIVE-EDGE TRIGGERED FLOP with RESET_L, without SCAN
209 
module dffrl_ns (din, clk, rst_l, q);
210 
// synopsys template
211 
 
212 
parameter SIZE = 1;
213 
 
214 
input   [SIZE-1:0]       din ;   // data in
215 
input                   clk ;   // clk
216 
input                   rst_l ; // reset
217 
 
218 
output  [SIZE-1:0]       q ;     // output
219 
 
220 
reg     [SIZE-1:0]       q ;
221 
 
222 
// synopsys sync_set_reset "rst_l"
223 
always @ (posedge clk)
224 
  q[SIZE-1:0] <= rst_l ? din[SIZE-1:0] : {SIZE{1'b0}};
225 
 
226 
endmodule // dffrl_ns
227 
 
228 
// POSITIVE-EDGE TRIGGERED FLOP with SCAN and FUNCTIONAL ENABLE
229 113 albert.wat 
module dffe_s (din, en, clk, q, se, si, so);
230 95 fafa1971 
// synopsys template
231 
 
232 
parameter SIZE = 1;
233 
 
234 
input   [SIZE-1:0]       din ;   // data in
235 
input                   en ;    // functional enable
236 
input                   clk ;   // clk or scan clk
237 
 
238 
output  [SIZE-1:0]       q ;     // output
239 
 
240 
input                   se ;    // scan-enable
241 
input   [SIZE-1:0]       si ;    // scan-input
242 
output  [SIZE-1:0]       so ;    // scan-output
243 
 
244 
reg     [SIZE-1:0]       q ;
245 
 
246 
// Enable Interpretation. Ultimate interpretation depends on design
247 
//
248 
// en   se      out
249 
//------------------
250 
// x    1       sin ; scan dominates
251 
// 1    0        din
252 
// 0    0        q
253 
//
254 
 
255 113 albert.wat 
`ifdef NO_SCAN
256 95 fafa1971 
always @ (posedge clk)
257 
        q[SIZE-1:0]  <= ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) ;
258 113 albert.wat 
`else
259 95 fafa1971 
 
260 113 albert.wat 
always @ (posedge clk)
261 95 fafa1971 
 
262 113 albert.wat 
        q[SIZE-1:0]  <= (se) ? si[SIZE-1:0]  : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) ;
263 95 fafa1971 
 
264 113 albert.wat 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
265 
`endif
266 95 fafa1971 
 
267 113 albert.wat 
endmodule // dffe_s
268 95 fafa1971 
 
269 113 albert.wat 
`ifndef SIMPLY_RISC_TWEAKS
270 95 fafa1971 
// POSITIVE-EDGE TRIGGERED FLOP with enable, without SCAN
271 
module dffe_ns (din, en, clk, q);
272 
// synopsys template
273 
 
274 
parameter SIZE = 1;
275 
 
276 
input   [SIZE-1:0]       din ;   // data in
277 
input                   en ;    // functional enable
278 
input                   clk ;   // clk
279 
 
280 
output  [SIZE-1:0]       q ;     // output
281 
 
282 
reg     [SIZE-1:0]       q ;
283 
 
284 
always @ (posedge clk)
285 
  q[SIZE-1:0] <= en ? din[SIZE-1:0] : q[SIZE-1:0];
286 
 
287 
endmodule // dffe_ns
288 113 albert.wat 
`endif
289 95 fafa1971 
 
290 
// POSITIVE-EDGE TRIGGERED FLOP with RESET, FUNCTIONAL ENABLE, SCAN.
291 113 albert.wat 
module dffre_s (din, rst, en, clk, q, se, si, so);
292 95 fafa1971 
// synopsys template
293 
 
294 
parameter SIZE = 1;
295 
 
296 
input   [SIZE-1:0]       din ;   // data in
297 
input                   en ;    // functional enable
298 
input                   rst ;   // reset
299 
input                   clk ;   // clk or scan clk
300 
 
301 
output  [SIZE-1:0]       q ;     // output
302 
 
303 
input                   se ;    // scan-enable
304 
input   [SIZE-1:0]       si ;    // scan-input
305 
output  [SIZE-1:0]       so ;    // scan-output
306 
 
307 
reg     [SIZE-1:0]       q ;
308 
 
309 
// Enable Interpretation. Ultimate interpretation depends on design
310 
//
311 
// rst  en      se      out
312 
//------------------
313 
// 1    x       x       0   ; reset dominates
314 
// 0    x       1       sin ; scan dominates
315 
// 0    1       0        din
316 
// 0    0       0        q
317 
//
318 
 
319 113 albert.wat 
`ifdef NO_SCAN
320 95 fafa1971 
always @ (posedge clk)
321 
        q[SIZE-1:0]  <= (rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
322 113 albert.wat 
`else
323 95 fafa1971 
 
324 113 albert.wat 
always @ (posedge clk)
325 95 fafa1971 
 
326 113 albert.wat 
//      q[SIZE-1:0]  <= rst ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0]  : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
327 
        q[SIZE-1:0]  <= se ? si[SIZE-1:0]  : (rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
328 95 fafa1971 
 
329 113 albert.wat 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
330 95 fafa1971 
 
331 113 albert.wat 
`endif
332 95 fafa1971 
 
333 113 albert.wat 
endmodule // dffre_s
334 95 fafa1971 
 
335 
// POSITIVE-EDGE TRIGGERED FLOP with RESET_L, FUNCTIONAL ENABLE, SCAN.
336 113 albert.wat 
module dffrle_s (din, rst_l, en, clk, q, se, si, so);
337 95 fafa1971 
// synopsys template
338 
 
339 
parameter SIZE = 1;
340 
 
341 
input   [SIZE-1:0]       din ;   // data in
342 
input                   en ;    // functional enable
343 
input                   rst_l ; // reset
344 
input                   clk ;   // clk or scan clk
345 
 
346 
output  [SIZE-1:0]       q ;     // output
347 
 
348 
input                   se ;    // scan-enable
349 
input   [SIZE-1:0]       si ;    // scan-input
350 
output  [SIZE-1:0]       so ;    // scan-output
351 
 
352 
reg     [SIZE-1:0]       q ;
353 
 
354 
// Enable Interpretation. Ultimate interpretation depends on design
355 
//
356 
// rst  en      se      out
357 
//------------------
358 
// 0    x       x       0   ; reset dominates
359 
// 1    x       1       sin ; scan dominates
360 
// 1    1       0        din
361 
// 1    0       0        q
362 
//
363 
 
364 113 albert.wat 
`ifdef NO_SCAN
365 95 fafa1971 
always @ (posedge clk)
366 
         q[SIZE-1:0]  <= (rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}}) ;
367 113 albert.wat 
`else
368 95 fafa1971 
 
369 113 albert.wat 
always @ (posedge clk)
370 95 fafa1971 
 
371 113 albert.wat 
//      q[SIZE-1:0]  <= rst_l ? ((se) ? si[SIZE-1:0]  : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) : {SIZE{1'b0}} ;
372 
        q[SIZE-1:0]  <= se ? si[SIZE-1:0]  : (rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}}) ;
373 95 fafa1971 
 
374 113 albert.wat 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
375 
`endif
376 95 fafa1971 
 
377 113 albert.wat 
endmodule // dffrle_s
378 95 fafa1971 
 
379 113 albert.wat 
`ifndef SIMPLY_RISC_TWEAKS
380 95 fafa1971 
// POSITIVE-EDGE TRIGGERED FLOP with RESET, ENABLE, without SCAN.
381 
module dffre_ns (din, rst, en, clk, q);
382 
// synopsys template
383 
 
384 
parameter SIZE = 1;
385 
 
386 
input   [SIZE-1:0]       din ;   // data in
387 
input                   en ;    // functional enable
388 
input                   rst ;   // reset
389 
input                   clk ;   // clk
390 
 
391 
output  [SIZE-1:0]       q ;     // output
392 
 
393 
reg     [SIZE-1:0]       q ;
394 
 
395 
// Enable Interpretation. Ultimate interpretation depends on design
396 
//
397 
// rst  en      out
398 
//------------------
399 
// 1    x       0   ; reset dominates
400 
// 0    1       din
401 
// 0    0       q
402 
//
403 
 
404 
// synopsys sync_set_reset "rst"
405 
always @ (posedge clk)
406 
  q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]);
407 
 
408 
endmodule // dffre_ns
409 113 albert.wat 
`endif
410 95 fafa1971 
 
411 
// POSITIVE-EDGE TRIGGERED FLOP with RESET_L, ENABLE, without SCAN.
412 
module dffrle_ns (din, rst_l, en, clk, q);
413 
// synopsys template
414 
 
415 
parameter SIZE = 1;
416 
 
417 
input   [SIZE-1:0]       din ;   // data in
418 
input                   en ;    // functional enable
419 
input                   rst_l ; // reset
420 
input                   clk ;   // clk
421 
 
422 
output  [SIZE-1:0]       q ;     // output
423 
 
424 
reg     [SIZE-1:0]       q ;
425 
 
426 
// Enable Interpretation. Ultimate interpretation depends on design
427 
//
428 
// rst  en      out
429 
//------------------
430 
// 0    x       0   ; reset dominates
431 
// 1    1       din
432 
// 1    0       q
433 
//
434 
 
435 
// synopsys sync_set_reset "rst_l"
436 
always @ (posedge clk)
437 
  q[SIZE-1:0] <= rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}} ;
438 
 
439 
endmodule // dffrle_ns
440 
 
441 113 albert.wat 
`ifndef SIMPLY_RISC_TWEAKS
442 95 fafa1971 
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, and ASYNC RESET
443 
module dffr_async (din, clk, rst, q, se, si, so);
444 
// synopsys template
445 
 
446 
parameter SIZE = 1;
447 
 
448 
input   [SIZE-1:0]      din ;   // data in
449 
input                   clk ;   // clk or scan clk
450 
input                   rst ;   // reset
451 
 
452 
output  [SIZE-1:0]      q ;     // output
453 
 
454 
input                   se ;    // scan-enable
455 
input   [SIZE-1:0]      si ;    // scan-input
456 
output  [SIZE-1:0]      so ;    // scan-output
457 
 
458 
reg     [SIZE-1:0]      q ;
459 
 
460 113 albert.wat 
`ifdef NO_SCAN
461 95 fafa1971 
always @ (posedge clk or posedge rst)
462 
        q[SIZE-1:0]  <= rst ? {SIZE{1'b0}} : din[SIZE-1:0];
463 113 albert.wat 
`else
464 95 fafa1971 
 
465 113 albert.wat 
// Reset dominates
466 
always @ (posedge clk or posedge rst)
467 
  q[SIZE-1:0]  <= rst ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0]  : din[SIZE-1:0] );
468 95 fafa1971 
 
469 113 albert.wat 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
470 95 fafa1971 
 
471 113 albert.wat 
`endif
472 95 fafa1971 
 
473 
endmodule // dffr_async
474 113 albert.wat 
`endif
475 95 fafa1971 
 
476 
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, and ASYNC RESET_L
477 
module dffrl_async (din, clk, rst_l, q, se, si, so);
478 
// synopsys template
479 
 
480 
parameter SIZE = 1;
481 
 
482 
input   [SIZE-1:0]      din ;   // data in
483 
input                   clk ;   // clk or scan clk
484 
input                   rst_l ;   // reset
485 
 
486 
output  [SIZE-1:0]      q ;     // output
487 
 
488 
input                   se ;    // scan-enable
489 
input   [SIZE-1:0]      si ;    // scan-input
490 
output  [SIZE-1:0]      so ;    // scan-output
491 
 
492 
reg     [SIZE-1:0]      q ;
493 
 
494 113 albert.wat 
`ifdef NO_SCAN
495 95 fafa1971 
always @ (posedge clk or negedge rst_l)
496 
        q[SIZE-1:0]  <= (!rst_l) ? {SIZE{1'b0}} : din[SIZE-1:0];
497 113 albert.wat 
`else
498 95 fafa1971 
 
499 113 albert.wat 
// Reset dominates
500 
always @ (posedge clk or negedge rst_l)
501 
  q[SIZE-1:0]  <= (!rst_l) ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0]  : din[SIZE-1:0] );
502 95 fafa1971 
 
503 113 albert.wat 
assign so[SIZE-1:0] = q[SIZE-1:0] ;
504 95 fafa1971 
 
505 113 albert.wat 
`endif
506 95 fafa1971 
 
507 
endmodule // dffrl_async
508 
 
509 
// POSITIVE-EDGE TRIGGERED FLOP with ASYNC RESET, without SCAN
510 
//module dffr_async_ns (din, clk, rst, q);
511 
//// synopsys template
512 
//parameter SIZE = 1;
513 
//input   [SIZE-1:0]      din ;   // data in
514 
//input                   clk ;   // clk or scan clk
515 
//input                   rst ;   // reset
516 
//output  [SIZE-1:0]      q ;     // output
517 
//reg     [SIZE-1:0]      q ;
518 
// Reset dominates
519 
//// synopsys async_set_reset "rst"
520 
//always @ (posedge clk or posedge rst)
521 
//        if(rst) q[SIZE-1:0]  <= {SIZE{1'b0}};
522 
//        else if(clk) q[SIZE-1:0]  <= din[SIZE-1:0];
523 
//endmodule // dffr_async_ns
524 
 
525 113 albert.wat 
`ifndef SIMPLY_RISC_TWEAKS
526 95 fafa1971 
// POSITIVE-EDGE TRIGGERED FLOP with ASYNC RESET_L, without SCAN
527 
module dffrl_async_ns (din, clk, rst_l, q);
528 
// synopsys template
529 
 
530 
parameter SIZE = 1;
531 
 
532 
input   [SIZE-1:0]      din ;   // data in
533 
input                   clk ;   // clk or scan clk
534 
input                   rst_l ;   // reset
535 
 
536 
output  [SIZE-1:0]      q ;     // output
537 
 
538 
// Reset dominates
539 
// synopsys async_set_reset "rst_l"
540 
 reg [SIZE-1:0] q;
541 
always @ (posedge clk or negedge rst_l)
542 
  q[SIZE-1:0] <= ~rst_l ?  {SIZE{1'b0}} : ({SIZE{rst_l}} & din[SIZE-1:0]);
543 
 
544 
//   reg  [SIZE-1:0]   qm, qs, qm_l, qs_l, qm_f, qs_f;
545 
//   wire              s_l;
546 
//   assign            s_l = 1'b1;
547 
//
548 
//   always @ (rst_l or qm)   qm_l = ~(qm & {SIZE{rst_l}});
549 
//   always @ (s_l or qs)   qs_l = ~(qs & {SIZE{s_l}});
550 
//   always @ (s_l or qm_l) qm_f = ~(qm_l & {SIZE{s_l}});
551 
//   always @ (rst_l or qs_l) qs_f = ~(qs_l & {SIZE{rst_l}});
552 
//
553 
//   always @ (clk or din or qm_f)
554 
//      qm <= clk ? qm_f : din;
555 
//
556 
//   always @ (clk or qm_l or qs_f)
557 
//      qs <= clk ? qm_l : qs_f;
558 
//
559 
//   assign q  = ~qs;
560 
 
561 
endmodule // dffrl_async_ns
562 113 albert.wat 
`endif
563 95 fafa1971 
 
564 
// 2:1 MUX WITH DECODED SELECTS
565 
module mux2ds (dout, in0, in1, sel0, sel1) ;
566 
// synopsys template
567 
 
568 
parameter SIZE = 1;
569 
 
570 
output  [SIZE-1:0]       dout;
571 
input   [SIZE-1:0]       in0;
572 
input   [SIZE-1:0]       in1;
573 
input                   sel0;
574 
input                   sel1;
575 
 
576 
// reg declaration does not imply state being maintained
577 
// across cycles. Used to construct case statement and
578 
// always updated by inputs every cycle.
579 
reg     [SIZE-1:0]       dout ;
580 
 
581 
// priority encoding takes care of mutex'ing selects.
582 113 albert.wat 
`ifdef VERPLEX
583 
   $constraint cl_1h_chk2 ($one_hot ({sel1,sel0}));
584 
`endif
585 95 fafa1971 
 
586 
wire [1:0] sel = {sel1, sel0}; // 0in one_hot
587 
 
588 
always @ (sel0 or sel1 or in0 or in1)
589 
 
590 
        case ({sel1,sel0}) // synopsys infer_mux
591 
                2'b01 : dout = in0 ;
592 
                2'b10 : dout = in1 ;
593 
                2'b11 : dout = {SIZE{1'bx}} ;
594 
                2'b00 : dout = {SIZE{1'bx}} ;
595 
                        // 2'b00 : // E.g. 4state vs. 2state modelling.
596 
                        // begin
597 
                        //      `ifdef FOUR_STATE
598 
                        //              dout = {SIZE{1'bx}};
599 
                        //      `else
600 
                        //              begin
601 
                        //              dout = {SIZE{1'b0}};
602 113 albert.wat 
                        //              $error();
603 95 fafa1971 
                        //              end
604 
                        //      `endif
605 
                        // end
606 
                default : dout = {SIZE{1'bx}};
607 
        endcase
608 
 
609 
endmodule // mux2ds
610 
 
611 
// 3:1 MUX WITH DECODED SELECTS
612 
module mux3ds (dout, in0, in1, in2, sel0, sel1, sel2) ;
613 
// synopsys template
614 
 
615 
parameter SIZE = 1;
616 
 
617 
output  [SIZE-1:0]       dout;
618 
input   [SIZE-1:0]       in0;
619 
input   [SIZE-1:0]       in1;
620 
input   [SIZE-1:0]       in2;
621 
input                   sel0;
622 
input                   sel1;
623 
input                   sel2;
624 
 
625 
// reg declaration does not imply state being maintained
626 
// across cycles. Used to construct case statement and
627 
// always updated by inputs every cycle.
628 
reg     [SIZE-1:0]       dout ;
629 
 
630 113 albert.wat 
`ifdef VERPLEX
631 
   $constraint cl_1h_chk3 ($one_hot ({sel2,sel1,sel0}));
632 
`endif
633 95 fafa1971 
 
634 
wire [2:0] sel = {sel2,sel1,sel0}; // 0in one_hot
635 
 
636 
// priority encoding takes care of mutex'ing selects.
637 
always @ (sel0 or sel1 or sel2 or in0 or in1 or in2)
638 
 
639 
        case ({sel2,sel1,sel0})
640 
                3'b001 : dout = in0 ;
641 
                3'b010 : dout = in1 ;
642 
                3'b100 : dout = in2 ;
643 
                3'b000 : dout = {SIZE{1'bx}} ;
644 
                3'b011 : dout = {SIZE{1'bx}} ;
645 
                3'b101 : dout = {SIZE{1'bx}} ;
646 
                3'b110 : dout = {SIZE{1'bx}} ;
647 
                3'b111 : dout = {SIZE{1'bx}} ;
648 
                default : dout = {SIZE{1'bx}};
649 
                        // two state vs four state modelling will be added.
650 
        endcase
651 
 
652 
endmodule // mux3ds
653 
 
654 
// 4:1 MUX WITH DECODED SELECTS
655 
module mux4ds (dout, in0, in1, in2, in3, sel0, sel1, sel2, sel3) ;
656 
// synopsys template
657 
 
658 
parameter SIZE = 1;
659 
 
660 
output  [SIZE-1:0]       dout;
661 
input   [SIZE-1:0]       in0;
662 
input   [SIZE-1:0]       in1;
663 
input   [SIZE-1:0]       in2;
664 
input   [SIZE-1:0]       in3;
665 
input                   sel0;
666 
input                   sel1;
667 
input                   sel2;
668 
input                   sel3;
669 
 
670 
// reg declaration does not imply state being maintained
671 
// across cycles. Used to construct case statement and
672 
// always updated by inputs every cycle.
673 
reg     [SIZE-1:0]       dout ;
674 
 
675 113 albert.wat 
`ifdef VERPLEX
676 
   $constraint cl_1h_chk4 ($one_hot ({sel3,sel2,sel1,sel0}));
677 
`endif
678 95 fafa1971 
 
679 
wire [3:0] sel = {sel3,sel2,sel1,sel0}; // 0in one_hot
680 
 
681 
// priority encoding takes care of mutex'ing selects.
682 
always @ (sel0 or sel1 or sel2 or sel3 or in0 or in1 or in2 or in3)
683 
 
684 
        case ({sel3,sel2,sel1,sel0})
685 
                4'b0001 : dout = in0 ;
686 
                4'b0010 : dout = in1 ;
687 
                4'b0100 : dout = in2 ;
688 
                4'b1000 : dout = in3 ;
689 
                4'b0000 : dout = {SIZE{1'bx}} ;
690 
                4'b0011 : dout = {SIZE{1'bx}} ;
691 
                4'b0101 : dout = {SIZE{1'bx}} ;
692 
                4'b0110 : dout = {SIZE{1'bx}} ;
693 
                4'b0111 : dout = {SIZE{1'bx}} ;
694 
                4'b1001 : dout = {SIZE{1'bx}} ;
695 
                4'b1010 : dout = {SIZE{1'bx}} ;
696 
                4'b1011 : dout = {SIZE{1'bx}} ;
697 
                4'b1100 : dout = {SIZE{1'bx}} ;
698 
                4'b1101 : dout = {SIZE{1'bx}} ;
699 
                4'b1110 : dout = {SIZE{1'bx}} ;
700 
                4'b1111 : dout = {SIZE{1'bx}} ;
701 
                default : dout = {SIZE{1'bx}};
702 
                        // two state vs four state modelling will be added.
703 
        endcase
704 
 
705 
endmodule // mux4ds
706 
 
707 
// SINK FOR UNLOADED INPUT PORTS
708 
module sink (in);
709 
// synopsys template
710 
 
711 
parameter SIZE = 1;
712 
 
713 
input [SIZE-1:0] in;
714 
 
715 113 albert.wat 
`ifdef FPGA_SYN
716 95 fafa1971 
   // As of version 8.2 XST does not remove this module without the
717 
   // following additional dead code
718 
 
719 
   wire    a;
720 
 
721 
   assign               a = | in;
722 
 
723 113 albert.wat 
`endif
724 95 fafa1971 
 
725 
endmodule //sink
726 
 
727 113 albert.wat 
`ifndef SIMPLY_RISC_TWEAKS
728 95 fafa1971 
// SOURCE FOR UNDRIVEN OUTPUT PORTS
729 
module source (out) ;
730 
// synopsys template
731 
 
732 
parameter SIZE = 1;
733 
 
734 
output  [SIZE-1:0] out;
735 
//
736 
// Once 4state/2state model established
737 
// then enable check.
738 
// `ifdef FOUR_STATE
739 
// leda check for x_or_z_in rhs_of assign turned off
740 
// assign  out = {SIZE{1'bx}};
741 
//`else
742 
assign  out = {SIZE{1'b0}};
743 
//`endif
744 
 
745 
endmodule //source
746 113 albert.wat 
`endif
747 95 fafa1971 
 
748 
// 2:1 MUX WITH PRIORITY ENCODED SELECTS
749 
//module mux2es (dout, in0, in1, sel0, sel1) ;
750 
//
751 
//parameter SIZE = 1;
752 
//
753 
//output        [SIZE-1:0]      dout;
754 
//input [SIZE-1:0]      in0;
755 
//input [SIZE-1:0]      in1;
756 
//input                 sel0;
757 
//input                 sel1;
758 
//
759 
//// reg declaration does not imply state being maintained
760 
//// across cycles. Used to construct case statement and
761 
//// always updated by inputs every cycle.
762 
//reg   [SIZE-1:0]      dout ;
763 
//
764 
//// must take into account lack of mutex selects.
765 
//// there is no reason for handling of x and z conditions.
766 
//// This will be dictated by design.
767 
//always @ (sel0 or sel1 or in0 or in1)
768 
//
769 
//      case ({sel1,sel0})
770 
//              2'b1x : dout = in1 ; // 10(in1),11(z)
771 
//              2'b0x : dout = in0 ; // 01(in0),00(x)
772 
//      endcase
773 
//
774 
//endmodule // mux2es
775 
 
776 
// CLK Header for gating off the clock of
777 
// a FF.
778 
// clk - output of the clk header
779 
// rclk - input clk
780 
// enb_l - Active low clock enable
781 
// tmb_l  - Active low clock enable ( in scan mode, this input is !se )
782 
 
783 113 albert.wat 
`ifndef SIMPLY_RISC_TWEAKS
784 95 fafa1971 
module clken_buf (clk, rclk, enb_l, tmb_l);
785 
output clk;
786 
input  rclk, enb_l, tmb_l;
787 
reg    clken;
788 
 
789 
  always @ (rclk or enb_l or tmb_l)
790 
    if (!rclk)  //latch opens on rclk low phase
791 
      clken = !enb_l | !tmb_l;
792 
  assign clk = clken & rclk;
793 
 
794 
endmodule
795 
 
796 
 
797 
// The following flops are maintained and used in ENET , MAC IP  ONLY
798 
// -- Mimi X61467
799 
 
800 
// POSITIVE-EDGE TRIGGERED FLOP with SET_L, without SCAN.
801 
module dffsl_ns (din, clk, set_l, q);
802 
// synopsys template
803 
parameter SIZE = 1;
804 
 
805 
input   [SIZE-1:0]      din ;   // data in
806 
input                   clk ;   // clk or scan clk
807 
input                   set_l ; // set
808 
 
809 
output  [SIZE-1:0]      q ;     // output
810 
 
811 
reg     [SIZE-1:0]      q ;
812 
 
813 
// synopsys sync_set_reset "set_l"
814 
always @ (posedge clk)
815 
  q[SIZE-1:0] <= set_l ? din[SIZE-1:0] : {SIZE{1'b1}};
816 
 
817 
endmodule // dffsl_ns
818 
 
819 113 albert.wat 
 
820 95 fafa1971 
// POSITIVE-EDGE TRIGGERED FLOP with SET_L, without SCAN.
821 
module dffsl_async_ns (din, clk, set_l, q);
822 
// synopsys template
823 
parameter SIZE = 1;
824 
 
825 
input   [SIZE-1:0]      din ;   // data in
826 
input                   clk ;   // clk or scan clk
827 
input                   set_l ; // set
828 
 
829 
output  [SIZE-1:0]      q ;     // output
830 
 
831 
reg     [SIZE-1:0]      q ;
832 
 
833 
// synopsys async_set_reset "set_l"
834 
always @ (posedge clk or negedge set_l)
835 
  q[SIZE-1:0] <= ~set_l ? {SIZE{1'b1}} : ({SIZE{~set_l}} | din[SIZE-1:0]);
836 
 
837 
endmodule // dffsl_async_ns
838 
 
839 113 albert.wat 
 
840 95 fafa1971 
// POSITIVE-EDGE TRIGGERED FLOP WITH SET_H , without SCAN.
841 
module dffr_ns_r1 (din, clk, rst, q);
842 
// synopsys template
843 
parameter SIZE = 1;
844 
 
845 
input   [SIZE-1:0]      din ;   // data in
846 
input                   clk ;   // clk or scan clk
847 
input                   rst ;   // reset
848 
 
849 
output  [SIZE-1:0]      q ;     // output
850 
 
851 
reg     [SIZE-1:0]      q ;
852 
 
853 
// Set to 1
854 
// synopsys sync_set_reset "rst"
855 
always @ (posedge clk)
856 
  q[SIZE-1:0] <= rst ? {SIZE{1'b1}} : din[SIZE-1:0];
857 
 
858 
endmodule // dffr_ns_r1
859 
 
860 113 albert.wat 
 
861 95 fafa1971 
// POSITIVE-EDGE TRIGGERED ASYNC RESET_H FLOP , without SCAN.
862 
module dffr_async_ns (din, clk, rst, q);
863 
// synopsys template
864 
 
865 
parameter SIZE = 1;
866 
 
867 
input   [SIZE-1:0]      din ;   // data in
868 
input                   clk ;   // clk or scan clk
869 
input                   rst;   // reset
870 
 
871 
output  [SIZE-1:0]      q ;     // output
872 
 
873 
reg     [SIZE-1:0]      q ;
874 
 
875 
// Reset dominates
876 
// synopsys async_set_reset "rst"
877 
always @ (posedge clk or posedge rst)
878 
  q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : din[SIZE-1:0];
879 
 
880 
endmodule // dffr_async_ns
881 
 
882 113 albert.wat 
 
883 95 fafa1971 
// POSITIVE-EDGE TRIGGERED ASYNC SET_H FLOP , without SCAN.
884 
module dffr_async_ns_r1 (din, clk, rst, q);
885 
// synopsys template
886 
 
887 
parameter SIZE = 1;
888 
 
889 
input   [SIZE-1:0]      din ;   // data in
890 
input                   clk ;   // clk or scan clk
891 
input                   rst;   // reset
892 
 
893 
output  [SIZE-1:0]      q ;     // output
894 
 
895 
reg     [SIZE-1:0]      q ;
896 
 
897 
// Reset to 1
898 
// synopsys async_set_reset "rst"
899 
always @ (posedge clk or posedge rst)
900 
  q[SIZE-1:0] <= rst ? {SIZE{1'b1}} : din[SIZE-1:0];
901 
 
902 
endmodule // dffr_async_ns_r1
903 
 
904 
 
905 
// NEGATIVE-EDGE TRIGGERED ASYNC SET_H FLOP , without SCAN.
906 
module dffr_async_ns_cl_r1 (din, clkl, rst, q);
907 
// synopsys template
908 
parameter SIZE = 1;
909 
 
910 
input   [SIZE-1:0]      din ;   // data in
911 
input                   clkl ;  // clk or scan clk
912 
input                   rst ;   // reset
913 
 
914 
output  [SIZE-1:0]      q ;     // output
915 
 
916 
reg     [SIZE-1:0]      q ;
917 
 
918 
// Set to 1
919 
// synopsys sync_set_reset "rst"
920 
always @ (negedge clkl or posedge rst)
921 
  q[SIZE-1:0] <= rst ? {SIZE{1'b1}} : din[SIZE-1:0];
922 
 
923 
endmodule // dffr_async_ns_cl_r1
924 113 albert.wat 
`endif

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