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// ========== Copyright Header Begin ==========================================

// 

// OpenSPARC T1 Processor File: tlu_hyperv.v

// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

// 

// The above named program is free software; you can redistribute it and/or

// modify it under the terms of the GNU General Public

// License version 2 as published by the Free Software Foundation.

// 

// The above named program is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

// General Public License for more details.

// 

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// ========== Copyright Header End ============================================

`ifdef SIMPLY_RISC_TWEAKS

`define SIMPLY_RISC_SCANIN .si(0)

`else

`define SIMPLY_RISC_SCANIN .si()

`endif

////////////////////////////////////////////////////////////////////////

/*

//      Description:    Block that contain most of the Hypervisor support

//                      additions

*/

////////////////////////////////////////////////////////////////////////

// Global header file includes

////////////////////////////////////////////////////////////////////////

`include        "sys.h" // system level definition file which contains the

                        // time scale definition

`include "tlu.h"

////////////////////////////////////////////////////////////////////////

// Local header file includes / local defines

////////////////////////////////////////////////////////////////////////

module  tlu_hyperv (/*AUTOARG*/

    // outputs

    tlu_htickcmp_rw_e, tlu_gl_rw_m, tlu_hpstate_din_sel0, tlu_hpstate_din_sel1,

    tlu_hpstate_din_sel2, tlu_hpstate_din_sel3, tlu_update_hpstate_l_w2,

    tlu_htickcmp_intdis, tlu_gl_lvl0, tlu_gl_lvl1, tlu_gl_lvl2, tlu_gl_lvl3,

    tlu_htstate_rw_d, tlu_wr_hintp_g, tlu_htstate_rw_g, tlu_set_hintp_sel_g,

    tlu_htba_en_l, tlu_scpd_wr_addr_g, tlu_scpd_wr_vld_g, tlu_scpd_rd_vld_m,

    tlu_scpd_rd_addr_m, tlu_hscpd_dacc_excpt_m, tlu_hyperv_rdpr_sel,

    tlu_exu_agp_swap, tlu_exu_agp, tlu_cpu_mondo_cmp, tlu_dev_mondo_cmp,

    tlu_resum_err_cmp, tlu_asi_queue_rd_vld_g, tlu_asi_queue_data_g, tlu_ld_data_vld_g,

    tlu_va_ill_g, tlu_asi_queue_rdata_g, tlu_qtail_dacc_excpt_m, tlu_asi_write_g, so,

    inc_ind_asi_wr_indr, inc_ind_asi_wr_inrr, inc_ind_asi_rd_invr, tlu_local_thrid_g,

    // inputs

    ifu_tlu_thrid_d, ifu_tlu_sraddr_d, tlu_wsr_data_w_global, tlu_tickcmp_sel,

    tlu_thrd_traps_w2, tlu_wsr_inst_nq_g, tlu_dnrtry0_inst_g, tlu_dnrtry1_inst_g,

    tlu_dnrtry2_inst_g, tlu_dnrtry3_inst_g, tlu_dnrtry_global_g, tlu_tick_ctl_din,

    tlu_pstate_priv, tlu_select_tba_w2, tlu_hpstate_priv, tlu_hpstate_enb,

    tlu_asi_state_e, ifu_lsu_alt_space_e, ifu_lsu_ld_inst_e, ifu_lsu_st_inst_e,

    lsu_tlu_early_flush_w, tlu_por_rstint_g, tlu_agp_tid_w2, // exu_lsu_ldst_va_e, 

    tlu_local_flush_w, ifu_tlu_flush_fd_w, tlu_inst_vld_m, tlu_lsu_int_ldxa_vld_w2,

    tlu_asi_data_nf_vld_w2, lsu_tlu_ldst_va_m, arst_l, grst_l, rst_tri_en,

    si, se, rclk);

//=================================================

// output

//=================================================

// mux select to tdp to access the hyper-privileged ASR registers

output tlu_htickcmp_rw_e;

output tlu_gl_rw_m;

// output tlu_gl_rw_g;

// global switch indicator - used to be in tlu_tcl

output [1:0] tlu_exu_agp;

// output [1:0] tlu_exu_agp_tid;  

output tlu_exu_agp_swap;

//

// global register outputs

output [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl0; // global register value t0 

output [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl1; // global register value t1 

output [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl2; // global register value t2 

output [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl3; // global register value t3 

// mux selects to choose source of data to store in the hpstate regs 

output [1:0] tlu_hpstate_din_sel0;

output [1:0] tlu_hpstate_din_sel1;

output [1:0] tlu_hpstate_din_sel2;

output [1:0] tlu_hpstate_din_sel3;

//

// mux selects to read out the ASR registers

// output [3:0] tlu_rdpr_mx5_sel; 

output [4:0] tlu_hyperv_rdpr_sel;

// signal indicating mx5 is used

// output       tlu_rdpr_mx5_active; 

//

// hpstate write enable

// modified for timing

// output [`TLU_THRD_NUM-1:0] tlu_update_hpstate_l_g;

output [`TLU_THRD_NUM-1:0] tlu_update_hpstate_l_w2;

//

// htick compare reg write enable 

// output [`TLU_THRD_NUM-1:0] htickcmp_intdis_en;

// htick compare interrupt disable

output tlu_htickcmp_intdis;

//  clock enable for hintp regs.

// output [`TLU_THRD_NUM-1:0] tlu_hintp_en_l_g;

// wr control for hintp regs.

output [`TLU_THRD_NUM-1:0] tlu_wr_hintp_g;

// set control for hintp regs.

// output [`TLU_THRD_NUM-1:0] tlu_set_hintp_g;

output [`TLU_THRD_NUM-1:0] tlu_set_hintp_sel_g;

//

// update enable for the htba registers 

output [`TLU_THRD_NUM-1:0] tlu_htba_en_l;

// 

// hypervisor lite indicator

// output [`TLU_THRD_NUM-1:0] tlu_hyper_lite;

// 

// hyper-privileged scratch-pad data access exception 

output tlu_hscpd_dacc_excpt_m;

//

// store instruction to alt space

output tlu_asi_write_g;

output [`TLU_THRD_NUM-1:0] inc_ind_asi_wr_indr;

output [`TLU_THRD_NUM-1:0] inc_ind_asi_wr_inrr;

output [`TLU_THRD_NUM-1:0] inc_ind_asi_rd_invr;

output [`TLU_THRD_NUM-1:0] tlu_local_thrid_g;

// read and write valids for the scratch-pad 

output tlu_scpd_rd_vld_m, tlu_scpd_wr_vld_g;

output [`SCPD_RW_ADDR_WIDTH-1:0] tlu_scpd_wr_addr_g;

output [`SCPD_RW_ADDR_WIDTH-1:0] tlu_scpd_rd_addr_m;

//

// decode of the htstate register write/read

output tlu_htstate_rw_d;

output tlu_htstate_rw_g;

// 

// select for rdpr read in tlu_tdp

// output tlu_htba_rsr_sel; 

// 

// 

output [`TLU_THRD_NUM-1:0] tlu_cpu_mondo_cmp;

output [`TLU_THRD_NUM-1:0] tlu_dev_mondo_cmp;

output [`TLU_THRD_NUM-1:0] tlu_resum_err_cmp;

output tlu_qtail_dacc_excpt_m;

//

// asi queue rdata output

output [`TLU_ASI_QUE_WIDTH-1:0] tlu_asi_queue_rdata_g;

output tlu_asi_queue_rd_vld_g;

output tlu_ld_data_vld_g;

// output tlu_scpd_rd_vld_g;

output tlu_va_ill_g;

// output tlu_va_all_zero_g;

output tlu_lsu_int_ldxa_vld_w2;

//

// global nets

output so;

//=================================================

// input

//=================================================

// non-thread specific por reset indicator

// modified for timing

// input [1:0] ifu_tlu_thrid_e; 

input [1:0] ifu_tlu_thrid_d;

// 

// staged write asr instruction

// modified for timing 

// input tlu_wsr_inst_g;

input tlu_wsr_inst_nq_g;

// non-threaded por instruciton 

input [`TLU_THRD_NUM-1:0] tlu_por_rstint_g;

// 

// addr of sr(st/pr)

input [`TLU_ASR_ADDR_WIDTH-1:0] ifu_tlu_sraddr_d;

//

// staged pr/st data from irf.

input [`TLU_GLOBAL_WIDTH-1:0] tlu_wsr_data_w_global;

// restored global value for done/retry instructions 

input [`TSA_GLOBAL_WIDTH-1:0] tlu_dnrtry_global_g;

// thread specific done and retry signals

input tlu_dnrtry0_inst_g, tlu_dnrtry1_inst_g;

input tlu_dnrtry2_inst_g, tlu_dnrtry3_inst_g;

// 

// thread specific trap assetion signals

// modified due to timing

// input tlu_thrd0_traps, tlu_thrd1_traps;

// input tlu_thrd2_traps, tlu_thrd3_traps;

input [`TLU_THRD_NUM-1:0] tlu_thrd_traps_w2;

// 

// indicating whether the trap is supervisor or hypervisor 

// added for bug 2889

// modified due to timing

// input tlu_select_tba_g; 

input tlu_select_tba_w2;

//

input tlu_tick_ctl_din;

// htick compare match

// input tlu_htick_match;       

//

// select src for tickcmp 

input [`TLU_THRD_NUM-1:0] tlu_tickcmp_sel;

// 

// pstate - supervisor privilege  

input [`TLU_THRD_NUM-1:0] tlu_pstate_priv;

// hpstate - hypervisor privilege  

input [`TLU_THRD_NUM-1:0] tlu_hpstate_priv;

// hpstate - hypervisor lite enb  

input [`TLU_THRD_NUM-1:0] tlu_hpstate_enb;

// thread id for the agp that needs swap

// modified for timing

// input [1:0] tlu_agp_tid_g;

input [1:0] tlu_agp_tid_w2;

// ASI addresses and valid bits for decode to 

// access the ASI registers

input       ifu_lsu_alt_space_e; // valid bit for the ASI data

input       ifu_lsu_ld_inst_e;  // read enable

input       ifu_lsu_st_inst_e;  // write enable

// replaced due to timing violations

// input            tlu_nlsu_flush_w;   // trap flush 

input       tlu_local_flush_w;   // trap flush 

input       ifu_tlu_flush_fd_w;   // trap flush 

input       lsu_tlu_early_flush_w;   // trap flush 

input       tlu_asi_data_nf_vld_w2;   // trap flush 

input       tlu_inst_vld_m;     // instruciton valid 

//

// asi to be read/written

input [`TLU_ASI_STATE_WIDTH-1:0] tlu_asi_state_e;

// input [`TLU_ASI_VA_WIDTH-1:0] exu_lsu_ldst_va_e;  

input [`TLU_ASI_VA_WIDTH-1:0] lsu_tlu_ldst_va_m;

// head and tail pointers

input [`TLU_ASI_QUE_WIDTH-1:0] tlu_asi_queue_data_g;

//reset

// input tlu_rst_l;  // unit reset

input grst_l ;  // unit reset

input arst_l ;  // unit reset

input rst_tri_en ;  // unit reset

//clk

input rclk;

//

// global nets

input si, se;

/*AUTOOUTPUT*/

//

// staged thread id

wire [1:0] thrid_e, thrid_m, thrid_g;

// decoded thread id

wire [`TLU_THRD_NUM-1:0] thread_sel_id_e;

wire [`TLU_THRD_NUM-1:0] thread_sel_id_m;

wire [`TLU_THRD_NUM-1:0] thread_sel_id_g;

wire [`TLU_THRD_NUM-1:0] thread_sel_id_w2;

// 

// flush due to "early traps"

wire        local_flush_all_w;   // trap flush 

wire        local_flush_all_w2;   // trap flush 

//

// por indicators generations 

wire por_rstint0_g, por_rstint1_g;

wire por_rstint2_g, por_rstint3_g;

//

// GL register definitions - one GL register/thread

wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl0, gl_lvl1, gl_lvl2, gl_lvl3;

// updated value of the GL registers 

wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl0_new, gl_lvl1_new;

wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl2_new, gl_lvl3_new;

wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl0_update_g, gl_lvl1_update_g;

wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl2_update_g, gl_lvl3_update_g;

wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl0_update_w2, gl_lvl1_update_w2;

wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl2_update_w2, gl_lvl3_update_w2;

wire [`TSA_GLOBAL_WIDTH-1:0] wsr_gl_lvl0_data, wsr_gl_lvl1_data;

wire [`TSA_GLOBAL_WIDTH-1:0] wsr_gl_lvl2_data, wsr_gl_lvl3_data;

wire [`TSA_GLOBAL_WIDTH-1:0] dnrtry_gl_lvl0_data, dnrtry_gl_lvl1_data;

wire [`TSA_GLOBAL_WIDTH-1:0] dnrtry_gl_lvl2_data, dnrtry_gl_lvl3_data;

// value to be incremented for the GL registers

// modified due to timing

// wire gl0_incr_sel, gl1_incr_sel, gl2_incr_sel, gl3_incr_sel; 

// wire[1:0] gl_lvl0_incr, gl_lvl1_incr, gl_lvl2_incr, gl_lvl3_incr; 

// indicators to signal gl is at certain pre-defined values 

// added for timing

wire [`TLU_THRD_NUM-1:0] gl_incr_sel_w2;

wire [`TLU_THRD_NUM-1:0] gl_update_sel_g;

wire [`TLU_THRD_NUM-1:0] gl_update_sel_w2;

wire [`TLU_THRD_NUM-1:0] gl_priv_max_sel_w2;

wire gl_lvl0_at_maxgl, gl_lvl1_at_maxgl;

wire gl_lvl2_at_maxgl, gl_lvl3_at_maxgl;

wire gl_lvl0_at_maxstl, gl_lvl1_at_maxstl;

wire gl_lvl2_at_maxstl, gl_lvl3_at_maxstl;

// gl write enables  

wire gl0_en, gl1_en, gl2_en, gl3_en;

wire [`TLU_THRD_NUM-1:0] dnrtry_inst_w2;

// maxgl control

wire [`TLU_THRD_NUM-1:0] maxstl_gl_dnrtry_sel;

wire [`TLU_THRD_NUM-1:0] maxstl_gl_wr_sel;

wire [`TLU_THRD_NUM-1:0] maxgl_gl_wr_sel;

// decoded thread info for agp swap

// wire [`TLU_THRD_NUM-1:0] agp_thrid;

wire [`TLU_THRD_NUM-1:0] agp_thrid_w2;

// modified for for timing fix

// wire agp_swap; 

// wire [1:0] agp_new; 

wire wsr_inst_g, wsr_inst_w2;

wire agp_swap_w2, agp_swap_w3;

wire [1:0] agp_new_w2, agp_new_w3;

//

// hyper-privileged ASR registers

wire [`TLU_THRD_NUM-1:0] tlu_wr_hintp_g;

wire htba_rw_d, hpstate_rw_d, htstate_rw_d, hintp_rw_d;

wire htickcmp_rw_d, gl_rw_d;

wire htba_rw_e, hpstate_rw_e, htstate_rw_e, hintp_rw_e;

wire htickcmp_rw_e, gl_rw_e;

wire htba_rw_m, hpstate_rw_m, htstate_rw_m, hintp_rw_m;

wire htickcmp_rw_m, gl_rw_m;

wire htba_rw_g, hpstate_rw_g, htstate_rw_g, hintp_rw_g;

wire htickcmp_rw_g, gl_rw_g;

wire [`TLU_THRD_NUM-1:0] htickcmp_intdis_en;

wire hpstate_rw_w2;

//

// hyper-lite mode indicator

wire [`TLU_THRD_NUM-1:0] tlu_hyper_lite;

// 

// contorls to update the hpstate registers

// wire update_hpstate0_g, update_hpstate1_g;

// wire update_hpstate2_g, update_hpstate3_g;

wire [`TLU_THRD_NUM-1:0] update_hpstate_g;

wire [`TLU_THRD_NUM-1:0] update_hpstate_w2;

//

// htick interrupt disable control

wire htick_intdis0, htick_intdis1;

wire htick_intdis2, htick_intdis3;

//

// local addr of sr(st/pr) 

wire [`TLU_ASR_ADDR_WIDTH-3:0] sraddr;

// ASI_QUEUE for hyper visor

// thread 0

wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo0_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo0_tail;

wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo0_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo0_tail;

wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err0_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err0_tail;

wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err0_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err0_tail;

// thread 1

wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo1_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo1_tail;

wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo1_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo1_tail;

wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err1_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err1_tail;

wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err1_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err1_tail;

// thread 2

wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo2_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo2_tail;

wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo2_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo2_tail;

wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err2_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err2_tail;

wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err2_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err2_tail;

// thread 3

wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo3_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo3_tail;

wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo3_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo3_tail;

wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err3_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err3_tail;

wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err3_head;

wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err3_tail;

//

// read asi data from the asi queues

wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo_hd_rdata;

wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo_ta_rdata;

wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo_hd_rdata;

wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo_ta_rdata;

wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err_hd_rdata;

wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err_ta_rdata;

wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err_hd_rdata;

wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err_ta_rdata;

wire [`TLU_ASI_QUE_WIDTH-1:0] asi_queue_rdata1_g;

wire [`TLU_ASI_QUE_WIDTH-1:0] asi_queue_rdata2_g;

wire asi_qrdata_mx_sel2;

//

// head and tail comparison results

// modified due to timing violations

// wire cpu_mondo_head_rw_e,  cpu_mondo_tail_rw_e;

// wire dev_mondo_head_rw_e,  dev_mondo_tail_rw_e;

// wire resum_err_head_rw_e,  resum_err_tail_rw_e;

// wire nresum_err_head_rw_e, nresum_err_tail_rw_e;

//

wire cpu_mondo_head_rw_m,  cpu_mondo_tail_rw_m;

wire dev_mondo_head_rw_m,  dev_mondo_tail_rw_m;

wire resum_err_head_rw_m,  resum_err_tail_rw_m;

wire nresum_err_head_rw_m, nresum_err_tail_rw_m;

//

wire cpu_mondo_head_rw_g,  cpu_mondo_tail_rw_g;

wire dev_mondo_head_rw_g,  dev_mondo_tail_rw_g;

wire resum_err_head_rw_g,  resum_err_tail_rw_g;

wire nresum_err_head_rw_g, nresum_err_tail_rw_g;

// creating one-hot selects

// wire cpu_mondo_hd_onehot_g, cpu_mondo_ta_onehot_g;

// wire dev_mondo_hd_onehot_g, dev_mondo_ta_onehot_g;

// wire resum_err_hd_onehot_g, resum_err_ta_onehot_g;

// wire nresum_err_hd_onehot_g, nresum_err_ta_onehot_g;

// read 

wire [`TLU_THRD_NUM-1:0] cpu_mondo_head_rd_g;

wire cpu_mondo_hd_rd_g;

wire [`TLU_THRD_NUM-1:0] cpu_mondo_tail_rd_g;

wire cpu_mondo_ta_rd_g;

wire [`TLU_THRD_NUM-1:0] dev_mondo_head_rd_g;

wire dev_mondo_hd_rd_g;

wire [`TLU_THRD_NUM-1:0] dev_mondo_tail_rd_g;

wire dev_mondo_ta_rd_g;

wire [`TLU_THRD_NUM-1:0] resum_err_head_rd_g;

wire resum_err_hd_rd_g;

wire [`TLU_THRD_NUM-1:0] resum_err_tail_rd_g;

wire resum_err_ta_rd_g;

wire [`TLU_THRD_NUM-1:0] nresum_err_head_rd_g;

wire nresum_err_hd_rd_g;

wire [`TLU_THRD_NUM-1:0] nresum_err_tail_rd_g;

wire nresum_err_ta_rd_g;

wire [3:0] asi_qrdata_mx1_sel;

wire [3:0] asi_qrdata_mx2_sel;

// write 

wire [`TLU_THRD_NUM-1:0] cpu_mondo_head_wr_g;

wire [`TLU_THRD_NUM-1:0] cpu_mondo_tail_wr_g;

wire [`TLU_THRD_NUM-1:0] dev_mondo_head_wr_g;

wire [`TLU_THRD_NUM-1:0] dev_mondo_tail_wr_g;

wire [`TLU_THRD_NUM-1:0] resum_err_head_wr_g;

wire [`TLU_THRD_NUM-1:0] resum_err_tail_wr_g;

wire [`TLU_THRD_NUM-1:0] nresum_err_head_wr_g;

wire [`TLU_THRD_NUM-1:0] nresum_err_tail_wr_g;

// 

// ASI va address

// modified due to timing fix

// wire [`TLU_ASI_VA_WIDTH-1:0] tlu_ldst_va_e;

wire [`TLU_ASI_VA_WIDTH-1:0] tlu_ldst_va_m;

//

// ASI read or write enables

wire asi_queue_write_e;

wire asi_queue_read_e;

wire asi_queue_write_pq_m;

wire asi_queue_read_pq_m;

wire asi_queue_write_m;

wire asi_queue_read_m;

wire asi_queue_write_uf_g;

// wire asi_queue_read_uf_g;

wire asi_queue_write_g;

wire asi_queue_read_g;

//

// decoded ASI addresses 

// ASI QUE

wire asi_queue_rw_e, asi_queue_rw_m, asi_queue_rw_g;

wire asi_inrr_rw_e, asi_inrr_rw_m, asi_inrr_rw_g;

wire asi_indr_rw_e, asi_indr_rw_m, asi_indr_rw_g;

wire asi_invr_rw_e, asi_invr_rw_m, asi_invr_rw_g;

// supervisor scratch-pad asi state

wire asi_scpd_rw_e, asi_scpd_rw_m;

// hypervisor scratch-pad asi state

wire asi_hscpd_rw_e, asi_hscpd_rw_m;

wire asi_scpd_rw_vld_m, asi_scpd_rw_vld_g;

// legal va addresses

// modified due to timing

// wire que_legal_va_e;

wire que_legal_va_m;

// modified due to timing

// illegal va range indicator

// wire que_ill_va_e, 

wire que_ill_va_m, que_ill_va_g;

// modified due to timing

// wire scpd_ill_va_e, 

wire scpd_ill_va_m, scpd_ill_va_g;

// alignment checking

wire va_not_baligned_m;

// no longer necessary

// wire va_all_zero_e, va_all_zero_m, va_all_zero_g;

// write operation to queue tails 

wire qtail_write_m;

//

// data_access_exception for hyper-privileged scratch-pad

wire hscpd_data_acc_excpt_m;

wire hscpd_data_acc_excpt_pq_m;

// write to hypervisor scratch-pad using 0x20 ASI state

wire hscpd_priv_asi_acc_m;

// access hypervisor scratchpad va addresses

wire hscpd_va_rw_m;

//

// relevant portion of the va address for the scratch-pad 

// modified due to timing fix

// wire [`TLU_ASI_SCPD_VA_HI:0]       scpd_addr_va_e;

wire [`SCPD_ASI_VA_ADDR_WIDTH-1:0] scpd_addr_va_m;

wire [`SCPD_ASI_VA_ADDR_WIDTH-1:0] scpd_addr_va_g;

//

// load instruction data valid

wire asi_ld_addr_vld_m, asi_ld_addr_vld_g;

// privilege or hyper-privileged address indicators

wire asr_hyperp, asr_priv;

//

// local reset

wire local_rst_l;

wire local_rst;

// local clk

wire clk;

////////////////////////////////////////////////////////////////////////

// local reset

////////////////////////////////////////////////////////////////////////

dffrl_async dffrl_local_rst_l(

    .din  (grst_l),

    .clk  (clk),

    .rst_l(arst_l),

    .q    (local_rst_l),

    .se   (se),

    `SIMPLY_RISC_SCANIN,

    .so   ()

);

assign local_rst = ~local_rst_l;

////////////////////////////////////////////////////////////////////////

// local clock

////////////////////////////////////////////////////////////////////////

assign clk = rclk;

////////////////////////////////////////////////////////////////////////

// Hyper-lite mode indicator

////////////////////////////////////////////////////////////////////////

assign tlu_hyper_lite[0] =

           tlu_hpstate_priv[0]| (~tlu_hpstate_enb[0] & tlu_pstate_priv[0]);

assign tlu_hyper_lite[1] =

           tlu_hpstate_priv[1]| (~tlu_hpstate_enb[1] & tlu_pstate_priv[1]);

assign tlu_hyper_lite[2] =

           tlu_hpstate_priv[2]| (~tlu_hpstate_enb[2] & tlu_pstate_priv[2]);

assign tlu_hyper_lite[3] =

           tlu_hpstate_priv[3]| (~tlu_hpstate_enb[3] & tlu_pstate_priv[3]);

////////////////////////////////////////////////////////////////////////

// Thread ID staging and decoding 

////////////////////////////////////////////////////////////////////////

//

assign  thread_sel_id_e[0] = ~thrid_e[1] & ~thrid_e[0];

assign  thread_sel_id_e[1] = ~thrid_e[1] &  thrid_e[0];

assign  thread_sel_id_e[2] =  thrid_e[1] & ~thrid_e[0];

assign  thread_sel_id_e[3] =  thrid_e[1] &  thrid_e[0];

dff_s #(`TLU_THRD_NUM) dff_thread_sel_id_m (

    .din (thread_sel_id_e[`TLU_THRD_NUM-1:0]),

    .q   (thread_sel_id_m[`TLU_THRD_NUM-1:0]),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

dff_s #(`TLU_THRD_NUM) dff_thread_id_sel_g (

    .din (thread_sel_id_m[`TLU_THRD_NUM-1:0]),

    .q   (thread_sel_id_g[`TLU_THRD_NUM-1:0]),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

dff_s #(`TLU_THRD_NUM) dff_thread_id_sel_w2 (

    .din (thread_sel_id_g[`TLU_THRD_NUM-1:0]),

    .q   (thread_sel_id_w2[`TLU_THRD_NUM-1:0]),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

dff_s #(2) dff_thrid_e (

    .din (ifu_tlu_thrid_d[1:0]),

    .q   (thrid_e[1:0]),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

dff_s #(2) dff_thrid_m (

    .din (thrid_e[1:0]),

    .q   (thrid_m[1:0]),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

dff_s #(2) dff_thrid_g (

    .din (thrid_m[1:0]),

    .q   (thrid_g[1:0]),

    .clk (clk),

    .se  (se),

    `SIMPLY_RISC_SCANIN,

    .so  ()

);

//

// modified due to rte failure

assign tlu_local_thrid_g[0] = ~(|thrid_g[1:0]);

assign tlu_local_thrid_g[1] = ~thrid_g[1] &  thrid_g[0];

assign tlu_local_thrid_g[2] =  thrid_g[1] & ~thrid_g[0];

assign tlu_local_thrid_g[3] =  (&thrid_g[1:0]);

/*

assign tlu_local_thrid_g[`TLU_THRD_NUM-1:0] =

           thread_sel_id_g[`TLU_THRD_NUM-1:0];

*/